From nobody Tue Feb 10 01:35:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488512208349852.0691003108859; Thu, 2 Mar 2017 19:36:48 -0800 (PST) Received: from localhost ([::1]:55910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cje1O-00087v-QX for importer@patchew.org; Thu, 02 Mar 2017 22:36:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cjdqb-0008Ag-MZ for qemu-devel@nongnu.org; Thu, 02 Mar 2017 22:25:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cjdqX-0001PL-SE for qemu-devel@nongnu.org; Thu, 02 Mar 2017 22:25:37 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:33817) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cjdqW-0001MI-UH; Thu, 02 Mar 2017 22:25:33 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vZF1Y4GL0z9s8W; Fri, 3 Mar 2017 14:25:20 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1488511521; bh=nqfiwFSC5zGiRzmt/AerXcXsJKqpanWrEZJhEzTbTu4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LawySUJ8H9kdflNfVEhXlWgRyBA+R53IP01nwzve+KfbC+u/u8N7FJ77LNv3pFAYw O0yAmiKJl1Na5PgxRpusKq058Nrp0vaabk8ESbMUwgE7IGmNTbl2tDLScju04JMmbF PmO9Omr7PVggW2XkoFfxerZ38HoEt/xKAKHc5hSk= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 3 Mar 2017 14:25:06 +1100 Message-Id: <20170303032507.16142-17-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170303032507.16142-1-david@gibson.dropbear.id.au> References: <20170303032507.16142-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 16/17] spapr: Small cleanup of PPC MMU enums X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, mdroth@linux.vnet.ibm.com, aik@ozlabs.ru, agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, sjitindarsingh@gmail.com, sam.bobroff@au1.ibm.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Sam Bobroff The PPC MMU types are sometimes treated as if they were a bit field and sometime as if they were an enum which causes maintenance problems: flipping bits in the MMU type (which is done on both the 1TB segment and 64K segment bits) currently produces new MMU type values that are not handled in every "switch" on it, sometimes causing an abort(). This patch provides some macros that can be used to filter out the "bit field-like" bits so that the remainder of the value can be switched on, like an enum. This allows removal of all of the "degraded" types from the list and should ease maintenance. Signed-off-by: Sam Bobroff Signed-off-by: David Gibson --- hw/ppc/spapr.c | 10 +++---- target/ppc/cpu-qom.h | 12 ++++----- target/ppc/kvm.c | 8 +++--- target/ppc/mmu-hash64.c | 12 ++++----- target/ppc/mmu_helper.c | 71 ++++++++++++++++++++-------------------------= ---- target/ppc/translate.c | 14 +++++----- 6 files changed, 55 insertions(+), 72 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 81e2ada..14192ac 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -407,18 +407,16 @@ static void spapr_populate_pa_features(CPUPPCState *e= nv, void *fdt, int offset) uint8_t *pa_features; size_t pa_size; =20 - switch (env->mmu_model) { - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: + switch (POWERPC_MMU_VER(env->mmu_model)) { + case POWERPC_MMU_VER_2_06: pa_features =3D pa_features_206; pa_size =3D sizeof(pa_features_206); break; - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: + case POWERPC_MMU_VER_2_07: pa_features =3D pa_features_207; pa_size =3D sizeof(pa_features_207); break; - case POWERPC_MMU_3_00: + case POWERPC_MMU_VER_3_00: pa_features =3D pa_features_300; pa_size =3D sizeof(pa_features_300); break; diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index da7eb5a..81500e5 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -80,22 +80,22 @@ enum powerpc_mmu_t { POWERPC_MMU_2_06 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000003, - /* Architecture 2.06 "degraded" (no 1T segments) */ - POWERPC_MMU_2_06a =3D POWERPC_MMU_64 | POWERPC_MMU_AMR - | 0x00000003, /* Architecture 2.07 variant */ POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000004, - /* Architecture 2.07 "degraded" (no 1T segments) */ - POWERPC_MMU_2_07a =3D POWERPC_MMU_64 | POWERPC_MMU_AMR - | 0x00000004, /* Architecture 3.00 variant */ POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | POWERPC_MMU_V3 | 0x00000005, }; +#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) +#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B) +#define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03) +#define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06) +#define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07) +#define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00) =20 /*************************************************************************= ****/ /* Exception model = */ diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 9b51484..1adb55c 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -283,8 +283,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, info->flags |=3D KVM_PPC_1T_SEGMENTS; } =20 - if (env->mmu_model =3D=3D POWERPC_MMU_2_06 || - env->mmu_model =3D=3D POWERPC_MMU_2_07) { + if (POWERPC_MMU_VER(env->mmu_model) =3D=3D POWERPC_MMU_VER_2_06 || + POWERPC_MMU_VER(env->mmu_model) =3D=3D POWERPC_MMU_VER_2_07) { info->slb_size =3D 32; } else { info->slb_size =3D 64; @@ -298,8 +298,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, i++; =20 /* 64K on MMU 2.06 and later */ - if (env->mmu_model =3D=3D POWERPC_MMU_2_06 || - env->mmu_model =3D=3D POWERPC_MMU_2_07) { + if (POWERPC_MMU_VER(env->mmu_model) =3D=3D POWERPC_MMU_VER_2_06 || + POWERPC_MMU_VER(env->mmu_model) =3D=3D POWERPC_MMU_VER_2_07) { info->sps[i].page_shift =3D 16; info->sps[i].slb_enc =3D 0x110; info->sps[i].enc[0].page_shift =3D 16; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d5a871f..14d34e5 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1032,8 +1032,8 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong= val) uint64_t lpcr =3D 0; =20 /* Filter out bits */ - switch (env->mmu_model) { - case POWERPC_MMU_64B: /* 970 */ + switch (POWERPC_MMU_VER(env->mmu_model)) { + case POWERPC_MMU_VER_64B: /* 970 */ if (val & 0x40) { lpcr |=3D LPCR_LPES0; } @@ -1059,26 +1059,26 @@ void helper_store_lpcr(CPUPPCState *env, target_ulo= ng val) * to dig HRMOR out of HID5 */ break; - case POWERPC_MMU_2_03: /* P5p */ + case POWERPC_MMU_VER_2_03: /* P5p */ lpcr =3D val & (LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | LPCR_RMI | LPCR_HDICE); break; - case POWERPC_MMU_2_06: /* P7 */ + case POWERPC_MMU_VER_2_06: /* P7 */ lpcr =3D val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); break; - case POWERPC_MMU_2_07: /* P8 */ + case POWERPC_MMU_VER_2_07: /* P8 */ lpcr =3D val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); break; - case POWERPC_MMU_3_00: /* P9 */ + case POWERPC_MMU_VER_3_00: /* P9 */ lpcr =3D val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL= | LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 18a76d2..65d1c86 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1266,7 +1266,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function= cpu_fprintf, =20 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) { - switch (env->mmu_model) { + switch (POWERPC_MMU_VER(env->mmu_model)) { case POWERPC_MMU_BOOKE: mmubooke_dump_mmu(f, cpu_fprintf, env); break; @@ -1278,15 +1278,13 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf= , CPUPPCState *env) mmu6xx_dump_mmu(f, cpu_fprintf, env); break; #if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: + case POWERPC_MMU_VER_64B: + case POWERPC_MMU_VER_2_03: + case POWERPC_MMU_VER_2_06: + case POWERPC_MMU_VER_2_07: dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); break; - case POWERPC_MMU_3_00: + case POWERPC_MMU_VER_3_00: if (ppc64_radix_guest(ppc_env_get_cpu(env))) { /* TODO - Unsupported */ } else { @@ -1425,16 +1423,14 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) CPUPPCState *env =3D &cpu->env; mmu_ctx_t ctx; =20 - switch (env->mmu_model) { + switch (POWERPC_MMU_VER(env->mmu_model)) { #if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: + case POWERPC_MMU_VER_64B: + case POWERPC_MMU_VER_2_03: + case POWERPC_MMU_VER_2_06: + case POWERPC_MMU_VER_2_07: return ppc_hash64_get_phys_page_debug(cpu, addr); - case POWERPC_MMU_3_00: + case POWERPC_MMU_VER_3_00: if (ppc64_radix_guest(ppc_env_get_cpu(env))) { /* TODO - Unsupported */ } else { @@ -1924,6 +1920,12 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) { PowerPCCPU *cpu =3D ppc_env_get_cpu(env); =20 +#if defined(TARGET_PPC64) + if (env->mmu_model & POWERPC_MMU_64) { + env->tlb_need_flush =3D 0; + tlb_flush(CPU(cpu)); + } else +#endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: @@ -1948,21 +1950,12 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) break; case POWERPC_MMU_32B: case POWERPC_MMU_601: -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: - case POWERPC_MMU_3_00: -#endif /* defined(TARGET_PPC64) */ env->tlb_need_flush =3D 0; tlb_flush(CPU(cpu)); break; default: /* XXX: TODO */ - cpu_abort(CPU(cpu), "Unknown MMU model %d\n", env->mmu_model); + cpu_abort(CPU(cpu), "Unknown MMU model %x\n", env->mmu_model); break; } } @@ -1971,6 +1964,16 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target= _ulong addr) { #if !defined(FLUSH_ALL_TLBS) addr &=3D TARGET_PAGE_MASK; +#if defined(TARGET_PPC64) + if (env->mmu_model & POWERPC_MMU_64) { + /* tlbie invalidate TLBs for all segments */ + /* XXX: given the fact that there are too many segments to invalid= ate, + * and we still don't have a tlb_flush_mask(env, n, mask) in = QEMU, + * we just invalidate all TLBs + */ + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; + } else +#endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: @@ -1988,22 +1991,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target= _ulong addr) */ env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; break; -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: - case POWERPC_MMU_3_00: - /* tlbie invalidate TLBs for all segments */ - /* XXX: given the fact that there are too many segments to invalid= ate, - * and we still don't have a tlb_flush_mask(env, n, mask) in = QEMU, - * we just invalidate all TLBs - */ - env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; - break; -#endif /* defined(TARGET_PPC64) */ default: /* Should never reach here with other MMU models */ assert(0); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 1de554a..b6abc60 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7078,19 +7078,17 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, if (env->spr_cb[SPR_LPCR].name) cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); =20 - switch (env->mmu_model) { + switch (POWERPC_MMU_VER(env->mmu_model)) { case POWERPC_MMU_32B: case POWERPC_MMU_601: case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: #if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: - case POWERPC_MMU_3_00: + case POWERPC_MMU_VER_64B: + case POWERPC_MMU_VER_2_03: + case POWERPC_MMU_VER_2_06: + case POWERPC_MMU_VER_2_07: + case POWERPC_MMU_VER_3_00: #endif if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); --=20 2.9.3