From nobody Tue Feb 10 06:27:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 14885120396611023.4771955018861; Thu, 2 Mar 2017 19:33:59 -0800 (PST) Received: from localhost ([::1]:55887 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cjdyg-0005kW-Ds for importer@patchew.org; Thu, 02 Mar 2017 22:33:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44240) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cjdqV-00083z-Kp for qemu-devel@nongnu.org; Thu, 02 Mar 2017 22:25:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cjdqU-0001MV-Cz for qemu-devel@nongnu.org; Thu, 02 Mar 2017 22:25:31 -0500 Received: from ozlabs.org ([103.22.144.67]:35599) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cjdqU-0001I8-0O; Thu, 02 Mar 2017 22:25:30 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vZF1W6m2zz9s83; Fri, 3 Mar 2017 14:25:19 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1488511519; bh=gBT+HJ20uq3UgRFbRRwFh+B/w4OpUryW1clIFpIT+Mk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W4hZ1gtWLNe2qIGRBioISbkQGfDOO7113MtUTRVTTQAPaSZiWSfP5M+bfc8AEXuBC gzCTmm8Jrn/UUHDXt7M+C8BxyiAuxuOdiEYK7Js0QXU1hwE96/41R9jwYbG9D+dnPu z0ZbAQUnPFqhqFxpXMzA1eSmswxR2BQ7adnGKByo= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 3 Mar 2017 14:25:03 +1100 Message-Id: <20170303032507.16142-14-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170303032507.16142-1-david@gibson.dropbear.id.au> References: <20170303032507.16142-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 13/17] target/ppc: Move no-execute and guarded page checking into new function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, mdroth@linux.vnet.ibm.com, aik@ozlabs.ru, agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, sjitindarsingh@gmail.com, sam.bobroff@au1.ibm.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Suraj Jitindar Singh A pte entry has bit fields which can be used to make a page no-execute or guarded, if either of these bits are set then an instruction access to this page will fail. Currently these bits are checked with the pp_prot function however the ISA specifies that the access authority controlled by the key-pp value pair should only be checked on an instruction access after the no-execute and guard bits have already been verified to permit the access. Move the no-execute and guard bit checking into a new separate function. Note that we can remove the check for the no-execute bit in the slb entry since this check was already performed above when we obtained the slb entry. In the event that the no-execute or guard bits are set, an ISI should be generated with the SRR1_NOEXEC_GUARD (0x10000000) bit set in srr1. Add a define for this for clarity. Signed-off-by: Suraj Jitindar Singh [dwg: Move constants to cpu.h since they're not MMUv3 specific] Signed-off-by: David Gibson --- target/ppc/cpu.h | 1 + target/ppc/mmu-hash64.c | 25 ++++++++++++++++--------- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 42fed6e..14c286e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -475,6 +475,7 @@ struct ppc_slb_t { =20 /* SRR1 error code fields */ =20 +#define SRR1_NOEXEC_GUARD 0x10000000 #define SRR1_PROTFAULT 0x08000000 #define SRR1_IAMR 0x00200000 =20 diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 99f936d..d985617 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -290,6 +290,16 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, ta= rget_ulong rb) return rt; } =20 +/* Check No-Execute or Guarded Storage */ +static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu, + ppc_hash_pte64_t pte) +{ + /* Exec permissions CANNOT take away read or write permissions */ + return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ? + PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC; +} + +/* Check Basic Storage Protection */ static int ppc_hash64_pte_prot(PowerPCCPU *cpu, ppc_slb_t *slb, ppc_hash_pte64_t pte) { @@ -333,12 +343,6 @@ static int ppc_hash64_pte_prot(PowerPCCPU *cpu, } } =20 - /* No execute if either noexec or guarded bits set */ - if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) - || (slb->vsid & SLB_VSID_N)) { - prot |=3D PAGE_EXEC; - } - return prot; } =20 @@ -696,7 +700,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, unsigned apshift; hwaddr ptex; ppc_hash_pte64_t pte; - int pp_prot, amr_prot, prot; + int exec_prot, pp_prot, amr_prot, prot; uint64_t new_pte1, dsisr; const int need_prot[] =3D {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; hwaddr raddr; @@ -803,16 +807,19 @@ skip_slb_search: =20 /* 5. Check access permissions */ =20 + exec_prot =3D ppc_hash64_pte_noexec_guard(cpu, pte); pp_prot =3D ppc_hash64_pte_prot(cpu, slb, pte); amr_prot =3D ppc_hash64_amr_prot(cpu, pte); - prot =3D pp_prot & amr_prot; + prot =3D exec_prot & pp_prot & amr_prot; =20 if ((need_prot[rwx] & ~prot) !=3D 0) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); if (rwx =3D=3D 2) { int srr1 =3D 0; - if (PAGE_EXEC & ~pp_prot) { + if (PAGE_EXEC & ~exec_prot) { + srr1 |=3D SRR1_NOEXEC_GUARD; /* Access violates noexec or = guard */ + } else if (PAGE_EXEC & ~pp_prot) { srr1 |=3D SRR1_PROTFAULT; /* Access violates access author= ity */ } if (PAGE_EXEC & ~amr_prot) { --=20 2.9.3