From nobody Thu Nov 6 19:13:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488343731211199.92594127195673; Tue, 28 Feb 2017 20:48:51 -0800 (PST) Received: from localhost ([::1]:38352 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciwC2-0002gu-0W for importer@patchew.org; Tue, 28 Feb 2017 23:48:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciw7k-0007ws-5D for qemu-devel@nongnu.org; Tue, 28 Feb 2017 23:44:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ciw7h-0008UT-NJ for qemu-devel@nongnu.org; Tue, 28 Feb 2017 23:44:24 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:42107) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ciw7g-0008SM-U2; Tue, 28 Feb 2017 23:44:21 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vY2sR1Qnrz9sN4; Wed, 1 Mar 2017 15:44:10 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1488343451; bh=Qfw5yAazRygQroGoxoGvCLav+AjOVCRh608jXU5kTmw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=STXAyBmLXNvJ9iNPFYR07/+f1i8Tz21sPehNWZTOvIm5BGd7tHvs+TsCqlqobvpBG +6yMljnPCbACK2B1fYzDLWgJCn0x/t34neCWFMeb+iiKwbly4PQVNCgnqpsRenfJZk INVX0xgmpqYRY+nK3qAhOX8AKmGx/W3MvLYtoeWY= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 1 Mar 2017 15:43:23 +1100 Message-Id: <20170301044405.1792-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170301044405.1792-1-david@gibson.dropbear.id.au> References: <20170301044405.1792-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 08/50] pseries: Minor cleanups to HPT management hypercalls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com, agraf@suse.de, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" * Standardize on 'ptex' instead of 'pte_index' for HPTE index variables for consistency and brevity * Avoid variables named 'index'; shadowing index(3) from libc can lead to surprising bugs if the variable is removed, because compiler errors might not appear for remaining references * Clarify index calculations in h_enter() - we have two cases, H_EXACT where the exact HPTE slot is given, and !H_EXACT where we search for an empty slot within the hash bucket. Make the calculation more consistent between the cases. Signed-off-by: David Gibson Reviewed-by: Suraj Jitindar Singh --- hw/ppc/spapr_hcall.c | 58 +++++++++++++++++++++++++-----------------------= ---- 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 42d20e0..3298a14 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -47,12 +47,12 @@ static bool has_spr(PowerPCCPU *cpu, int spr) return cpu->env.spr_cb[spr].name !=3D NULL; } =20 -static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_inde= x) +static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) { /* * hash value/pteg group index is normalized by htab_mask */ - if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) { + if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~cpu->env.htab_mask) { return false; } return true; @@ -77,14 +77,13 @@ static bool is_ram_address(sPAPRMachineState *spapr, hw= addr addr) static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - CPUPPCState *env =3D &cpu->env; target_ulong flags =3D args[0]; - target_ulong pte_index =3D args[1]; + target_ulong ptex =3D args[1]; target_ulong pteh =3D args[2]; target_ulong ptel =3D args[3]; unsigned apshift; target_ulong raddr; - target_ulong index; + target_ulong slot; uint64_t token; =20 apshift =3D ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); @@ -116,25 +115,26 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMac= hineState *spapr, =20 pteh &=3D ~0x60ULL; =20 - if (!valid_pte_index(env, pte_index)) { + if (!valid_ptex(cpu, ptex)) { return H_PARAMETER; } =20 - index =3D 0; + slot =3D ptex & 7ULL; + ptex =3D ptex & ~7ULL; + if (likely((flags & H_EXACT) =3D=3D 0)) { - pte_index &=3D ~7ULL; - token =3D ppc_hash64_start_access(cpu, pte_index); - for (; index < 8; index++) { - if (!(ppc_hash64_load_hpte0(cpu, token, index) & HPTE64_V_VALI= D)) { + token =3D ppc_hash64_start_access(cpu, ptex); + for (slot =3D 0; slot < 8; slot++) { + if (!(ppc_hash64_load_hpte0(cpu, token, slot) & HPTE64_V_VALID= )) { break; } } ppc_hash64_stop_access(cpu, token); - if (index =3D=3D 8) { + if (slot =3D=3D 8) { return H_PTEG_FULL; } } else { - token =3D ppc_hash64_start_access(cpu, pte_index); + token =3D ppc_hash64_start_access(cpu, ptex); if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) { ppc_hash64_stop_access(cpu, token); return H_PTEG_FULL; @@ -142,10 +142,9 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMach= ineState *spapr, ppc_hash64_stop_access(cpu, token); } =20 - ppc_hash64_store_hpte(cpu, pte_index + index, - pteh | HPTE64_V_HPTE_DIRTY, ptel); + ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, pt= el); =20 - args[0] =3D pte_index + index; + args[0] =3D ptex + slot; return H_SUCCESS; } =20 @@ -161,11 +160,10 @@ static RemoveResult remove_hpte(PowerPCCPU *cpu, targ= et_ulong ptex, target_ulong flags, target_ulong *vp, target_ulong *rp) { - CPUPPCState *env =3D &cpu->env; uint64_t token; target_ulong v, r; =20 - if (!valid_pte_index(env, ptex)) { + if (!valid_ptex(cpu, ptex)) { return REMOVE_PARM; } =20 @@ -191,11 +189,11 @@ static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMa= chineState *spapr, { CPUPPCState *env =3D &cpu->env; target_ulong flags =3D args[0]; - target_ulong pte_index =3D args[1]; + target_ulong ptex =3D args[1]; target_ulong avpn =3D args[2]; RemoveResult ret; =20 - ret =3D remove_hpte(cpu, pte_index, avpn, flags, + ret =3D remove_hpte(cpu, ptex, avpn, flags, &args[0], &args[1]); =20 switch (ret) { @@ -291,16 +289,16 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRM= achineState *spapr, { CPUPPCState *env =3D &cpu->env; target_ulong flags =3D args[0]; - target_ulong pte_index =3D args[1]; + target_ulong ptex =3D args[1]; target_ulong avpn =3D args[2]; uint64_t token; target_ulong v, r; =20 - if (!valid_pte_index(env, pte_index)) { + if (!valid_ptex(cpu, ptex)) { return H_PARAMETER; } =20 - token =3D ppc_hash64_start_access(cpu, pte_index); + token =3D ppc_hash64_start_access(cpu, ptex); v =3D ppc_hash64_load_hpte0(cpu, token, 0); r =3D ppc_hash64_load_hpte1(cpu, token, 0); ppc_hash64_stop_access(cpu, token); @@ -315,13 +313,13 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRM= achineState *spapr, r |=3D (flags << 55) & HPTE64_R_PP0; r |=3D (flags << 48) & HPTE64_R_KEY_HI; r |=3D flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); - ppc_hash64_store_hpte(cpu, pte_index, + ppc_hash64_store_hpte(cpu, ptex, (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); - ppc_hash64_tlb_flush_hpte(cpu, pte_index, v, r); + ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); /* Flush the tlb */ check_tlb_flush(env, true); /* Don't need a memory barrier, due to qemu's global lock */ - ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r); + ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); return H_SUCCESS; } =20 @@ -330,21 +328,21 @@ static target_ulong h_read(PowerPCCPU *cpu, sPAPRMach= ineState *spapr, { CPUPPCState *env =3D &cpu->env; target_ulong flags =3D args[0]; - target_ulong pte_index =3D args[1]; + target_ulong ptex =3D args[1]; uint8_t *hpte; int i, ridx, n_entries =3D 1; =20 - if (!valid_pte_index(env, pte_index)) { + if (!valid_ptex(cpu, ptex)) { return H_PARAMETER; } =20 if (flags & H_READ_4) { /* Clear the two low order bits */ - pte_index &=3D ~(3ULL); + ptex &=3D ~(3ULL); n_entries =3D 4; } =20 - hpte =3D env->external_htab + (pte_index * HASH_PTE_SIZE_64); + hpte =3D env->external_htab + (ptex * HASH_PTE_SIZE_64); =20 for (i =3D 0, ridx =3D 0; i < n_entries; i++) { args[ridx++] =3D ldq_p(hpte); --=20 2.9.3