From nobody Thu Nov 6 19:13:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488343960114217.3121042681655; Tue, 28 Feb 2017 20:52:40 -0800 (PST) Received: from localhost ([::1]:38374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciwFi-0005yT-RG for importer@patchew.org; Tue, 28 Feb 2017 23:52:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciw7l-0007yT-GI for qemu-devel@nongnu.org; Tue, 28 Feb 2017 23:44:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ciw7i-0008VY-R8 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 23:44:25 -0500 Received: from ozlabs.org ([103.22.144.67]:52611) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ciw7i-0008TI-85; Tue, 28 Feb 2017 23:44:22 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vY2sR4Tyhz9sNb; Wed, 1 Mar 2017 15:44:11 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1488343451; bh=cilhdPUTKKhpLOz2sB07FpOpWWloo0mHdEdmOq7Tz5E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IJ898xJDkaz0U7377pWITeli04hjEQ9yO4qx7YF+TNCM1Eyr5OvNWPmDMPivfWQYr Cr9BA+h5R0wJixXfgrjokcQT3KVI50MUPZpVwN+5GQtNZTtaN8KK+HWSlH3hZk+Tac DRWGYQ2oE7WsL8fjtgTEUdkftYfVZxOdwsbpb2Gk= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 1 Mar 2017 15:43:31 +1100 Message-Id: <20170301044405.1792-17-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170301044405.1792-1-david@gibson.dropbear.id.au> References: <20170301044405.1792-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 16/50] target/ppc: support for 32-bit carry and overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, Nikunj A Dadhania , aik@ozlabs.ru, mdroth@linux.vnet.ibm.com, agraf@suse.de, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Nikunj A Dadhania POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags and corresponding defines. Moreover, CA32 is updated when CA is updated and OV32 is updated when OV is updated. Arithmetic instructions: * Addition and Substractions: addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme, addze, and subfze always updates CA and CA32. =3D> CA reflects the carry out of bit 0 in 64-bit mode and out of bit 32 in 32-bit mode. =3D> CA32 reflects the carry out of bit 32 independent of the mode. =3D> SO and OV reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode =3D> OV32 reflects overflow of the low-order 32-bit independent of the mode * Multiply Low and Divide: For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits reflects overflow of the 64-bit result For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits reflects overflow of the 32-bit result * Negate with OE=3D1 (nego) For 64-bit mode if the register RA contains 0x8000_0000_0000_0000, OV and OV32 are set to 1. For 32-bit mode if the register RA contains 0x8000_0000, OV and OV32 are set to 1. Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/cpu.c | 13 ++++++++++++- target/ppc/cpu.h | 7 +++++++ target/ppc/translate.c | 21 ++++++++++++++++++--- target/ppc/translate_init.c | 2 +- 4 files changed, 38 insertions(+), 5 deletions(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index de3004b..2801166 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -23,6 +23,12 @@ =20 target_ulong cpu_read_xer(CPUPPCState *env) { + if (is_isa300(env)) { + return env->xer | (env->so << XER_SO) | + (env->ov << XER_OV) | (env->ca << XER_CA) | + (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); + } + return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA); } @@ -32,5 +38,10 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer) env->so =3D (xer >> XER_SO) & 1; env->ov =3D (xer >> XER_OV) & 1; env->ca =3D (xer >> XER_CA) & 1; - env->xer =3D xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)); + /* write all the flags, while reading back check of isa300 */ + env->ov32 =3D (xer >> XER_OV32) & 1; + env->ca32 =3D (xer >> XER_CA32) & 1; + env->xer =3D xer & ~((1ul << XER_SO) | + (1ul << XER_OV) | (1ul << XER_CA) | + (1ul << XER_OV32) | (1ul << XER_CA32)); } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4e7fc2c..420e6d6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -958,6 +958,8 @@ struct CPUPPCState { target_ulong so; target_ulong ov; target_ulong ca; + target_ulong ov32; + target_ulong ca32; /* Reservation address */ target_ulong reserve_addr; /* Reservation value */ @@ -1367,11 +1369,15 @@ int ppc_compat_max_threads(PowerPCCPU *cpu); #define XER_SO 31 #define XER_OV 30 #define XER_CA 29 +#define XER_OV32 19 +#define XER_CA32 18 #define XER_CMP 8 #define XER_BC 0 #define xer_so (env->so) #define xer_ov (env->ov) #define xer_ca (env->ca) +#define xer_ov32 (env->ov) +#define xer_ca32 (env->ca) #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) #define xer_bc ((env->xer >> XER_BC) & 0x7F) =20 @@ -2338,6 +2344,7 @@ enum { =20 /*************************************************************************= ****/ =20 +#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) target_ulong cpu_read_xer(CPUPPCState *env); void cpu_write_xer(CPUPPCState *env, target_ulong xer); =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b09e16f..be7378b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -71,7 +71,7 @@ static TCGv cpu_lr; #if defined(TARGET_PPC64) static TCGv cpu_cfar; #endif -static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; +static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; @@ -173,6 +173,10 @@ void ppc_translate_init(void) offsetof(CPUPPCState, ov), "OV"); cpu_ca =3D tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, ca), "CA"); + cpu_ov32 =3D tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, ov32), "OV32"); + cpu_ca32 =3D tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, ca32), "CA32"); =20 cpu_reserve =3D tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, reserve_addr), @@ -3703,7 +3707,7 @@ static void gen_tdi(DisasContext *ctx) =20 /*** Processor control = ***/ =20 -static void gen_read_xer(TCGv dst) +static void gen_read_xer(DisasContext *ctx, TCGv dst) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -3715,6 +3719,12 @@ static void gen_read_xer(TCGv dst) tcg_gen_or_tl(t0, t0, t1); tcg_gen_or_tl(dst, dst, t2); tcg_gen_or_tl(dst, dst, t0); + if (is_isa300(ctx)) { + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); + tcg_gen_or_tl(dst, dst, t0); + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); + tcg_gen_or_tl(dst, dst, t0); + } tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free(t2); @@ -3722,8 +3732,13 @@ static void gen_read_xer(TCGv dst) =20 static void gen_write_xer(TCGv src) { + /* Write all flags, while reading back check for isa300 */ tcg_gen_andi_tl(cpu_xer, src, - ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); + ~((1u << XER_SO) | + (1u << XER_OV) | (1u << XER_OV32) | + (1u << XER_CA) | (1u << XER_CA32))); + tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); + tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index c92435d..4dd1e36 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -107,7 +107,7 @@ static void spr_access_nop(DisasContext *ctx, int sprn,= int gprn) /* XER */ static void spr_read_xer (DisasContext *ctx, int gprn, int sprn) { - gen_read_xer(cpu_gpr[gprn]); + gen_read_xer(ctx, cpu_gpr[gprn]); } =20 static void spr_write_xer (DisasContext *ctx, int sprn, int gprn) --=20 2.9.3