From nobody Mon May 6 09:32:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488303392420248.568060017535; Tue, 28 Feb 2017 09:36:32 -0800 (PST) Received: from localhost ([::1]:35891 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilhM-0001Sx-2e for importer@patchew.org; Tue, 28 Feb 2017 12:36:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43805) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilPl-0003I8-9b for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cilPi-0003hV-46 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:17 -0500 Received: from clearmind.me ([178.32.49.9]:43757) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cilPh-0003gI-Qr for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=clearmind.me; s=dkim; h=Sender:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=wCpY6ifZNTMRX9LAmDmKKR3w3LDVc4QD2d1jfG2CK7E=; b=S3/k+KifYn8hwSUydiFQ1kT/r V58CWZI7TLwmPqVQKiaC6HI1mn9eB7Vh3XtIgwcJnx1evana/UvJu1SWFFkje/rc1tAYnP+cs0FZ4 R4jLJR18sgs+N3bzcv8YK5zcwbxxp/PhgAm8aLJpdSqtuYhkArIua/kugRdbmsCwT7+Ps=; From: Alessandro Di Federico To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 18:19:15 +0100 Message-Id: <20170228171921.21602-2-ale+qemu@clearmind.me> In-Reply-To: <20170228171921.21602-1-ale+qemu@clearmind.me> References: <20170228171921.21602-1-ale+qemu@clearmind.me> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.49.9 Subject: [Qemu-devel] [PATCH 1/7] Factor out linux-user/qemu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A quite large part of {linux,bsd}-user/qemu.h is shared, this patch introduces qemu-user-common.h which factors it out from linux-user. This shared part is also the bare minimum required to build a *-user-like target, and, in particular, it will be useful for the libtcg targets. At this point we don't factor out this code from bsd-user since currently it's not in a stable shape, and verifying if these changes affect its functionality is non-trivial. Once bsd-user will be back in a working shape, we can proceed factoring its code out. --- include/qemu-user-common.h | 180 +++++++++++++++++++++++++++++++++++++++++= ++++ linux-user/qemu.h | 176 +----------------------------------------= --- 2 files changed, 181 insertions(+), 175 deletions(-) create mode 100644 include/qemu-user-common.h diff --git a/include/qemu-user-common.h b/include/qemu-user-common.h new file mode 100644 index 0000000000..349dd72fff --- /dev/null +++ b/include/qemu-user-common.h @@ -0,0 +1,180 @@ +#ifndef QEMU_USER_COMMON_H +#define QEMU_USER_COMMON_H + +#include "cpu.h" +#include "exec/cpu_ldst.h" + +/* user access */ + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 /* implies read access */ + +static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +{ + return page_check_range((target_ulong)addr, size, + (type =3D=3D VERIFY_READ) ? PAGE_READ : (PAGE_= READ | PAGE_WRITE)) =3D=3D 0; +} + +/* NOTE __get_user and __put_user use host pointers and don't check access. + These are usually used to access struct data members once the struct has + been locked - usually with lock_user_struct. */ + +/* Tricky points: + - Use __builtin_choose_expr to avoid type promotion from ?:, + - Invalid sizes result in a compile time error stemming from + the fact that abort has no parameters. + - It's easier to use the endian-specific unaligned load/store + functions than host-endian unaligned load/store plus tswapN. */ + +#define __put_user_e(x, hptr, e) \ + (__builtin_choose_expr(sizeof(*(hptr)) =3D=3D 1, stb_p, = \ + __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 2, stw_##e##_p, = \ + __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 4, stl_##e##_p, = \ + __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 8, stq_##e##_p, abort)))) = \ + ((hptr), (x)), (void)0) + +#define __get_user_e(x, hptr, e) \ + ((x) =3D (typeof(*hptr))( \ + __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 1, ldub_p, = \ + __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 2, lduw_##e##_p, = \ + __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 4, ldl_##e##_p, = \ + __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 8, ldq_##e##_p, abort)))) = \ + (hptr)), (void)0) + +#ifdef TARGET_WORDS_BIGENDIAN +# define __put_user(x, hptr) __put_user_e(x, hptr, be) +# define __get_user(x, hptr) __get_user_e(x, hptr, be) +#else +# define __put_user(x, hptr) __put_user_e(x, hptr, le) +# define __get_user(x, hptr) __get_user_e(x, hptr, le) +#endif + +/* put_user()/get_user() take a guest address and check access */ +/* These are usually used to access an atomic data type, such as an int, + * that has been passed by address. These internally perform locking + * and unlocking on the data type. + */ +#define put_user(x, gaddr, target_type) \ +({ \ + abi_ulong __gaddr =3D (gaddr); \ + target_type *__hptr; \ + abi_long __ret =3D 0; \ + if ((__hptr =3D lock_user(VERIFY_WRITE, __gaddr, sizeof(target_type), = 0))) { \ + __put_user((x), __hptr); \ + unlock_user(__hptr, __gaddr, sizeof(target_type)); \ + } else \ + __ret =3D -TARGET_EFAULT; \ + __ret; \ +}) + +#define get_user(x, gaddr, target_type) \ +({ \ + abi_ulong __gaddr =3D (gaddr); \ + target_type *__hptr; \ + abi_long __ret =3D 0; \ + if ((__hptr =3D lock_user(VERIFY_READ, __gaddr, sizeof(target_type), 1= ))) { \ + __get_user((x), __hptr); \ + unlock_user(__hptr, __gaddr, 0); \ + } else { \ + /* avoid warning */ \ + (x) =3D 0; \ + __ret =3D -TARGET_EFAULT; \ + } \ + __ret; \ +}) + +#define put_user_ual(x, gaddr) put_user((x), (gaddr), abi_ulong) +#define put_user_sal(x, gaddr) put_user((x), (gaddr), abi_long) +#define put_user_u64(x, gaddr) put_user((x), (gaddr), uint64_t) +#define put_user_s64(x, gaddr) put_user((x), (gaddr), int64_t) +#define put_user_u32(x, gaddr) put_user((x), (gaddr), uint32_t) +#define put_user_s32(x, gaddr) put_user((x), (gaddr), int32_t) +#define put_user_u16(x, gaddr) put_user((x), (gaddr), uint16_t) +#define put_user_s16(x, gaddr) put_user((x), (gaddr), int16_t) +#define put_user_u8(x, gaddr) put_user((x), (gaddr), uint8_t) +#define put_user_s8(x, gaddr) put_user((x), (gaddr), int8_t) + +#define get_user_ual(x, gaddr) get_user((x), (gaddr), abi_ulong) +#define get_user_sal(x, gaddr) get_user((x), (gaddr), abi_long) +#define get_user_u64(x, gaddr) get_user((x), (gaddr), uint64_t) +#define get_user_s64(x, gaddr) get_user((x), (gaddr), int64_t) +#define get_user_u32(x, gaddr) get_user((x), (gaddr), uint32_t) +#define get_user_s32(x, gaddr) get_user((x), (gaddr), int32_t) +#define get_user_u16(x, gaddr) get_user((x), (gaddr), uint16_t) +#define get_user_s16(x, gaddr) get_user((x), (gaddr), int16_t) +#define get_user_u8(x, gaddr) get_user((x), (gaddr), uint8_t) +#define get_user_s8(x, gaddr) get_user((x), (gaddr), int8_t) + +/* copy_from_user() and copy_to_user() are usually used to copy data + * buffers between the target and host. These internally perform + * locking/unlocking of the memory. + */ +abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len); +abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len); + +/* Functions for accessing guest memory. The tget and tput functions + read/write single values, byteswapping as necessary. The lock_user fun= ction + gets a pointer to a contiguous area of guest memory, but does not perfo= rm + any byteswapping. lock_user may return either a pointer to the guest + memory, or a temporary buffer. */ + +/* Lock an area of guest memory into the host. If copy is true then the + host area will have the same contents as the guest. */ +static inline void *lock_user(int type, abi_ulong guest_addr, long len, in= t copy) +{ + if (!access_ok(type, guest_addr, len)) + return NULL; +#ifdef DEBUG_REMAP + { + void *addr; + addr =3D g_malloc(len); + if (copy) + memcpy(addr, g2h(guest_addr), len); + else + memset(addr, 0, len); + return addr; + } +#else + return g2h(guest_addr); +#endif +} + +/* Unlock an area of guest memory. The first LEN bytes must be + flushed back to guest memory. host_ptr =3D NULL is explicitly + allowed and does nothing. */ +static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, + long len) +{ + +#ifdef DEBUG_REMAP + if (!host_ptr) + return; + if (host_ptr =3D=3D g2h(guest_addr)) + return; + if (len > 0) + memcpy(g2h(guest_addr), host_ptr, len); + g_free(host_ptr); +#endif +} + +/* Return the length of a string in target memory or -TARGET_EFAULT if + access error. */ +abi_long target_strlen(abi_ulong gaddr); + +/* Like lock_user but for null terminated strings. */ +static inline void *lock_user_string(abi_ulong guest_addr) +{ + abi_long len; + len =3D target_strlen(guest_addr); + if (len < 0) + return NULL; + return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); +} + +/* Helper macros for locking/unlocking a target struct. */ +#define lock_user_struct(type, host_ptr, guest_addr, copy) \ + (host_ptr =3D lock_user(type, guest_addr, sizeof(*host_ptr), copy)) +#define unlock_user_struct(host_ptr, guest_addr, copy) \ + unlock_user(host_ptr, guest_addr, (copy) ? sizeof(*host_ptr) : 0) + +#endif /* QEMU_USER_COMMON_H */ diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 4edd7d0c08..22b0ad7d30 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -2,9 +2,8 @@ #define QEMU_H =20 #include "hostdep.h" -#include "cpu.h" +#include "qemu-user-common.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" =20 #undef DEBUG_REMAP #ifdef DEBUG_REMAP @@ -439,179 +438,6 @@ void mmap_fork_end(int child); /* main.c */ extern unsigned long guest_stack_size; =20 -/* user access */ - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ - -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) -{ - return page_check_range((target_ulong)addr, size, - (type =3D=3D VERIFY_READ) ? PAGE_READ : (PAGE_= READ | PAGE_WRITE)) =3D=3D 0; -} - -/* NOTE __get_user and __put_user use host pointers and don't check access. - These are usually used to access struct data members once the struct has - been locked - usually with lock_user_struct. */ - -/* Tricky points: - - Use __builtin_choose_expr to avoid type promotion from ?:, - - Invalid sizes result in a compile time error stemming from - the fact that abort has no parameters. - - It's easier to use the endian-specific unaligned load/store - functions than host-endian unaligned load/store plus tswapN. */ - -#define __put_user_e(x, hptr, e) \ - (__builtin_choose_expr(sizeof(*(hptr)) =3D=3D 1, stb_p, = \ - __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 2, stw_##e##_p, = \ - __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 4, stl_##e##_p, = \ - __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 8, stq_##e##_p, abort)))) = \ - ((hptr), (x)), (void)0) - -#define __get_user_e(x, hptr, e) \ - ((x) =3D (typeof(*hptr))( \ - __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 1, ldub_p, = \ - __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 2, lduw_##e##_p, = \ - __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 4, ldl_##e##_p, = \ - __builtin_choose_expr(sizeof(*(hptr)) =3D=3D 8, ldq_##e##_p, abort)))) = \ - (hptr)), (void)0) - -#ifdef TARGET_WORDS_BIGENDIAN -# define __put_user(x, hptr) __put_user_e(x, hptr, be) -# define __get_user(x, hptr) __get_user_e(x, hptr, be) -#else -# define __put_user(x, hptr) __put_user_e(x, hptr, le) -# define __get_user(x, hptr) __get_user_e(x, hptr, le) -#endif - -/* put_user()/get_user() take a guest address and check access */ -/* These are usually used to access an atomic data type, such as an int, - * that has been passed by address. These internally perform locking - * and unlocking on the data type. - */ -#define put_user(x, gaddr, target_type) \ -({ \ - abi_ulong __gaddr =3D (gaddr); \ - target_type *__hptr; \ - abi_long __ret =3D 0; \ - if ((__hptr =3D lock_user(VERIFY_WRITE, __gaddr, sizeof(target_type), = 0))) { \ - __put_user((x), __hptr); \ - unlock_user(__hptr, __gaddr, sizeof(target_type)); \ - } else \ - __ret =3D -TARGET_EFAULT; \ - __ret; \ -}) - -#define get_user(x, gaddr, target_type) \ -({ \ - abi_ulong __gaddr =3D (gaddr); \ - target_type *__hptr; \ - abi_long __ret =3D 0; \ - if ((__hptr =3D lock_user(VERIFY_READ, __gaddr, sizeof(target_type), 1= ))) { \ - __get_user((x), __hptr); \ - unlock_user(__hptr, __gaddr, 0); \ - } else { \ - /* avoid warning */ \ - (x) =3D 0; \ - __ret =3D -TARGET_EFAULT; \ - } \ - __ret; \ -}) - -#define put_user_ual(x, gaddr) put_user((x), (gaddr), abi_ulong) -#define put_user_sal(x, gaddr) put_user((x), (gaddr), abi_long) -#define put_user_u64(x, gaddr) put_user((x), (gaddr), uint64_t) -#define put_user_s64(x, gaddr) put_user((x), (gaddr), int64_t) -#define put_user_u32(x, gaddr) put_user((x), (gaddr), uint32_t) -#define put_user_s32(x, gaddr) put_user((x), (gaddr), int32_t) -#define put_user_u16(x, gaddr) put_user((x), (gaddr), uint16_t) -#define put_user_s16(x, gaddr) put_user((x), (gaddr), int16_t) -#define put_user_u8(x, gaddr) put_user((x), (gaddr), uint8_t) -#define put_user_s8(x, gaddr) put_user((x), (gaddr), int8_t) - -#define get_user_ual(x, gaddr) get_user((x), (gaddr), abi_ulong) -#define get_user_sal(x, gaddr) get_user((x), (gaddr), abi_long) -#define get_user_u64(x, gaddr) get_user((x), (gaddr), uint64_t) -#define get_user_s64(x, gaddr) get_user((x), (gaddr), int64_t) -#define get_user_u32(x, gaddr) get_user((x), (gaddr), uint32_t) -#define get_user_s32(x, gaddr) get_user((x), (gaddr), int32_t) -#define get_user_u16(x, gaddr) get_user((x), (gaddr), uint16_t) -#define get_user_s16(x, gaddr) get_user((x), (gaddr), int16_t) -#define get_user_u8(x, gaddr) get_user((x), (gaddr), uint8_t) -#define get_user_s8(x, gaddr) get_user((x), (gaddr), int8_t) - -/* copy_from_user() and copy_to_user() are usually used to copy data - * buffers between the target and host. These internally perform - * locking/unlocking of the memory. - */ -abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len); -abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len); - -/* Functions for accessing guest memory. The tget and tput functions - read/write single values, byteswapping as necessary. The lock_user fun= ction - gets a pointer to a contiguous area of guest memory, but does not perfo= rm - any byteswapping. lock_user may return either a pointer to the guest - memory, or a temporary buffer. */ - -/* Lock an area of guest memory into the host. If copy is true then the - host area will have the same contents as the guest. */ -static inline void *lock_user(int type, abi_ulong guest_addr, long len, in= t copy) -{ - if (!access_ok(type, guest_addr, len)) - return NULL; -#ifdef DEBUG_REMAP - { - void *addr; - addr =3D g_malloc(len); - if (copy) - memcpy(addr, g2h(guest_addr), len); - else - memset(addr, 0, len); - return addr; - } -#else - return g2h(guest_addr); -#endif -} - -/* Unlock an area of guest memory. The first LEN bytes must be - flushed back to guest memory. host_ptr =3D NULL is explicitly - allowed and does nothing. */ -static inline void unlock_user(void *host_ptr, abi_ulong guest_addr, - long len) -{ - -#ifdef DEBUG_REMAP - if (!host_ptr) - return; - if (host_ptr =3D=3D g2h(guest_addr)) - return; - if (len > 0) - memcpy(g2h(guest_addr), host_ptr, len); - g_free(host_ptr); -#endif -} - -/* Return the length of a string in target memory or -TARGET_EFAULT if - access error. */ -abi_long target_strlen(abi_ulong gaddr); - -/* Like lock_user but for null terminated strings. */ -static inline void *lock_user_string(abi_ulong guest_addr) -{ - abi_long len; - len =3D target_strlen(guest_addr); - if (len < 0) - return NULL; - return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); -} - -/* Helper macros for locking/unlocking a target struct. */ -#define lock_user_struct(type, host_ptr, guest_addr, copy) \ - (host_ptr =3D lock_user(type, guest_addr, sizeof(*host_ptr), copy)) -#define unlock_user_struct(host_ptr, guest_addr, copy) \ - unlock_user(host_ptr, guest_addr, (copy) ? sizeof(*host_ptr) : 0) - #include =20 /* Include target-specific struct and function definitions; --=20 2.11.1 From nobody Mon May 6 09:32:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 148830314725514.589122312771224; Tue, 28 Feb 2017 09:32:27 -0800 (PST) Received: from localhost ([::1]:35853 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cildQ-0006RX-Rs for importer@patchew.org; Tue, 28 Feb 2017 12:32:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilPl-0003I7-9S for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cilPi-0003hO-1e for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:17 -0500 Received: from clearmind.me ([178.32.49.9]:57881) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cilPh-0003gM-Qj for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=clearmind.me; s=dkim; h=Sender:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=q5HMAIbWkFakodX4PFPOSeXN4JuwcC6MURQG2DlqxWA=; b=mEKYARUpuGajxa9IECTI8Ac4v 786e8dqshUqZ0ziBKRg7ZdxrBRxtbnLBIXD4n6DTaUo+41XwUKJ7JGoZeFW+oTLCdBnM6j4TsBir6 2ZUrXGfZPou1Se6/HfeCEzDHUbOssywCr4ksGLWbpMKMFeYPeNa4kll9NHzyM1KOLOy7s=; From: Alessandro Di Federico To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 18:19:16 +0100 Message-Id: <20170228171921.21602-3-ale+qemu@clearmind.me> In-Reply-To: <20170228171921.21602-1-ale+qemu@clearmind.me> References: <20170228171921.21602-1-ale+qemu@clearmind.me> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.49.9 Subject: [Qemu-devel] [PATCH 2/7] Factor out *-user/mmap.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit moves linux-user/mmap.c to the top level directory so that it can be employed by bsd-user (when it will be back in a working shape) and libtcg. --- Makefile.target | 1 + include/qemu-user-common.h | 17 +++++++++++++++++ linux-user/Makefile.objs | 2 +- linux-user/qemu.h | 16 ---------------- linux-user/mmap.c =3D> mmap.c | 0 5 files changed, 19 insertions(+), 17 deletions(-) rename linux-user/mmap.c =3D> mmap.c (100%) diff --git a/Makefile.target b/Makefile.target index 924304c9e6..cf8adc3ced 100644 --- a/Makefile.target +++ b/Makefile.target @@ -89,6 +89,7 @@ all: $(PROGS) stap ######################################################### # cpu emulator library obj-y =3D exec.o translate-all.o cpu-exec.o +obj-$(call land,$(CONFIG_USER_ONLY),$(call lnot,$(CONFIG_BSD_USER))) +=3D = mmap.o obj-y +=3D translate-common.o obj-y +=3D cpu-exec-common.o obj-y +=3D tcg/tcg.o tcg/tcg-op.o tcg/optimize.o diff --git a/include/qemu-user-common.h b/include/qemu-user-common.h index 349dd72fff..e772f54c8f 100644 --- a/include/qemu-user-common.h +++ b/include/qemu-user-common.h @@ -177,4 +177,21 @@ static inline void *lock_user_string(abi_ulong guest_a= ddr) #define unlock_user_struct(host_ptr, guest_addr, copy) \ unlock_user(host_ptr, guest_addr, (copy) ? sizeof(*host_ptr) : 0) =20 +/* mmap.c */ +extern unsigned long mmap_min_addr; + +int target_mprotect(abi_ulong start, abi_ulong len, int prot); +abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, + int flags, int fd, abi_ulong offset); +int target_munmap(abi_ulong start, abi_ulong len); +abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, + abi_ulong new_size, unsigned long flags, + abi_ulong new_addr); +int target_msync(abi_ulong start, abi_ulong len, int flags); +extern unsigned long last_brk; +extern abi_ulong mmap_next_start; +abi_ulong mmap_find_vma(abi_ulong, abi_ulong); +void mmap_fork_start(void); +void mmap_fork_end(int child); + #endif /* QEMU_USER_COMMON_H */ diff --git a/linux-user/Makefile.objs b/linux-user/Makefile.objs index 8c93058100..1595f44d12 100644 --- a/linux-user/Makefile.objs +++ b/linux-user/Makefile.objs @@ -1,4 +1,4 @@ -obj-y =3D main.o syscall.o strace.o mmap.o signal.o \ +obj-y =3D main.o syscall.o strace.o signal.o \ elfload.o linuxload.o uaccess.o uname.o \ safe-syscall.o =20 diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 22b0ad7d30..5cfe68bd43 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -156,7 +156,6 @@ void init_task_state(TaskState *ts); void task_settid(TaskState *); void stop_all_tasks(void); extern const char *qemu_uname_release; -extern unsigned long mmap_min_addr; =20 /* ??? See if we can avoid exposing so much of the loader internals. */ =20 @@ -420,21 +419,6 @@ void sparc64_set_context(CPUSPARCState *env); void sparc64_get_context(CPUSPARCState *env); #endif =20 -/* mmap.c */ -int target_mprotect(abi_ulong start, abi_ulong len, int prot); -abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, - int flags, int fd, abi_ulong offset); -int target_munmap(abi_ulong start, abi_ulong len); -abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, - abi_ulong new_size, unsigned long flags, - abi_ulong new_addr); -int target_msync(abi_ulong start, abi_ulong len, int flags); -extern unsigned long last_brk; -extern abi_ulong mmap_next_start; -abi_ulong mmap_find_vma(abi_ulong, abi_ulong); -void mmap_fork_start(void); -void mmap_fork_end(int child); - /* main.c */ extern unsigned long guest_stack_size; =20 diff --git a/linux-user/mmap.c b/mmap.c similarity index 100% rename from linux-user/mmap.c rename to mmap.c --=20 2.11.1 From nobody Mon May 6 09:32:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488303450240578.6982518613254; Tue, 28 Feb 2017 09:37:30 -0800 (PST) Received: from localhost ([::1]:35899 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciliK-0002VV-Sn for importer@patchew.org; Tue, 28 Feb 2017 12:37:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilPm-0003Jw-Cw for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cilPi-0003hr-Tt for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:18 -0500 Received: from clearmind.me ([178.32.49.9]:49925) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cilPi-0003ga-GH for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=clearmind.me; s=dkim; h=Sender:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=fvOjSAI8deYENh3Wv21/PNjPurmhBoOAt77VCMzg7xU=; b=mWb5LDf4RtqMbHmG8OduSktuq 97Gy6OXuUCBra9rQ+rfodfjGKADSQ1vbv4UJZJpGUjiTpvIFJ8kvxZ5WsosDr1p62d4ssjuJnd7kh Dn691tDlCr9jdp7SBazndjjPQAj/Mx7KX5jWqCBCVq3FSB66G9SQW2E2X9l3LolpDO2u4=; From: Alessandro Di Federico To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 18:19:17 +0100 Message-Id: <20170228171921.21602-4-ale+qemu@clearmind.me> In-Reply-To: <20170228171921.21602-1-ale+qemu@clearmind.me> References: <20170228171921.21602-1-ale+qemu@clearmind.me> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.49.9 Subject: [Qemu-devel] [PATCH 3/7] Move *_cpu_dump_state to translate.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The *_cpu_dump_state functions used to be spread in different files (mainly translate.c but also helper.c and cpu.c). This patch simply moves, for uniformity reasons, in translate.c those that were not there yet. --- target/alpha/helper.c | 34 ----- target/alpha/translate.c | 34 +++++ target/hppa/helper.c | 25 ---- target/hppa/translate.c | 25 ++++ target/i386/helper.c | 323 ------------------------------------------= ---- target/i386/translate.c | 323 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/sparc/cpu.c | 85 ------------ target/sparc/translate.c | 85 ++++++++++++ target/tilegx/cpu.c | 26 ---- target/tilegx/cpu.h | 3 + target/tilegx/translate.c | 26 ++++ 11 files changed, 496 insertions(+), 493 deletions(-) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index a5c308859b..041a9d1c2c 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -418,40 +418,6 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) return false; } =20 -void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, - int flags) -{ - static const char *linux_reg_names[] =3D { - "v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ", - "t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ", - "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ", - "t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero", - }; - AlphaCPU *cpu =3D ALPHA_CPU(cs); - CPUAlphaState *env =3D &cpu->env; - int i; - - cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n", - env->pc, env->ps); - for (i =3D 0; i < 31; i++) { - cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i, - linux_reg_names[i], cpu_alpha_load_gr(env, i)); - if ((i % 3) =3D=3D 2) - cpu_fprintf(f, "\n"); - } - - cpu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\= n", - env->lock_addr, env->lock_value); - - for (i =3D 0; i < 31; i++) { - cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i, - *((uint64_t *)(&env->fir[i]))); - if ((i % 3) =3D=3D 2) - cpu_fprintf(f, "\n"); - } - cpu_fprintf(f, "\n"); -} - /* This should only be called from translate, via gen_excp. We expect that ENV->PC has already been updated. */ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 055286a7b8..df06591997 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3025,3 +3025,37 @@ void restore_state_to_opc(CPUAlphaState *env, Transl= ationBlock *tb, { env->pc =3D data[0]; } + +void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, + int flags) +{ + static const char *linux_reg_names[] =3D { + "v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ", + "t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ", + "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ", + "t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero", + }; + AlphaCPU *cpu =3D ALPHA_CPU(cs); + CPUAlphaState *env =3D &cpu->env; + int i; + + cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n", + env->pc, env->ps); + for (i =3D 0; i < 31; i++) { + cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i, + linux_reg_names[i], cpu_alpha_load_gr(env, i)); + if ((i % 3) =3D=3D 2) + cpu_fprintf(f, "\n"); + } + + cpu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\= n", + env->lock_addr, env->lock_value); + + for (i =3D 0; i < 31; i++) { + cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i, + *((uint64_t *)(&env->fir[i]))); + if ((i % 3) =3D=3D 2) + cpu_fprintf(f, "\n"); + } + cpu_fprintf(f, "\n"); +} diff --git a/target/hppa/helper.c b/target/hppa/helper.c index ba04a9a52b..c7eecfc457 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -110,28 +110,3 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) abort(); return false; } - -void hppa_cpu_dump_state(CPUState *cs, FILE *f, - fprintf_function cpu_fprintf, int flags) -{ - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; - int i; - - cpu_fprintf(f, "IA_F " TARGET_FMT_lx - " IA_B " TARGET_FMT_lx - " PSW " TARGET_FMT_lx - " [N:" TARGET_FMT_ld " V:%d" - " CB:" TARGET_FMT_lx "]\n ", - env->iaoq_f, env->iaoq_b, cpu_hppa_get_psw(env), - env->psw_n, env->psw_v < 0, - ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28= )); - for (i =3D 1; i < 32; i++) { - cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]); - if ((i % 4) =3D=3D 3) { - cpu_fprintf(f, "\n"); - } - } - - /* ??? FR */ -} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5d571f0a4e..5eeb35abc3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3937,3 +3937,28 @@ void restore_state_to_opc(CPUHPPAState *env, Transla= tionBlock *tb, that the instruction was not nullified. */ env->psw_n =3D 0; } + +void hppa_cpu_dump_state(CPUState *cs, FILE *f, + fprintf_function cpu_fprintf, int flags) +{ + HPPACPU *cpu =3D HPPA_CPU(cs); + CPUHPPAState *env =3D &cpu->env; + int i; + + cpu_fprintf(f, "IA_F " TARGET_FMT_lx + " IA_B " TARGET_FMT_lx + " PSW " TARGET_FMT_lx + " [N:" TARGET_FMT_ld " V:%d" + " CB:" TARGET_FMT_lx "]\n ", + env->iaoq_f, env->iaoq_b, cpu_hppa_get_psw(env), + env->psw_n, env->psw_v < 0, + ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28= )); + for (i =3D 1; i < 32; i++) { + cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]); + if ((i % 4) =3D=3D 3) { + cpu_fprintf(f, "\n"); + } + } + + /* ??? FR */ +} diff --git a/target/i386/helper.c b/target/i386/helper.c index e2af3404f2..9bfcf8f238 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -55,132 +55,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) return 0; } =20 -/***********************************************************/ -/* x86 debug */ - -static const char *cc_op_str[CC_OP_NB] =3D { - "DYNAMIC", - "EFLAGS", - - "MULB", - "MULW", - "MULL", - "MULQ", - - "ADDB", - "ADDW", - "ADDL", - "ADDQ", - - "ADCB", - "ADCW", - "ADCL", - "ADCQ", - - "SUBB", - "SUBW", - "SUBL", - "SUBQ", - - "SBBB", - "SBBW", - "SBBL", - "SBBQ", - - "LOGICB", - "LOGICW", - "LOGICL", - "LOGICQ", - - "INCB", - "INCW", - "INCL", - "INCQ", - - "DECB", - "DECW", - "DECL", - "DECQ", - - "SHLB", - "SHLW", - "SHLL", - "SHLQ", - - "SARB", - "SARW", - "SARL", - "SARQ", - - "BMILGB", - "BMILGW", - "BMILGL", - "BMILGQ", - - "ADCX", - "ADOX", - "ADCOX", - - "CLR", -}; - -static void -cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, fprintf_function cpu_fpr= intf, - const char *name, struct SegmentCache *sc) -{ -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - cpu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, - sc->selector, sc->base, sc->limit, sc->flags & 0x00fff= f00); - } else -#endif - { - cpu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, - (uint32_t)sc->base, sc->limit, sc->flags & 0x00ffff00); - } - - if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) - goto done; - - cpu_fprintf(f, " DPL=3D%d ", (sc->flags & DESC_DPL_MASK) >> DESC_DPL_S= HIFT); - if (sc->flags & DESC_S_MASK) { - if (sc->flags & DESC_CS_MASK) { - cpu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : - ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); - cpu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-', - (sc->flags & DESC_R_MASK) ? 'R' : '-'); - } else { - cpu_fprintf(f, - (sc->flags & DESC_B_MASK || env->hflags & HF_LMA_M= ASK) - ? "DS " : "DS16"); - cpu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-', - (sc->flags & DESC_W_MASK) ? 'W' : '-'); - } - cpu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); - } else { - static const char *sys_type_name[2][16] =3D { - { /* 32 bit mode */ - "Reserved", "TSS16-avl", "LDT", "TSS16-busy", - "CallGate16", "TaskGate", "IntGate16", "TrapGate16", - "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", - "CallGate32", "Reserved", "IntGate32", "TrapGate32" - }, - { /* 64 bit mode */ - "", "Reserved", "LDT", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", - "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", - "Reserved", "IntGate64", "TrapGate64" - } - }; - cpu_fprintf(f, "%s", - sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] - [(sc->flags & DESC_TYPE_MASK) - >> DESC_TYPE_SHIFT]); - } -done: - cpu_fprintf(f, "\n"); -} - #ifndef CONFIG_USER_ONLY =20 /* ARRAY_SIZE check is not required because @@ -371,203 +245,6 @@ void x86_cpu_dump_local_apic_state(CPUState *cs, FILE= *f, } #endif /* !CONFIG_USER_ONLY */ =20 -#define DUMP_CODE_BYTES_TOTAL 50 -#define DUMP_CODE_BYTES_BACKWARD 20 - -void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprint= f, - int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int eflags, i, nb; - char cc_op_name[32]; - static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; - - eflags =3D cpu_compute_eflags(env); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - cpu_fprintf(f, - "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%016"= PRIx64 " RDX=3D%016" PRIx64 "\n" - "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016"= PRIx64 " RSP=3D%016" PRIx64 "\n" - "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016"= PRIx64 " R11=3D%016" PRIx64 "\n" - "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016"= PRIx64 " R15=3D%016" PRIx64 "\n" - "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - env->regs[R_EAX], - env->regs[R_EBX], - env->regs[R_ECX], - env->regs[R_EDX], - env->regs[R_ESI], - env->regs[R_EDI], - env->regs[R_EBP], - env->regs[R_ESP], - env->regs[8], - env->regs[9], - env->regs[10], - env->regs[11], - env->regs[12], - env->regs[13], - env->regs[14], - env->regs[15], - env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } else -#endif - { - cpu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" - "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" - "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II=3D= %d A20=3D%d SMM=3D%d HLT=3D%d\n", - (uint32_t)env->regs[R_EAX], - (uint32_t)env->regs[R_EBX], - (uint32_t)env->regs[R_ECX], - (uint32_t)env->regs[R_EDX], - (uint32_t)env->regs[R_ESI], - (uint32_t)env->regs[R_EDI], - (uint32_t)env->regs[R_EBP], - (uint32_t)env->regs[R_ESP], - (uint32_t)env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } - - for(i =3D 0; i < 6; i++) { - cpu_x86_dump_seg_cache(env, f, cpu_fprintf, seg_name[i], - &env->segs[i]); - } - cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "LDT", &env->ldt); - cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR", &env->tr); - -#ifdef TARGET_X86_64 - if (env->hflags & HF_LMA_MASK) { - cpu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", - env->gdt.base, env->gdt.limit); - cpu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", - env->idt.base, env->idt.limit); - cpu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx64= " CR4=3D%08x\n", - (uint32_t)env->cr[0], - env->cr[2], - env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) - cpu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); - cpu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", - env->dr[6], env->dr[7]); - } else -#endif - { - cpu_fprintf(f, "GDT=3D %08x %08x\n", - (uint32_t)env->gdt.base, env->gdt.limit); - cpu_fprintf(f, "IDT=3D %08x %08x\n", - (uint32_t)env->idt.base, env->idt.limit); - cpu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", - (uint32_t)env->cr[0], - (uint32_t)env->cr[2], - (uint32_t)env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) { - cpu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); - } - cpu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "\= n", - env->dr[6], env->dr[7]); - } - if (flags & CPU_DUMP_CCOP) { - if ((unsigned)env->cc_op < CC_OP_NB) - snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); - else - snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - cpu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", - env->cc_src, env->cc_dst, - cc_op_name); - } else -#endif - { - cpu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", - (uint32_t)env->cc_src, (uint32_t)env->cc_dst, - cc_op_name); - } - } - cpu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); - if (flags & CPU_DUMP_FPU) { - int fptag; - fptag =3D 0; - for(i =3D 0; i < 8; i++) { - fptag |=3D ((!env->fptags[i]) << i); - } - cpu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", - env->fpuc, - (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, - env->fpstt, - fptag, - env->mxcsr); - for(i=3D0;i<8;i++) { - CPU_LDoubleU u; - u.d =3D env->fpregs[i].d; - cpu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", - i, u.l.lower, u.l.upper); - if ((i & 1) =3D=3D 1) - cpu_fprintf(f, "\n"); - else - cpu_fprintf(f, " "); - } - if (env->hflags & HF_CS64_MASK) - nb =3D 16; - else - nb =3D 8; - for(i=3D0;ixmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); - if ((i & 1) =3D=3D 1) - cpu_fprintf(f, "\n"); - else - cpu_fprintf(f, " "); - } - } - if (flags & CPU_DUMP_CODE) { - target_ulong base =3D env->segs[R_CS].base + env->eip; - target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); - uint8_t code; - char codestr[3]; - - cpu_fprintf(f, "Code=3D"); - for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { - if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { - snprintf(codestr, sizeof(codestr), "%02x", code); - } else { - snprintf(codestr, sizeof(codestr), "??"); - } - cpu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", - i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs ?= ">" : ""); - } - cpu_fprintf(f, "\n"); - } -} - /***********************************************************/ /* x86 mmu */ /* XXX: add PGE support */ diff --git a/target/i386/translate.c b/target/i386/translate.c index 72c1b03a2a..5623ee65a6 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8526,3 +8526,326 @@ void restore_state_to_opc(CPUX86State *env, Transla= tionBlock *tb, env->cc_op =3D cc_op; } } + +/***********************************************************/ +/* x86 debug */ + +static const char *cc_op_str[CC_OP_NB] =3D { + "DYNAMIC", + "EFLAGS", + + "MULB", + "MULW", + "MULL", + "MULQ", + + "ADDB", + "ADDW", + "ADDL", + "ADDQ", + + "ADCB", + "ADCW", + "ADCL", + "ADCQ", + + "SUBB", + "SUBW", + "SUBL", + "SUBQ", + + "SBBB", + "SBBW", + "SBBL", + "SBBQ", + + "LOGICB", + "LOGICW", + "LOGICL", + "LOGICQ", + + "INCB", + "INCW", + "INCL", + "INCQ", + + "DECB", + "DECW", + "DECL", + "DECQ", + + "SHLB", + "SHLW", + "SHLL", + "SHLQ", + + "SARB", + "SARW", + "SARL", + "SARQ", + + "BMILGB", + "BMILGW", + "BMILGL", + "BMILGQ", + + "ADCX", + "ADOX", + "ADCOX", + + "CLR", +}; + +static void +cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, fprintf_function cpu_fpr= intf, + const char *name, struct SegmentCache *sc) +{ +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + cpu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, + sc->selector, sc->base, sc->limit, sc->flags & 0x00fff= f00); + } else +#endif + { + cpu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, + (uint32_t)sc->base, sc->limit, sc->flags & 0x00ffff00); + } + + if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) + goto done; + + cpu_fprintf(f, " DPL=3D%d ", (sc->flags & DESC_DPL_MASK) >> DESC_DPL_S= HIFT); + if (sc->flags & DESC_S_MASK) { + if (sc->flags & DESC_CS_MASK) { + cpu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : + ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); + cpu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-', + (sc->flags & DESC_R_MASK) ? 'R' : '-'); + } else { + cpu_fprintf(f, + (sc->flags & DESC_B_MASK || env->hflags & HF_LMA_M= ASK) + ? "DS " : "DS16"); + cpu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-', + (sc->flags & DESC_W_MASK) ? 'W' : '-'); + } + cpu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); + } else { + static const char *sys_type_name[2][16] =3D { + { /* 32 bit mode */ + "Reserved", "TSS16-avl", "LDT", "TSS16-busy", + "CallGate16", "TaskGate", "IntGate16", "TrapGate16", + "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", + "CallGate32", "Reserved", "IntGate32", "TrapGate32" + }, + { /* 64 bit mode */ + "", "Reserved", "LDT", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", + "Reserved", "IntGate64", "TrapGate64" + } + }; + cpu_fprintf(f, "%s", + sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] + [(sc->flags & DESC_TYPE_MASK) + >> DESC_TYPE_SHIFT]); + } +done: + cpu_fprintf(f, "\n"); +} + +#define DUMP_CODE_BYTES_TOTAL 50 +#define DUMP_CODE_BYTES_BACKWARD 20 + +void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprint= f, + int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + int eflags, i, nb; + char cc_op_name[32]; + static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; + + eflags =3D cpu_compute_eflags(env); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + cpu_fprintf(f, + "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%016"= PRIx64 " RDX=3D%016" PRIx64 "\n" + "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016"= PRIx64 " RSP=3D%016" PRIx64 "\n" + "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016"= PRIx64 " R11=3D%016" PRIx64 "\n" + "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016"= PRIx64 " R15=3D%016" PRIx64 "\n" + "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + env->regs[R_EAX], + env->regs[R_EBX], + env->regs[R_ECX], + env->regs[R_EDX], + env->regs[R_ESI], + env->regs[R_EDI], + env->regs[R_EBP], + env->regs[R_ESP], + env->regs[8], + env->regs[9], + env->regs[10], + env->regs[11], + env->regs[12], + env->regs[13], + env->regs[14], + env->regs[15], + env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } else +#endif + { + cpu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" + "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" + "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II=3D= %d A20=3D%d SMM=3D%d HLT=3D%d\n", + (uint32_t)env->regs[R_EAX], + (uint32_t)env->regs[R_EBX], + (uint32_t)env->regs[R_ECX], + (uint32_t)env->regs[R_EDX], + (uint32_t)env->regs[R_ESI], + (uint32_t)env->regs[R_EDI], + (uint32_t)env->regs[R_EBP], + (uint32_t)env->regs[R_ESP], + (uint32_t)env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } + + for(i =3D 0; i < 6; i++) { + cpu_x86_dump_seg_cache(env, f, cpu_fprintf, seg_name[i], + &env->segs[i]); + } + cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "LDT", &env->ldt); + cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR", &env->tr); + +#ifdef TARGET_X86_64 + if (env->hflags & HF_LMA_MASK) { + cpu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", + env->gdt.base, env->gdt.limit); + cpu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", + env->idt.base, env->idt.limit); + cpu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx64= " CR4=3D%08x\n", + (uint32_t)env->cr[0], + env->cr[2], + env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) + cpu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); + cpu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", + env->dr[6], env->dr[7]); + } else +#endif + { + cpu_fprintf(f, "GDT=3D %08x %08x\n", + (uint32_t)env->gdt.base, env->gdt.limit); + cpu_fprintf(f, "IDT=3D %08x %08x\n", + (uint32_t)env->idt.base, env->idt.limit); + cpu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", + (uint32_t)env->cr[0], + (uint32_t)env->cr[2], + (uint32_t)env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) { + cpu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); + } + cpu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "\= n", + env->dr[6], env->dr[7]); + } + if (flags & CPU_DUMP_CCOP) { + if ((unsigned)env->cc_op < CC_OP_NB) + snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); + else + snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + cpu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", + env->cc_src, env->cc_dst, + cc_op_name); + } else +#endif + { + cpu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", + (uint32_t)env->cc_src, (uint32_t)env->cc_dst, + cc_op_name); + } + } + cpu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); + if (flags & CPU_DUMP_FPU) { + int fptag; + fptag =3D 0; + for(i =3D 0; i < 8; i++) { + fptag |=3D ((!env->fptags[i]) << i); + } + cpu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", + env->fpuc, + (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, + env->fpstt, + fptag, + env->mxcsr); + for(i=3D0;i<8;i++) { + CPU_LDoubleU u; + u.d =3D env->fpregs[i].d; + cpu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", + i, u.l.lower, u.l.upper); + if ((i & 1) =3D=3D 1) + cpu_fprintf(f, "\n"); + else + cpu_fprintf(f, " "); + } + if (env->hflags & HF_CS64_MASK) + nb =3D 16; + else + nb =3D 8; + for(i=3D0;ixmm_regs[i].ZMM_L(3), + env->xmm_regs[i].ZMM_L(2), + env->xmm_regs[i].ZMM_L(1), + env->xmm_regs[i].ZMM_L(0)); + if ((i & 1) =3D=3D 1) + cpu_fprintf(f, "\n"); + else + cpu_fprintf(f, " "); + } + } + if (flags & CPU_DUMP_CODE) { + target_ulong base =3D env->segs[R_CS].base + env->eip; + target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); + uint8_t code; + char codestr[3]; + + cpu_fprintf(f, "Code=3D"); + for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { + if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { + snprintf(codestr, sizeof(codestr), "%02x", code); + } else { + snprintf(codestr, sizeof(codestr), "??"); + } + cpu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", + i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs ?= ">" : ""); + } + cpu_fprintf(f, "\n"); + } +} diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index d606eb53f4..652cbef425 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -686,91 +686,6 @@ void sparc_cpu_list(FILE *f, fprintf_function cpu_fpri= ntf) "fpu_version mmu_version nwindows\n"); } =20 -static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf, - uint32_t cc) -{ - cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', - cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', - cc & PSR_CARRY ? 'C' : '-'); -} - -#ifdef TARGET_SPARC64 -#define REGS_PER_LINE 4 -#else -#define REGS_PER_LINE 8 -#endif - -void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, - int flags) -{ - SPARCCPU *cpu =3D SPARC_CPU(cs); - CPUSPARCState *env =3D &cpu->env; - int i, x; - - cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env-= >pc, - env->npc); - - for (i =3D 0; i < 8; i++) { - if (i % REGS_PER_LINE =3D=3D 0) { - cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); - } - cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); - if (i % REGS_PER_LINE =3D=3D REGS_PER_LINE - 1) { - cpu_fprintf(f, "\n"); - } - } - for (x =3D 0; x < 3; x++) { - for (i =3D 0; i < 8; i++) { - if (i % REGS_PER_LINE =3D=3D 0) { - cpu_fprintf(f, "%%%c%d-%d: ", - x =3D=3D 0 ? 'o' : (x =3D=3D 1 ? 'l' : 'i'), - i, i + REGS_PER_LINE - 1); - } - cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); - if (i % REGS_PER_LINE =3D=3D REGS_PER_LINE - 1) { - cpu_fprintf(f, "\n"); - } - } - } - - for (i =3D 0; i < TARGET_DPREGS; i++) { - if ((i & 3) =3D=3D 0) { - cpu_fprintf(f, "%%f%02d: ", i * 2); - } - cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); - if ((i & 3) =3D=3D 3) { - cpu_fprintf(f, "\n"); - } - } -#ifdef TARGET_SPARC64 - cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, - (unsigned)cpu_get_ccr(env)); - cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT); - cpu_fprintf(f, " xcc: "); - cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)= ); - cpu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->t= l, - env->psrpil, env->gl); - cpu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba= : " - TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); - cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " - "cleanwin: %d cwp: %d\n", - env->cansave, env->canrestore, env->otherwin, env->wstate, - env->cleanwin, env->nwindows - 1 - env->cwp); - cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " - TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs); - -#else - cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); - cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env)); - cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', - env->psrps ? 'P' : '-', env->psret ? 'E' : '-', - env->wim); - cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", - env->fsr, env->y); -#endif - cpu_fprintf(f, "\n"); -} - static void sparc_cpu_set_pc(CPUState *cs, vaddr value) { SPARCCPU *cpu =3D SPARC_CPU(cs); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 655060cd9a..248ff9018d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5964,3 +5964,88 @@ void restore_state_to_opc(CPUSPARCState *env, Transl= ationBlock *tb, env->npc =3D npc; } } + +static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf, + uint32_t cc) +{ + cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', + cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', + cc & PSR_CARRY ? 'C' : '-'); +} + +#ifdef TARGET_SPARC64 +#define REGS_PER_LINE 4 +#else +#define REGS_PER_LINE 8 +#endif + +void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, + int flags) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + CPUSPARCState *env =3D &cpu->env; + int i, x; + + cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env-= >pc, + env->npc); + + for (i =3D 0; i < 8; i++) { + if (i % REGS_PER_LINE =3D=3D 0) { + cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); + } + cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); + if (i % REGS_PER_LINE =3D=3D REGS_PER_LINE - 1) { + cpu_fprintf(f, "\n"); + } + } + for (x =3D 0; x < 3; x++) { + for (i =3D 0; i < 8; i++) { + if (i % REGS_PER_LINE =3D=3D 0) { + cpu_fprintf(f, "%%%c%d-%d: ", + x =3D=3D 0 ? 'o' : (x =3D=3D 1 ? 'l' : 'i'), + i, i + REGS_PER_LINE - 1); + } + cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); + if (i % REGS_PER_LINE =3D=3D REGS_PER_LINE - 1) { + cpu_fprintf(f, "\n"); + } + } + } + + for (i =3D 0; i < TARGET_DPREGS; i++) { + if ((i & 3) =3D=3D 0) { + cpu_fprintf(f, "%%f%02d: ", i * 2); + } + cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); + if ((i & 3) =3D=3D 3) { + cpu_fprintf(f, "\n"); + } + } +#ifdef TARGET_SPARC64 + cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, + (unsigned)cpu_get_ccr(env)); + cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT); + cpu_fprintf(f, " xcc: "); + cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)= ); + cpu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->t= l, + env->psrpil, env->gl); + cpu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba= : " + TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); + cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " + "cleanwin: %d cwp: %d\n", + env->cansave, env->canrestore, env->otherwin, env->wstate, + env->cleanwin, env->nwindows - 1 - env->cwp); + cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " + TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs); + +#else + cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); + cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env)); + cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', + env->psrps ? 'P' : '-', env->psret ? 'E' : '-', + env->wim); + cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", + env->fsr, env->y); +#endif + cpu_fprintf(f, "\n"); +} diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index d90e38e88c..b79868e1e4 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -27,32 +27,6 @@ #include "linux-user/syscall_defs.h" #include "exec/exec-all.h" =20 -static void tilegx_cpu_dump_state(CPUState *cs, FILE *f, - fprintf_function cpu_fprintf, int flags) -{ - static const char * const reg_names[TILEGX_R_COUNT] =3D { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", - "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", - "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", - "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr" - }; - - TileGXCPU *cpu =3D TILEGX_CPU(cs); - CPUTLGState *env =3D &cpu->env; - int i; - - for (i =3D 0; i < TILEGX_R_COUNT; i++) { - cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s", - reg_names[i], env->regs[i], - (i % 4) =3D=3D 3 ? "\n" : " "); - } - cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n", - env->pc, env->spregs[TILEGX_SPR_CMPEXCH]); -} - TileGXCPU *cpu_tilegx_init(const char *cpu_model) { TileGXCPU *cpu; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index f32be49f65..aa40bbd6bb 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -178,4 +178,7 @@ static inline void cpu_get_tb_cpu_state(CPUTLGState *en= v, target_ulong *pc, *flags =3D 0; } =20 +void tilegx_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpr= intf, + int flags); + #endif diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index ff2ef7b63d..a170b744f4 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2455,3 +2455,29 @@ void tilegx_tcg_init(void) reg_names[i]); } } + +void tilegx_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpr= intf, + int flags) +{ + static const char * const reg_names[TILEGX_R_COUNT] =3D { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", + "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", + "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr" + }; + + TileGXCPU *cpu =3D TILEGX_CPU(cs); + CPUTLGState *env =3D &cpu->env; + int i; + + for (i =3D 0; i < TILEGX_R_COUNT; i++) { + cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s", + reg_names[i], env->regs[i], + (i % 4) =3D=3D 3 ? "\n" : " "); + } + cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n", + env->pc, env->spregs[TILEGX_SPR_CMPEXCH]); +} --=20 2.11.1 From nobody Mon May 6 09:32:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488303067435533.6848330007452; Tue, 28 Feb 2017 09:31:07 -0800 (PST) Received: from localhost ([::1]:35847 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilcA-0005UJ-0z for importer@patchew.org; Tue, 28 Feb 2017 12:31:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilPl-0003IM-H7 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cilPi-0003hl-Mr for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:17 -0500 Received: from clearmind.me ([178.32.49.9]:41905) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cilPi-0003gT-8p for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=clearmind.me; s=dkim; h=Sender:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=CePdjHPpiPAOslJxqGKk4k36m7riEEd/uHU1M1fSt+c=; b=tzi+NsLhHC43YlLQOLE92ubBO vT0SsXHqLx21/qPDFyKlBfpyg38fgt5330xqu8egHpehk4eCK0KD65BmXdixXeQuZDY6Hu5ldFaby 0gHW+kfpMr66rByfr/93O69kYqbbbj+zjSvAlu/GzctEnshtK3Ag57Q/0nwc9iQlqCpws=; From: Alessandro Di Federico To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 18:19:18 +0100 Message-Id: <20170228171921.21602-5-ale+qemu@clearmind.me> In-Reply-To: <20170228171921.21602-1-ale+qemu@clearmind.me> References: <20170228171921.21602-1-ale+qemu@clearmind.me> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.49.9 Subject: [Qemu-devel] [PATCH 4/7] *-user targets object files decoupling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move some functions around in target/$arch/*.c to reduce the coupling among the various compilation units. In particular, we want to make the various translate.c and cpu.c as much standalone as possible, so that they can be easily employed by libtcg. --- exec.c | 6 ++- target/alpha/cpu.c | 38 +++++++++++++++ target/alpha/helper.c | 39 ---------------- target/arm/cpu.h | 74 ++++++++++++++++++++--------- target/arm/helper.c | 85 ++++++---------------------------- target/arm/translate.c | 33 +++++++++++++ target/m68k/cpu.c | 61 ++++++++++++++++++++++++ target/m68k/cpu.h | 49 ++++++++++++++++++++ target/m68k/helper.c | 110 ----------------------------------------= ---- target/mips/op_helper.c | 8 ---- target/mips/translate.c | 8 ++++ target/ppc/gdbstub.c | 20 -------- target/ppc/translate_init.c | 20 ++++++++ target/s390x/cpu.c | 75 ++++++++++++++++++++++++++++++ target/s390x/helper.c | 75 ------------------------------ target/sparc/cpu.h | 2 + target/unicore32/cpu.c | 5 ++ target/unicore32/helper.c | 5 -- 18 files changed, 360 insertions(+), 353 deletions(-) diff --git a/exec.c b/exec.c index 865a1e8295..cf9f039dba 100644 --- a/exec.c +++ b/exec.c @@ -665,16 +665,18 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, in= t asidx) =20 void cpu_exec_unrealizefn(CPUState *cpu) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - cpu_list_remove(cpu); =20 +#ifndef CONFIG_USER_ONLY + CPUClass *cc =3D CPU_GET_CLASS(cpu); + if (cc->vmsd !=3D NULL) { vmstate_unregister(NULL, cc->vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); } +#endif } =20 void cpu_exec_initfn(CPUState *cpu) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b4f97983e5..a1125fca93 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -266,6 +266,44 @@ static const TypeInfo ev68_cpu_type_info =3D { .parent =3D TYPE("ev67"), }; =20 +#define CONVERT_BIT(X, SRC, DST) \ + (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) + +void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val) +{ + uint32_t fpcr =3D val >> 32; + uint32_t t =3D 0; + + t |=3D CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE); + t |=3D CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF); + t |=3D CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF); + t |=3D CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE); + t |=3D CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV); + + env->fpcr =3D fpcr; + env->fpcr_exc_enable =3D ~t & FPCR_STATUS_MASK; + + switch (fpcr & FPCR_DYN_MASK) { + case FPCR_DYN_NORMAL: + default: + t =3D float_round_nearest_even; + break; + case FPCR_DYN_CHOPPED: + t =3D float_round_to_zero; + break; + case FPCR_DYN_MINUS: + t =3D float_round_down; + break; + case FPCR_DYN_PLUS: + t =3D float_round_up; + break; + } + env->fpcr_dyn_round =3D t; + + env->fpcr_flush_to_zero =3D (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ); + env->fp_status.flush_inputs_to_zero =3D (fpcr & FPCR_DNZ) !=3D 0; +} + static void alpha_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 041a9d1c2c..a20c7cd421 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -24,50 +24,11 @@ #include "fpu/softfloat.h" #include "exec/helper-proto.h" =20 - -#define CONVERT_BIT(X, SRC, DST) \ - (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) - uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env) { return (uint64_t)env->fpcr << 32; } =20 -void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val) -{ - uint32_t fpcr =3D val >> 32; - uint32_t t =3D 0; - - t |=3D CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE); - t |=3D CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF); - t |=3D CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF); - t |=3D CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE); - t |=3D CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV); - - env->fpcr =3D fpcr; - env->fpcr_exc_enable =3D ~t & FPCR_STATUS_MASK; - - switch (fpcr & FPCR_DYN_MASK) { - case FPCR_DYN_NORMAL: - default: - t =3D float_round_nearest_even; - break; - case FPCR_DYN_CHOPPED: - t =3D float_round_to_zero; - break; - case FPCR_DYN_MINUS: - t =3D float_round_down; - break; - case FPCR_DYN_PLUS: - t =3D float_round_up; - break; - } - env->fpcr_dyn_round =3D t; - - env->fpcr_flush_to_zero =3D (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ); - env->fp_status.flush_inputs_to_zero =3D (fpcr & FPCR_DNZ) !=3D 0; -} - uint64_t helper_load_fpcr(CPUAlphaState *env) { return cpu_alpha_load_fpcr(env); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0956a54e89..a0067e0ffe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1038,7 +1038,6 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) =20 /* Return the current FPSCR value. */ -uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); =20 /* For A64 the FPSCR is split into two logically distinct registers, @@ -1047,27 +1046,6 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); */ #define FPSR_MASK 0xf800009f #define FPCR_MASK 0x07f79f00 -static inline uint32_t vfp_get_fpsr(CPUARMState *env) -{ - return vfp_get_fpscr(env) & FPSR_MASK; -} - -static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) -{ - uint32_t new_fpscr =3D (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR= _MASK); - vfp_set_fpscr(env, new_fpscr); -} - -static inline uint32_t vfp_get_fpcr(CPUARMState *env) -{ - return vfp_get_fpscr(env) & FPCR_MASK; -} - -static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) -{ - uint32_t new_fpscr =3D (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR= _MASK); - vfp_set_fpscr(env, new_fpscr); -} =20 enum arm_cpu_mode { ARM_CPU_MODE_USR =3D 0x10, @@ -1201,6 +1179,58 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ }; =20 +/* VFP support. We follow the convention used for VFP instructions: + Single precision routines have a "s" suffix, double precision a + "d" suffix. */ + +/* Convert host exception flags to vfp form. */ +static inline int vfp_exceptbits_from_host(int host_bits) +{ + int target_bits =3D 0; + + if (host_bits & float_flag_invalid) + target_bits |=3D 1; + if (host_bits & float_flag_divbyzero) + target_bits |=3D 2; + if (host_bits & float_flag_overflow) + target_bits |=3D 4; + if (host_bits & (float_flag_underflow | float_flag_output_denormal)) + target_bits |=3D 8; + if (host_bits & float_flag_inexact) + target_bits |=3D 0x10; + if (host_bits & float_flag_input_denormal) + target_bits |=3D 0x80; + return target_bits; +} + +static inline uint32_t vfp_get_fpscr(CPUARMState *env) +{ + int i; + uint32_t fpscr; + + fpscr =3D (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) + | (env->vfp.vec_len << 16) + | (env->vfp.vec_stride << 20); + i =3D get_float_exception_flags(&env->vfp.fp_status); + i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); + fpscr |=3D vfp_exceptbits_from_host(i); + return fpscr; +} + +static inline uint32_t vfp_get_fpsr(CPUARMState *env) +{ + return vfp_get_fpscr(env) & FPSR_MASK; +} + +void vfp_set_fpsr(CPUARMState *env, uint32_t val); + +static inline uint32_t vfp_get_fpcr(CPUARMState *env) +{ + return vfp_get_fpscr(env) & FPCR_MASK; +} + +void vfp_set_fpcr(CPUARMState *env, uint32_t val); + static inline int arm_feature(CPUARMState *env, int feature) { return (env->features & (1ULL << feature)) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 47250bcf16..d4075d2afb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5560,11 +5560,6 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, } } =20 -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) -{ - return g_hash_table_lookup(cpregs, &encoded_cp); -} - void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -8757,47 +8752,9 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t = a, uint32_t b) return (a & mask) | (b & ~mask); } =20 -/* VFP support. We follow the convention used for VFP instructions: - Single precision routines have a "s" suffix, double precision a - "d" suffix. */ - -/* Convert host exception flags to vfp form. */ -static inline int vfp_exceptbits_from_host(int host_bits) -{ - int target_bits =3D 0; - - if (host_bits & float_flag_invalid) - target_bits |=3D 1; - if (host_bits & float_flag_divbyzero) - target_bits |=3D 2; - if (host_bits & float_flag_overflow) - target_bits |=3D 4; - if (host_bits & (float_flag_underflow | float_flag_output_denormal)) - target_bits |=3D 8; - if (host_bits & float_flag_inexact) - target_bits |=3D 0x10; - if (host_bits & float_flag_input_denormal) - target_bits |=3D 0x80; - return target_bits; -} - uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) { - int i; - uint32_t fpscr; - - fpscr =3D (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) - | (env->vfp.vec_len << 16) - | (env->vfp.vec_stride << 20); - i =3D get_float_exception_flags(&env->vfp.fp_status); - i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); - fpscr |=3D vfp_exceptbits_from_host(i); - return fpscr; -} - -uint32_t vfp_get_fpscr(CPUARMState *env) -{ - return HELPER(vfp_get_fpscr)(env); + return vfp_get_fpscr(env); } =20 /* Convert vfp exception flags to target form. */ @@ -8820,6 +8777,18 @@ static inline int vfp_exceptbits_to_host(int target_= bits) return host_bits; } =20 +void vfp_set_fpsr(CPUARMState *env, uint32_t val) +{ + uint32_t new_fpscr =3D (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR= _MASK); + vfp_set_fpscr(env, new_fpscr); +} + +void vfp_set_fpcr(CPUARMState *env, uint32_t val) +{ + uint32_t new_fpscr =3D (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR= _MASK); + vfp_set_fpscr(env, new_fpscr); +} + void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { int i; @@ -9670,34 +9639,6 @@ float64 HELPER(rintd)(float64 x, void *fp_status) return ret; } =20 -/* Convert ARM rounding mode to softfloat */ -int arm_rmode_to_sf(int rmode) -{ - switch (rmode) { - case FPROUNDING_TIEAWAY: - rmode =3D float_round_ties_away; - break; - case FPROUNDING_ODD: - /* FIXME: add support for TIEAWAY and ODD */ - qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", - rmode); - case FPROUNDING_TIEEVEN: - default: - rmode =3D float_round_nearest_even; - break; - case FPROUNDING_POSINF: - rmode =3D float_round_up; - break; - case FPROUNDING_NEGINF: - rmode =3D float_round_down; - break; - case FPROUNDING_ZERO: - rmode =3D float_round_to_zero; - break; - } - return rmode; -} - /* CRC helpers. * The upper bytes of val (above the number specified by 'bytes') must have * been zeroed out by the caller. diff --git a/target/arm/translate.c b/target/arm/translate.c index 4436d8f3a2..495f967eb6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3007,6 +3007,34 @@ static int handle_vminmaxnm(uint32_t insn, uint32_t = rd, uint32_t rn, return 0; } =20 +/* Convert ARM rounding mode to softfloat */ +int arm_rmode_to_sf(int rmode) +{ + switch (rmode) { + case FPROUNDING_TIEAWAY: + rmode =3D float_round_ties_away; + break; + case FPROUNDING_ODD: + /* FIXME: add support for TIEAWAY and ODD */ + qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", + rmode); + case FPROUNDING_TIEEVEN: + default: + rmode =3D float_round_nearest_even; + break; + case FPROUNDING_POSINF: + rmode =3D float_round_up; + break; + case FPROUNDING_NEGINF: + rmode =3D float_round_down; + break; + case FPROUNDING_ZERO: + rmode =3D float_round_to_zero; + break; + } + return rmode; +} + static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t = dp, int rounding) { @@ -7435,6 +7463,11 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) return 0; } =20 +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) +{ + return g_hash_table_lookup(cpregs, &encoded_cp); +} + static int disas_coproc_insn(DisasContext *s, uint32_t insn) { int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index fa10b6e4cd..3b00d00461 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -43,6 +43,47 @@ static void m68k_set_feature(CPUM68KState *env, int feat= ure) env->features |=3D (1u << feature); } =20 +void m68k_switch_sp(CPUM68KState *env) +{ + int new_sp; + + env->sp[env->current_sp] =3D env->aregs[7]; + new_sp =3D (env->sr & SR_S && env->cacr & M68K_CACR_EUSP) + ? M68K_SSP : M68K_USP; + env->aregs[7] =3D env->sp[new_sp]; + env->current_sp =3D new_sp; +} + +void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t ccr) +{ + env->cc_x =3D (ccr & CCF_X ? 1 : 0); + env->cc_n =3D (ccr & CCF_N ? -1 : 0); + env->cc_z =3D (ccr & CCF_Z ? 0 : 1); + env->cc_v =3D (ccr & CCF_V ? -1 : 0); + env->cc_c =3D (ccr & CCF_C ? 1 : 0); + env->cc_op =3D CC_OP_FLAGS; +} + +uint32_t cpu_m68k_get_ccr(CPUM68KState *env) +{ + uint32_t x, c, n, z, v; + uint32_t res, src1, src2; + + x =3D env->cc_x; + n =3D env->cc_n; + z =3D env->cc_z; + v =3D env->cc_v; + c =3D env->cc_c; + + COMPUTE_CCR(env->cc_op, x, n, z, v, c); + + n =3D n >> 31; + z =3D (z =3D=3D 0); + v =3D v >> 31; + + return x * CCF_X + n * CCF_N + z * CCF_Z + v * CCF_V + c * CCF_C; +} + /* CPUClass::reset() */ static void m68k_cpu_reset(CPUState *s) { @@ -250,6 +291,26 @@ static void m68k_cpu_initfn(Object *obj) } } =20 +M68kCPU *cpu_m68k_init(const char *cpu_model) +{ + M68kCPU *cpu; + CPUM68KState *env; + ObjectClass *oc; + + oc =3D cpu_class_by_name(TYPE_M68K_CPU, cpu_model); + if (oc =3D=3D NULL) { + return NULL; + } + cpu =3D M68K_CPU(object_new(object_class_get_name(oc))); + env =3D &cpu->env; + + register_m68k_insns(env); + + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); + + return cpu; +} + static const VMStateDescription vmstate_m68k_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 809582212d..1b219c4952 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -262,6 +262,55 @@ void m68k_cpu_list(FILE *f, fprintf_function cpu_fprin= tf); =20 void register_m68k_insns (CPUM68KState *env); =20 +#define EXTSIGN(val, index) ( \ + (index =3D=3D 0) ? (int8_t)(val) : ((index =3D=3D 1) ? (int16_t)(val) = : (val)) \ +) + +#define COMPUTE_CCR(op, x, n, z, v, c) { = \ + switch (op) { = \ + case CC_OP_FLAGS: = \ + /* Everything in place. */ = \ + break; = \ + case CC_OP_ADDB: = \ + case CC_OP_ADDW: = \ + case CC_OP_ADDL: = \ + res =3D n; = \ + src2 =3D v; = \ + src1 =3D EXTSIGN(res - src2, op - CC_OP_ADDB); = \ + c =3D x; = \ + z =3D n; = \ + v =3D (res ^ src1) & ~(src1 ^ src2); = \ + break; = \ + case CC_OP_SUBB: = \ + case CC_OP_SUBW: = \ + case CC_OP_SUBL: = \ + res =3D n; = \ + src2 =3D v; = \ + src1 =3D EXTSIGN(res + src2, op - CC_OP_SUBB); = \ + c =3D x; = \ + z =3D n; = \ + v =3D (res ^ src1) & (src1 ^ src2); = \ + break; = \ + case CC_OP_CMPB: = \ + case CC_OP_CMPW: = \ + case CC_OP_CMPL: = \ + src1 =3D n; = \ + src2 =3D v; = \ + res =3D EXTSIGN(src1 - src2, op - CC_OP_CMPB); = \ + n =3D res; = \ + z =3D res; = \ + c =3D src1 < src2; = \ + v =3D (res ^ src1) & (src1 ^ src2); = \ + break; = \ + case CC_OP_LOGIC: = \ + c =3D v =3D 0; = \ + z =3D n; = \ + break; = \ + default: = \ + cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); = \ + } = \ +} while (0) + #ifdef CONFIG_USER_ONLY /* Coldfire Linux uses 8k pages * and m68k linux uses 4k pages diff --git a/target/m68k/helper.c b/target/m68k/helper.c index f750d3dbaa..987dc78296 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -100,26 +100,6 @@ static int fpu_gdb_set_reg(CPUM68KState *env, uint8_t = *mem_buf, int n) return 0; } =20 -M68kCPU *cpu_m68k_init(const char *cpu_model) -{ - M68kCPU *cpu; - CPUM68KState *env; - ObjectClass *oc; - - oc =3D cpu_class_by_name(TYPE_M68K_CPU, cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - cpu =3D M68K_CPU(object_new(object_class_get_name(oc))); - env =3D &cpu->env; - - register_m68k_insns(env); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; -} - void m68k_cpu_init_gdb(M68kCPU *cpu) { CPUState *cs =3D CPU(cpu); @@ -188,17 +168,6 @@ void HELPER(set_macsr)(CPUM68KState *env, uint32_t val) env->macsr =3D val; } =20 -void m68k_switch_sp(CPUM68KState *env) -{ - int new_sp; - - env->sp[env->current_sp] =3D env->aregs[7]; - new_sp =3D (env->sr & SR_S && env->cacr & M68K_CACR_EUSP) - ? M68K_SSP : M68K_USP; - env->aregs[7] =3D env->sp[new_sp]; - env->current_sp =3D new_sp; -} - #if defined(CONFIG_USER_ONLY) =20 int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, @@ -532,90 +501,11 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_= t acc) } } =20 -#define EXTSIGN(val, index) ( \ - (index =3D=3D 0) ? (int8_t)(val) : ((index =3D=3D 1) ? (int16_t)(val) = : (val)) \ -) - -#define COMPUTE_CCR(op, x, n, z, v, c) { = \ - switch (op) { = \ - case CC_OP_FLAGS: = \ - /* Everything in place. */ = \ - break; = \ - case CC_OP_ADDB: = \ - case CC_OP_ADDW: = \ - case CC_OP_ADDL: = \ - res =3D n; = \ - src2 =3D v; = \ - src1 =3D EXTSIGN(res - src2, op - CC_OP_ADDB); = \ - c =3D x; = \ - z =3D n; = \ - v =3D (res ^ src1) & ~(src1 ^ src2); = \ - break; = \ - case CC_OP_SUBB: = \ - case CC_OP_SUBW: = \ - case CC_OP_SUBL: = \ - res =3D n; = \ - src2 =3D v; = \ - src1 =3D EXTSIGN(res + src2, op - CC_OP_SUBB); = \ - c =3D x; = \ - z =3D n; = \ - v =3D (res ^ src1) & (src1 ^ src2); = \ - break; = \ - case CC_OP_CMPB: = \ - case CC_OP_CMPW: = \ - case CC_OP_CMPL: = \ - src1 =3D n; = \ - src2 =3D v; = \ - res =3D EXTSIGN(src1 - src2, op - CC_OP_CMPB); = \ - n =3D res; = \ - z =3D res; = \ - c =3D src1 < src2; = \ - v =3D (res ^ src1) & (src1 ^ src2); = \ - break; = \ - case CC_OP_LOGIC: = \ - c =3D v =3D 0; = \ - z =3D n; = \ - break; = \ - default: = \ - cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); = \ - } = \ -} while (0) - -uint32_t cpu_m68k_get_ccr(CPUM68KState *env) -{ - uint32_t x, c, n, z, v; - uint32_t res, src1, src2; - - x =3D env->cc_x; - n =3D env->cc_n; - z =3D env->cc_z; - v =3D env->cc_v; - c =3D env->cc_c; - - COMPUTE_CCR(env->cc_op, x, n, z, v, c); - - n =3D n >> 31; - z =3D (z =3D=3D 0); - v =3D v >> 31; - - return x * CCF_X + n * CCF_N + z * CCF_Z + v * CCF_V + c * CCF_C; -} - uint32_t HELPER(get_ccr)(CPUM68KState *env) { return cpu_m68k_get_ccr(env); } =20 -void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t ccr) -{ - env->cc_x =3D (ccr & CCF_X ? 1 : 0); - env->cc_n =3D (ccr & CCF_N ? -1 : 0); - env->cc_z =3D (ccr & CCF_Z ? 0 : 1); - env->cc_v =3D (ccr & CCF_V ? -1 : 0); - env->cc_c =3D (ccr & CCF_C ? 1 : 0); - env->cc_op =3D CC_OP_FLAGS; -} - void HELPER(set_ccr)(CPUM68KState *env, uint32_t ccr) { cpu_m68k_set_ccr(env, ccr); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index b683fcb025..9f3d25b660 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2432,14 +2432,6 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr= addr, #define FP_TO_INT32_OVERFLOW 0x7fffffff #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL =20 -/* convert MIPS rounding mode in FCR31 to IEEE library */ -unsigned int ieee_rm[] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1 =3D 0; diff --git a/target/mips/translate.c b/target/mips/translate.c index 8b4a072ecb..5077099a78 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -36,6 +36,14 @@ #include "trace-tcg.h" #include "exec/log.h" =20 +/* convert MIPS rounding mode in FCR31 to IEEE library */ +unsigned int ieee_rm[] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; + #define MIPS_DEBUG_DISAS 0 =20 /* MIPS major opcodes */ diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 7a338136a8..4f74946ec9 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -84,26 +84,6 @@ static int ppc_gdb_register_len(int n) } } =20 -/* We need to present the registers to gdb in the "current" memory orderin= g. - For user-only mode we get this for free; TARGET_WORDS_BIGENDIAN is set = to - the proper ordering for the binary, and cannot be changed. - For system mode, TARGET_WORDS_BIGENDIAN is always set, and we must check - the current mode of the chip to see if we're running in little-endian. = */ -void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) -{ -#ifndef CONFIG_USER_ONLY - if (!msr_le) { - /* do nothing */ - } else if (len =3D=3D 4) { - bswap32s((uint32_t *)mem_buf); - } else if (len =3D=3D 8) { - bswap64s((uint64_t *)mem_buf); - } else { - g_assert_not_reached(); - } -#endif -} - /* Old gdb always expects FP registers. Newer (xml-aware) gdb only * expects whatever the target description contains. Due to a * historical mishap the FP registers appear in between core integer diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index be35cbd3a2..12ef379d50 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -9458,6 +9458,26 @@ static bool avr_need_swap(CPUPPCState *env) #endif } =20 +/* We need to present the registers to gdb in the "current" memory orderin= g. + For user-only mode we get this for free; TARGET_WORDS_BIGENDIAN is set = to + the proper ordering for the binary, and cannot be changed. + For system mode, TARGET_WORDS_BIGENDIAN is always set, and we must check + the current mode of the chip to see if we're running in little-endian. = */ +void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) +{ +#ifndef CONFIG_USER_ONLY + if (!msr_le) { + /* do nothing */ + } else if (len =3D=3D 4) { + bswap32s((uint32_t *)mem_buf); + } else if (len =3D=3D 8) { + bswap64s((uint64_t *)mem_buf); + } else { + g_assert_not_reached(); + } +#endif +} + static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 066dcd17df..2101d1dbf1 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -440,6 +440,81 @@ static void s390_cpu_class_init(ObjectClass *oc, void = *data) s390_cpu_model_class_register_props(oc); } =20 +S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp) +{ + static bool features_parsed; + char *name, *features; + const char *typename; + ObjectClass *oc; + CPUClass *cc; + + name =3D g_strdup(cpu_model); + features =3D strchr(name, ','); + if (features) { + features[0] =3D 0; + features++; + } + + oc =3D cpu_class_by_name(TYPE_S390_CPU, name); + if (!oc) { + error_setg(errp, "Unknown CPU definition \'%s\'", name); + g_free(name); + return NULL; + } + typename =3D object_class_get_name(oc); + + if (!features_parsed) { + features_parsed =3D true; + cc =3D CPU_CLASS(oc); + cc->parse_features(typename, features, errp); + } + g_free(name); + + if (*errp) { + return NULL; + } + return S390_CPU(CPU(object_new(typename))); +} + +S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp) +{ + S390CPU *cpu; + Error *err =3D NULL; + + cpu =3D cpu_s390x_create(cpu_model, &err); + if (err !=3D NULL) { + goto out; + } + + object_property_set_int(OBJECT(cpu), id, "id", &err); + if (err !=3D NULL) { + goto out; + } + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + +out: + if (err) { + error_propagate(errp, err); + object_unref(OBJECT(cpu)); + cpu =3D NULL; + } + return cpu; +} + +S390CPU *cpu_s390x_init(const char *cpu_model) +{ + Error *err =3D NULL; + S390CPU *cpu; + /* Use to track CPU ID for linux-user only */ + static int64_t next_cpu_id; + + cpu =3D s390x_new_cpu(cpu_model, next_cpu_id++, &err); + if (err) { + error_report_err(err); + } + return cpu; +} + static const TypeInfo s390_cpu_type_info =3D { .name =3D TYPE_S390_CPU, .parent =3D TYPE_CPU, diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 68bd2f9784..19bcaf12dc 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -68,81 +68,6 @@ void s390x_cpu_timer(void *opaque) } #endif =20 -S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp) -{ - static bool features_parsed; - char *name, *features; - const char *typename; - ObjectClass *oc; - CPUClass *cc; - - name =3D g_strdup(cpu_model); - features =3D strchr(name, ','); - if (features) { - features[0] =3D 0; - features++; - } - - oc =3D cpu_class_by_name(TYPE_S390_CPU, name); - if (!oc) { - error_setg(errp, "Unknown CPU definition \'%s\'", name); - g_free(name); - return NULL; - } - typename =3D object_class_get_name(oc); - - if (!features_parsed) { - features_parsed =3D true; - cc =3D CPU_CLASS(oc); - cc->parse_features(typename, features, errp); - } - g_free(name); - - if (*errp) { - return NULL; - } - return S390_CPU(CPU(object_new(typename))); -} - -S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp) -{ - S390CPU *cpu; - Error *err =3D NULL; - - cpu =3D cpu_s390x_create(cpu_model, &err); - if (err !=3D NULL) { - goto out; - } - - object_property_set_int(OBJECT(cpu), id, "id", &err); - if (err !=3D NULL) { - goto out; - } - object_property_set_bool(OBJECT(cpu), true, "realized", &err); - -out: - if (err) { - error_propagate(errp, err); - object_unref(OBJECT(cpu)); - cpu =3D NULL; - } - return cpu; -} - -S390CPU *cpu_s390x_init(const char *cpu_model) -{ - Error *err =3D NULL; - S390CPU *cpu; - /* Use to track CPU ID for linux-user only */ - static int64_t next_cpu_id; - - cpu =3D s390x_new_cpu(cpu_model, next_cpu_id++, &err); - if (err) { - error_report_err(err); - } - return cpu; -} - #if defined(CONFIG_USER_ONLY) =20 void s390_cpu_do_interrupt(CPUState *cs) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 95a36a4bdc..e330bb1f63 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -740,6 +740,8 @@ static inline int cpu_interrupts_enabled(CPUSPARCState = *env1) return 0; } =20 +void compute_psr(CPUSPARCState *env); + static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) { #if !defined(TARGET_SPARC64) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index c9b78ce68e..bab718af7b 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -141,6 +141,11 @@ static void uc32_cpu_initfn(Object *obj) } } =20 +UniCore32CPU *uc32_cpu_init(const char *cpu_model) +{ + return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)); +} + static const VMStateDescription vmstate_uc32_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index f9239dc7b8..309dcd1ae1 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -27,11 +27,6 @@ #define DPRINTF(fmt, ...) do {} while (0) #endif =20 -UniCore32CPU *uc32_cpu_init(const char *cpu_model) -{ - return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)); -} - #ifndef CONFIG_USER_ONLY void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, uint32_t cop) --=20 2.11.1 From nobody Mon May 6 09:32:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488303698478381.0840565285139; Tue, 28 Feb 2017 09:41:38 -0800 (PST) Received: from localhost ([::1]:35918 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilmI-0004VH-IQ for importer@patchew.org; Tue, 28 Feb 2017 12:41:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilQI-0003kU-Qq for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:19:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cilPk-0003iA-29 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:50 -0500 Received: from clearmind.me ([178.32.49.9]:38579) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cilPi-0003ge-P7 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=clearmind.me; s=dkim; h=Sender:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=SpKDAqwTgobBzCfBvCA50IFoAusjO7VtQUM7d3GDnaU=; b=m8wKfaZZlfusMTlxAqfE3BUPR ypC+KZgH1gy82SI8aTmJjYcWdJOdOAO0ZX+zHiT25Iztvc8VydWFX/kzehCPMWGkFZ7SqjrWh8SK0 QunTW5pDKOJhJCDOtoWCn0DafFuJYwih1WAJmphvFgMHdTMMJbidtR5iprlUuanOWxwgI=; From: Alessandro Di Federico To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 18:19:19 +0100 Message-Id: <20170228171921.21602-6-ale+qemu@clearmind.me> In-Reply-To: <20170228171921.21602-1-ale+qemu@clearmind.me> References: <20170228171921.21602-1-ale+qemu@clearmind.me> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.49.9 X-Mailman-Approved-At: Tue, 28 Feb 2017 12:26:02 -0500 Subject: [Qemu-devel] [PATCH 5/7] Isolate coprocessor parts from target/arm/helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" target/arm/helper.c contains several helper functions but also a large amount of coprocessor-related code. This patch isolates the coprocessor-related code in a seperate file (coprocessors.c), since libtcg won't need the helpers but requires the coprocessor part. --- target/arm/Makefile.objs | 2 +- target/arm/coprocessors.c | 5802 +++++++++++++++++++++++++++++++++++++++++= +++ target/arm/helper.c | 5828 +----------------------------------------= ---- target/arm/internals.h | 8 + 4 files changed, 5822 insertions(+), 5818 deletions(-) create mode 100644 target/arm/coprocessors.c diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 847fb52ee0..82898a6a68 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -4,7 +4,7 @@ obj-$(CONFIG_KVM) +=3D kvm.o obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) +=3D kvm32.o obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) +=3D kvm64.o obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o -obj-y +=3D translate.o op_helper.o helper.o cpu.o +obj-y +=3D translate.o op_helper.o helper.o coprocessors.o cpu.o obj-y +=3D neon_helper.o iwmmxt_helper.o obj-y +=3D gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o diff --git a/target/arm/coprocessors.c b/target/arm/coprocessors.c new file mode 100644 index 0000000000..c2819f7ea2 --- /dev/null +++ b/target/arm/coprocessors.c @@ -0,0 +1,5802 @@ +#include "qemu/osdep.h" +#include "trace.h" +#include "cpu.h" +#include "internals.h" +#include "exec/gdbstub.h" +#include "sysemu/arch_init.h" +#include "sysemu/sysemu.h" +#include "exec/exec-all.h" + +#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ + +#ifndef CONFIG_USER_ONLY +/* Definitions for the PMCCNTR and PMCR registers */ +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 +#endif + +static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + int nregs; + + /* VFP data registers are always little-endian. */ + nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; + if (reg < nregs) { + stfq_le_p(buf, env->vfp.regs[reg]); + return 8; + } + if (arm_feature(env, ARM_FEATURE_NEON)) { + /* Aliases for Q regs. */ + nregs +=3D 16; + if (reg < nregs) { + stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); + stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); + return 16; + } + } + switch (reg - nregs) { + case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; + case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; + case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; + } + return 0; +} + +static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + int nregs; + + nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; + if (reg < nregs) { + env->vfp.regs[reg] =3D ldfq_le_p(buf); + return 8; + } + if (arm_feature(env, ARM_FEATURE_NEON)) { + nregs +=3D 16; + if (reg < nregs) { + env->vfp.regs[(reg - 32) * 2] =3D ldfq_le_p(buf); + env->vfp.regs[(reg - 32) * 2 + 1] =3D ldfq_le_p(buf + 8); + return 16; + } + } + switch (reg - nregs) { + case 0: env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); return 4; + case 1: env->vfp.xregs[ARM_VFP_FPSCR] =3D ldl_p(buf); return 4; + case 2: env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf) & (1 << 30); retu= rn 4; + } + return 0; +} + +static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { + case 0 ... 31: + /* 128 bit FP register */ + stfq_le_p(buf, env->vfp.regs[reg * 2]); + stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); + return 16; + case 32: + /* FPSR */ + stl_p(buf, vfp_get_fpsr(env)); + return 4; + case 33: + /* FPCR */ + stl_p(buf, vfp_get_fpcr(env)); + return 4; + default: + return 0; + } +} + +static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { + case 0 ... 31: + /* 128 bit FP register */ + env->vfp.regs[reg * 2] =3D ldfq_le_p(buf); + env->vfp.regs[reg * 2 + 1] =3D ldfq_le_p(buf + 8); + return 16; + case 32: + /* FPSR */ + vfp_set_fpsr(env, ldl_p(buf)); + return 4; + case 33: + /* FPCR */ + vfp_set_fpcr(env, ldl_p(buf)); + return 4; + default: + return 0; + } +} + +static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + assert(ri->fieldoffset); + if (cpreg_field_is_64bit(ri)) { + return CPREG_FIELD64(env, ri); + } else { + return CPREG_FIELD32(env, ri); + } +} + +static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + assert(ri->fieldoffset); + if (cpreg_field_is_64bit(ri)) { + CPREG_FIELD64(env, ri) =3D value; + } else { + CPREG_FIELD32(env, ri) =3D value; + } +} + +static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return (char *)env + ri->fieldoffset; +} + +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Raw read of a coprocessor register (as needed for migration, etc). = */ + if (ri->type & ARM_CP_CONST) { + return ri->resetvalue; + } else if (ri->raw_readfn) { + return ri->raw_readfn(env, ri); + } else if (ri->readfn) { + return ri->readfn(env, ri); + } else { + return raw_read(env, ri); + } +} + +static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t v) +{ + /* Raw write of a coprocessor register (as needed for migration, etc). + * Note that constant registers are treated as write-ignored; the + * caller should check for success by whether a readback gives the + * value written. + */ + if (ri->type & ARM_CP_CONST) { + return; + } else if (ri->raw_writefn) { + ri->raw_writefn(env, ri, v); + } else if (ri->writefn) { + ri->writefn(env, ri, v); + } else { + raw_write(env, ri, v); + } +} + +static bool raw_accessors_invalid(const ARMCPRegInfo *ri) +{ + /* Return true if the regdef would cause an assertion if you called + * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a + * program bug for it not to have the NO_RAW flag). + * NB that returning false here doesn't necessarily mean that calling + * read/write_raw_cp_reg() is safe, because we can't distinguish "has + * read/write access functions which are safe for raw use" from "has + * read/write access functions which have side effects but has forgotten + * to provide raw access functions". + * The tests here line up with the conditions in read/write_raw_cp_reg() + * and assertions in raw_read()/raw_write(). + */ + if ((ri->type & ARM_CP_CONST) || + ri->fieldoffset || + ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn= ))) { + return false; + } + return true; +} + +bool write_cpustate_to_list(ARMCPU *cpu) +{ + /* Write the coprocessor state from cpu->env to the (index,value) list= . */ + int i; + bool ok =3D true; + + for (i =3D 0; i < cpu->cpreg_array_len; i++) { + uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); + const ARMCPRegInfo *ri; + + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + if (!ri) { + ok =3D false; + continue; + } + if (ri->type & ARM_CP_NO_RAW) { + continue; + } + cpu->cpreg_values[i] =3D read_raw_cp_reg(&cpu->env, ri); + } + return ok; +} + +bool write_list_to_cpustate(ARMCPU *cpu) +{ + int i; + bool ok =3D true; + + for (i =3D 0; i < cpu->cpreg_array_len; i++) { + uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); + uint64_t v =3D cpu->cpreg_values[i]; + const ARMCPRegInfo *ri; + + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + if (!ri) { + ok =3D false; + continue; + } + if (ri->type & ARM_CP_NO_RAW) { + continue; + } + /* Write value and confirm it reads back as written + * (to catch read-only registers and partially read-only + * registers where the incoming migration value doesn't match) + */ + write_raw_cp_reg(&cpu->env, ri, v); + if (read_raw_cp_reg(&cpu->env, ri) !=3D v) { + ok =3D false; + } + } + return ok; +} + +static void add_cpreg_to_list(gpointer key, gpointer opaque) +{ + ARMCPU *cpu =3D opaque; + uint64_t regidx; + const ARMCPRegInfo *ri; + + regidx =3D *(uint32_t *)key; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + + if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { + cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); + /* The value array need not be initialized at this point */ + cpu->cpreg_array_len++; + } +} + +static void count_cpreg(gpointer key, gpointer opaque) +{ + ARMCPU *cpu =3D opaque; + uint64_t regidx; + const ARMCPRegInfo *ri; + + regidx =3D *(uint32_t *)key; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + + if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { + cpu->cpreg_array_len++; + } +} + +static gint cpreg_key_compare(gconstpointer a, gconstpointer b) +{ + uint64_t aidx =3D cpreg_to_kvm_id(*(uint32_t *)a); + uint64_t bidx =3D cpreg_to_kvm_id(*(uint32_t *)b); + + if (aidx > bidx) { + return 1; + } + if (aidx < bidx) { + return -1; + } + return 0; +} + +void init_cpreg_list(ARMCPU *cpu) +{ + /* Initialise the cpreg_tuples[] array based on the cp_regs hash. + * Note that we require cpreg_tuples[] to be sorted by key ID. + */ + GList *keys; + int arraylen; + + keys =3D g_hash_table_get_keys(cpu->cp_regs); + keys =3D g_list_sort(keys, cpreg_key_compare); + + cpu->cpreg_array_len =3D 0; + + g_list_foreach(keys, count_cpreg, cpu); + + arraylen =3D cpu->cpreg_array_len; + cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; + cpu->cpreg_array_len =3D 0; + + g_list_foreach(keys, add_cpreg_to_list, cpu); + + assert(cpu->cpreg_array_len =3D=3D arraylen); + + g_list_free(keys); +} + +/* + * Some registers are not accessible if EL3.NS=3D0 and EL3 is using AArch3= 2 but + * they are accessible when EL3 is using AArch64 regardless of EL3.NS. + * + * access_el3_aa32ns: Used to check AArch32 register views. + * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. + */ +static CPAccessResult access_el3_aa32ns(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + bool secure =3D arm_is_secure_below_el3(env); + + assert(!arm_el_is_aa64(env, 3)); + if (secure) { + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (!arm_el_is_aa64(env, 3)) { + return access_el3_aa32ns(env, ri, isread); + } + return CP_ACCESS_OK; +} + +/* Some secure-only AArch32 registers trap to EL3 if used from + * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). + * Note that an access from Secure EL1 can only happen if EL3 is AArch64. + * We assume that the .access field is set to PL1_RW. + */ +static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 3) { + return CP_ACCESS_OK; + } + if (arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_EL3; + } + /* This will be EL1 NS and EL2 NS, which just UNDEF */ + return CP_ACCESS_TRAP_UNCATEGORIZED; +} + +/* Check for traps to "powerdown debug" registers, which are controlled + * by MDCR.TDOSA + */ +static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) + && !arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* Check for traps to "debug ROM" registers, which are controlled + * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. + */ +static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) + && !arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* Check for traps to general debug registers, which are controlled + * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. + */ +static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) + && !arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* Check for traps to performance monitor registers, which are controlled + * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. + */ +static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) + && !arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ +} + +static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + if (raw_read(env, ri) !=3D value) { + /* Unlike real hardware the qemu TLB uses virtual addresses, + * not modified virtual addresses, so this causes a TLB flush. + */ + tlb_flush(CPU(cpu)); + raw_write(env, ri, value); + } +} + +static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_MPU) + && !extended_addresses_enabled(env)) { + /* For VMSA (when not using the LPAE long descriptor page table + * format) this register includes the ASID, so do a TLB flush. + * For PMSA it is purely a process ID and no action is needed. + */ + tlb_flush(CPU(cpu)); + } + raw_write(env, ri, value); +} + +static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate all (TLBIALL) */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + tlb_flush(CPU(cpu)); +} + +static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); +} + +static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by ASID (TLBIASID) */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + tlb_flush(CPU(cpu)); +} + +static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); +} + +/* IS variants of TLB operations must affect all cores */ +static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush(other_cs); + } +} + +static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush(other_cs); + } +} + +static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); + } +} + +static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); + } +} + +static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D ENV_GET_CPU(env); + + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, + ARMMMUIdx_S2NS, -1); +} + +static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, + ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); + } +} + +static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by IPA. This has to invalidate any structures that + * contain only stage 2 translation information, but does not need + * to apply to structures that contain combined stage 1 and stage 2 + * translation information. + * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. + */ + CPUState *cs =3D ENV_GET_CPU(env); + uint64_t pageaddr; + + if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { + return; + } + + pageaddr =3D sextract64(value << 12, 0, 40); + + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); +} + +static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + uint64_t pageaddr; + + if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { + return; + } + + pageaddr =3D sextract64(value << 12, 0, 40); + + CPU_FOREACH(other_cs) { + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); + } +} + +static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D ENV_GET_CPU(env); + + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); +} + +static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); + } +} + +static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D ENV_GET_CPU(env); + uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); + + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); +} + +static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); + + CPU_FOREACH(other_cs) { + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); + } +} + +static const ARMCPRegInfo cp_reginfo[] =3D { + /* Define the secure and non-secure FCSE identifier CP registers + * separately because there is no secure bank in V8 (no _EL3). This a= llows + * the secure register to be properly reset and migrated. There is als= o no + * v8 EL1 version of the register so the non-secure instance stands al= one. + */ + { .name =3D "FCSEIDR(NS)", + .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, + .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_ns), + .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, + { .name =3D "FCSEIDR(S)", + .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, + .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), + .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, + /* Define the secure and non-secure context identifier CP registers + * separately because there is no secure bank in V8 (no _EL3). This a= llows + * the secure register to be properly reset and migrated. In the + * non-secure case, the 32-bit register will have reset and migration + * disabled during registration as it is handled by the 64-bit instanc= e. + */ + { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), + .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, + { .name =3D "CONTEXTIDR(S)", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), + .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { + /* NB: Some of these registers exist in v8 but with more precise + * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginf= o[]). + */ + /* MMU Domain access control / MPU write buffer control */ + { .name =3D "DACR", + .cp =3D 15, .opc1 =3D CP_ANY, .crn =3D 3, .crm =3D CP_ANY, .opc2 =3D= CP_ANY, + .access =3D PL1_RW, .resetvalue =3D 0, + .writefn =3D dacr_write, .raw_writefn =3D raw_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), + offsetoflow32(CPUARMState, cp15.dacr_ns) } }, + /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. + * For v6 and v5, these mappings are overly broad. + */ + { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 0, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, + { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 1, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, + { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 4, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, + { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 8, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, + /* Cache maintenance ops; some of this space may be overridden later. = */ + { .name =3D "CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, + .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, + .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { + /* Not all pre-v6 cores implemented this WFI, so this is slightly + * over-broad. + */ + { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_WFI }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { + /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which + * is UNPREDICTABLE; we choose to NOP as most implementations do). + */ + { .name =3D "WFI_v6", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0,= .opc2 =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_WFI }, + /* L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice + * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM a= nd + * OMAPCP will override this space. + */ + { .name =3D "DLOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_d= ata), + .resetvalue =3D 0 }, + { .name =3D "ILOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 1, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_i= nsn), + .resetvalue =3D 0 }, + /* v6 doesn't have the cache ID registers but Linux reads them anyway = */ + { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, = .opc2 =3D CP_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D 0 }, + /* We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; + * implementing it as RAZ means the "debug architecture version" bits + * will read as a reserved value, which should cause Linux to not try + * to use the debug hardware. + */ + { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* MMU TLB control. Note that the wildcarding means we cover not just + * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. + */ + { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, .writefn =3D tlbia= ll_write, + .type =3D ARM_CP_NO_RAW }, + { .name =3D "TLBIMVA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, .writefn =3D tlbim= va_write, + .type =3D ARM_CP_NO_RAW }, + { .name =3D "TLBIASID", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, .writefn =3D tlbia= sid_write, + .type =3D ARM_CP_NO_RAW }, + { .name =3D "TLBIMVAA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim= vaa_write, + .type =3D ARM_CP_NO_RAW }, + { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, + .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, + .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t mask =3D 0; + + /* In ARMv8 most bits of CPACR_EL1 are RES0. */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. + * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. + * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. + */ + if (arm_feature(env, ARM_FEATURE_VFP)) { + /* VFP coprocessor: cp10 & cp11 [23:20] */ + mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); + + if (!arm_feature(env, ARM_FEATURE_NEON)) { + /* ASEDIS [31] bit is RAO/WI */ + value |=3D (1 << 31); + } + + /* VFPv3 and upwards with NEON implement 32 double precision + * registers (D0-D31). + */ + if (!arm_feature(env, ARM_FEATURE_NEON) || + !arm_feature(env, ARM_FEATURE_VFP3)) { + /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ + value |=3D (1 << 30); + } + } + value &=3D mask; + } + env->cp15.cpacr_el1 =3D value; +} + +static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + /* Check if CPACR accesses are to be trapped to EL2 */ + if (arm_current_el(env) =3D=3D 1 && + (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { + return CP_ACCESS_TRAP_EL2; + /* Check if CPACR accesses are to be trapped to EL3 */ + } else if (arm_current_el(env) < 3 && + (env->cp15.cptr_el[3] & CPTR_TCPAC)) { + return CP_ACCESS_TRAP_EL3; + } + } + + return CP_ACCESS_OK; +} + +static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + /* Check if CPTR accesses are set to trap to EL3 */ + if (arm_current_el(env) =3D=3D 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC= )) { + return CP_ACCESS_TRAP_EL3; + } + + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo v6_cp_reginfo[] =3D { + /* prefetch by MVA in v6, NOP in v7 */ + { .name =3D "MVA_prefetch", + .cp =3D 15, .crn =3D 7, .crm =3D 13, .opc1 =3D 0, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + /* We need to break the TB after ISB to execute self-modifying code + * correctly and also to take any pending interrupts immediately. + * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. + */ + { .name =3D "ISB", .cp =3D 15, .crn =3D 7, .crm =3D 5, .opc1 =3D 0, .o= pc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_NO_RAW, .writefn =3D arm_cp_writ= e_ignore }, + { .name =3D "DSB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_NOP }, + { .name =3D "DMB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 5, + .access =3D PL0_W, .type =3D ARM_CP_NOP }, + { .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 2, + .access =3D PL1_RW, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), + offsetof(CPUARMState, cp15.ifar_ns) }, + .resetvalue =3D 0, }, + /* Watchpoint Fault Address Register : should actually only be present + * for 1136, 1176, 11MPCore. + */ + { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, + { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, + .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), + .resetvalue =3D 0, .writefn =3D cpacr_write }, + REGINFO_SENTINEL +}; + +static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + /* Performance monitor registers user accessibility is controlled + * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable + * trapping to EL2 or EL3 for other accesses. + */ + int el =3D arm_current_el(env); + + if (el =3D=3D 0 && !env->cp15.c9_pmuserenr) { + return CP_ACCESS_TRAP; + } + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) + && !arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL3; + } + + return CP_ACCESS_OK; +} + +#ifndef CONFIG_USER_ONLY + +static inline bool arm_ccnt_enabled(CPUARMState *env) +{ + /* This does not support checking PMCCFILTR_EL0 register */ + + if (!(env->cp15.c9_pmcr & PMCRE)) { + return false; + } + + return true; +} + +void pmccntr_sync(CPUARMState *env) +{ + uint64_t temp_ticks; + + temp_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + temp_ticks /=3D 64; + } + + if (arm_ccnt_enabled(env)) { + env->cp15.c15_ccnt =3D temp_ticks - env->cp15.c15_ccnt; + } +} + +static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_sync(env); + + if (value & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt =3D 0; + } + + /* only the DP, X, D and E bits are writable */ + env->cp15.c9_pmcr &=3D ~0x39; + env->cp15.c9_pmcr |=3D (value & 0x39); + + pmccntr_sync(env); +} + +static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t total_ticks; + + if (!arm_ccnt_enabled(env)) { + /* Counter is disabled, do not change value */ + return env->cp15.c15_ccnt; + } + + total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + total_ticks /=3D 64; + } + return total_ticks - env->cp15.c15_ccnt; +} + +static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and + * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the + * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are + * accessed. + */ + env->cp15.c9_pmselr =3D value & 0x1f; +} + +static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t total_ticks; + + if (!arm_ccnt_enabled(env)) { + /* Counter is disabled, set the absolute value */ + env->cp15.c15_ccnt =3D value; + return; + } + + total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + total_ticks /=3D 64; + } + env->cp15.c15_ccnt =3D total_ticks - value; +} + +static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t cur_val =3D pmccntr_read(env, NULL); + + pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); +} + +#else /* CONFIG_USER_ONLY */ + +void pmccntr_sync(CPUARMState *env) +{ +} + +#endif + +static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_sync(env); + env->cp15.pmccfiltr_el0 =3D value & 0x7E000000; + pmccntr_sync(env); +} + +static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D (1 << 31); + env->cp15.c9_pmcnten |=3D value; +} + +static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D (1 << 31); + env->cp15.c9_pmcnten &=3D ~value; +} + +static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c9_pmovsr &=3D ~value; +} + +static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when + * PMSELR value is equal to or greater than the number of implemented + * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. + */ + if (env->cp15.c9_pmselr =3D=3D 0x1f) { + pmccfiltr_write(env, ri, value); + } +} + +static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER + * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). + */ + if (env->cp15.c9_pmselr =3D=3D 0x1f) { + return env->cp15.pmccfiltr_el0; + } else { + return 0; + } +} + +static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c9_pmuserenr =3D value & 1; +} + +static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* We have no event counters so only the C bit can be changed */ + value &=3D (1 << 31); + env->cp15.c9_pminten |=3D value; +} + +static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D (1 << 31); + env->cp15.c9_pminten &=3D ~value; +} + +static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Note that even though the AArch64 view of this register has bits + * [10:0] all RES0 we can only mask the bottom 5, to comply with the + * architectural requirements for bits which are RES0 only in some + * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 + * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP= .) + */ + raw_write(env, ri, value & ~0x1FULL); +} + +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + /* We only mask off bits that are RES0 both for AArch64 and AArch32. + * For bits that vary between AArch32/64, code needs to check the + * current execution mode before directly using the feature bit. + */ + uint32_t valid_mask =3D SCR_AARCH64_MASK | SCR_AARCH32_MASK; + + if (!arm_feature(env, ARM_FEATURE_EL2)) { + valid_mask &=3D ~SCR_HCE; + + /* On ARMv7, SMD (or SCD as it is called in v7) is only + * supported if EL2 exists. The bit is UNK/SBZP when + * EL2 is unavailable. In QEMU ARMv7, we force it to always zero + * when EL2 is unavailable. + * On ARMv8, this bit is always available. + */ + if (arm_feature(env, ARM_FEATURE_V7) && + !arm_feature(env, ARM_FEATURE_V8)) { + valid_mask &=3D ~SCR_SMD; + } + } + + /* Clear all-context RES0 bits. */ + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + /* Acquire the CSSELR index from the bank corresponding to the CCSIDR + * bank + */ + uint32_t index =3D A32_BANKED_REG_GET(env, csselr, + ri->secure & ARM_CP_SECSTATE_S); + + return cpu->ccsidr[index]; +} + +static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value & 0xf); +} + +static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + CPUState *cs =3D ENV_GET_CPU(env); + uint64_t ret =3D 0; + + if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + ret |=3D CPSR_I; + } + if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { + ret |=3D CPSR_F; + } + /* External aborts are not possible in QEMU so A bit is always clear */ + return ret; +} + +static const ARMCPRegInfo v7_cp_reginfo[] =3D { + /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ + { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + /* Performance monitors are implementation defined in v7, + * but with an ARM recommended set of registers, which we + * follow (although we don't actually implement any counters) + * + * Performance registers fall into three categories: + * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) + * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) + * (c) UNDEF in PL0 if PMUSERENR.EN=3D=3D0, otherwise accessible (all= others) + * For the cases controlled by PMUSERENR we must set .access to PL0_RW + * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. + */ + { .name =3D "PMCNTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), + .writefn =3D pmcntenset_write, + .accessfn =3D pmreg_access, + .raw_writefn =3D raw_write }, + { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, + .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, + { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL0_RW, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), + .accessfn =3D pmreg_access, + .writefn =3D pmcntenclr_write, + .type =3D ARM_CP_ALIAS }, + { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), + .writefn =3D pmcntenclr_write }, + { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, + .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_p= movsr), + .accessfn =3D pmreg_access, + .writefn =3D pmovsr_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsr_write, + .raw_writefn =3D raw_write }, + /* Unimplemented so WI. */ + { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access, .type =3D ARM_CP_NOP = }, +#ifndef CONFIG_USER_ONLY + { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), + .accessfn =3D pmreg_access, .writefn =3D pmselr_write, + .raw_writefn =3D raw_write}, + { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), + .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, + { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, + .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_IO, + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, + .accessfn =3D pmreg_access }, + { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_IO, + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, +#endif + { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), + .resetvalue =3D 0, }, + { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, + { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, + /* Unimplemented, RAZ/WI. */ + { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + .accessfn =3D pmreg_access }, + { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), + .resetvalue =3D 0, + .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMUSERENR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 0, + .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_= CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), + .resetvalue =3D 0, + .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), + .resetvalue =3D 0, + .writefn =3D pmintenset_write, .raw_writefn =3D raw_write }, + { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, + .resetvalue =3D 0x0 }, + { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenclr_write, }, + { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenclr_write }, + { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, + .access =3D PL1_R, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW = }, + { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .writefn =3D csselr_write, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_ns) } }, + /* Auxiliary ID register: this actually has an IMPDEF value but for now + * just RAZ for all cores: + */ + { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* Auxiliary fault status registers: these also are IMPDEF, and we + * choose to RAZ/WI for all cores. + */ + { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* MAIR can just read-as-written because we don't implement caches + * and so don't need to care about memory attributes. + */ + { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[1]), + .resetvalue =3D 0 }, + { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[3]), + .resetvalue =3D 0 }, + /* For non-long-descriptor page tables these are PRRR and NMRR; + * regardless they still act as reads-as-written for QEMU. + */ + /* MAIR0/1 are defined separately from their 64-bit counterpart which + * allows them to assign the correct fieldoffset based on the endiann= ess + * handled in the field definitions. + */ + { .name =3D "MAIR0", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .acce= ss =3D PL1_RW, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair0_s), + offsetof(CPUARMState, cp15.mair0_ns) }, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "MAIR1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .acce= ss =3D PL1_RW, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair1_s), + offsetof(CPUARMState, cp15.mair1_ns) }, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "ISR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, + /* 32 bit ITLB invalidates */ + { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 5, .opc2 =3D 2, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + /* 32 bit DTLB invalidates */ + { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 6, .opc2 =3D 2, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + /* 32 bit TLB invalidates */ + { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 2, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { + /* 32 bit TLB invalidates, Inner Shareable */ + { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_is_= write }, + { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, + { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .writefn =3D tlbiasid_is_write }, + { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .writefn =3D tlbimvaa_is_write }, + REGINFO_SENTINEL +}; + +static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D 1; + env->teecr =3D value; +} + +static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *= ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 0 && (env->teecr & 1)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo t2ee_cp_reginfo[] =3D { + { .name =3D "TEECR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 6, = .opc2 =3D 0, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, teecr), + .resetvalue =3D 0, + .writefn =3D teecr_write }, + { .name =3D "TEEHBR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 6,= .opc2 =3D 0, + .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, teehbr), + .accessfn =3D teehbr_access, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo v6k_cp_reginfo[] =3D { + { .name =3D "TPIDR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 2, .crn =3D 13, .crm =3D 0, + .access =3D PL0_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalu= e =3D 0 }, + { .name =3D "TPIDRURW", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 2, + .access =3D PL0_RW, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrurw_s), + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = }, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, + .access =3D PL0_R|PL1_W, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el[0]), + .resetvalue =3D 0}, + { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, + .access =3D PL0_R|PL1_W, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), + offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D 13, .crm =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalu= e =3D 0 }, + { .name =3D "TPIDRPRW", .opc1 =3D 0, .cp =3D 15, .crn =3D 13, .crm =3D= 0, .opc2 =3D 4, + .access =3D PL1_RW, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrprw_s), + offsetoflow32(CPUARMState, cp15.tpidrprw_ns) = }, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +#ifndef CONFIG_USER_ONLY + +static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. + * Writable only at the highest implemented exception level. + */ + int el =3D arm_current_el(env); + + switch (el) { + case 0: + if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { + return CP_ACCESS_TRAP; + } + break; + case 1: + if (!isread && ri->state =3D=3D ARM_CP_STATE_AA32 && + arm_is_secure_below_el3(env)) { + /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) = */ + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + break; + case 2: + case 3: + break; + } + + if (!isread && el < arm_highest_el(env)) { + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, + bool isread) +{ + unsigned int cur_el =3D arm_current_el(env); + bool secure =3D arm_is_secure(env); + + /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ + if (cur_el =3D=3D 0 && + !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { + return CP_ACCESS_TRAP; + } + + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 && + !extract32(env->cp15.cnthctl_el2, 0, 1)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + +static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, + bool isread) +{ + unsigned int cur_el =3D arm_current_el(env); + bool secure =3D arm_is_secure(env); + + /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if + * EL0[PV]TEN is zero. + */ + if (cur_el =3D=3D 0 && + !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { + return CP_ACCESS_TRAP; + } + + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 && + !extract32(env->cp15.cnthctl_el2, 1, 1)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + +static CPAccessResult gt_pct_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + return gt_counter_access(env, GTIMER_PHYS, isread); +} + +static CPAccessResult gt_vct_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + return gt_counter_access(env, GTIMER_VIRT, isread); +} + +static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + return gt_timer_access(env, GTIMER_PHYS, isread); +} + +static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + return gt_timer_access(env, GTIMER_VIRT, isread); +} + +static CPAccessResult gt_stimer_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* The AArch64 register view of the secure physical timer is + * always accessible from EL3, and configurably accessible from + * Secure EL1. + */ + switch (arm_current_el(env)) { + case 1: + if (!arm_is_secure(env)) { + return CP_ACCESS_TRAP; + } + if (!(env->cp15.scr_el3 & SCR_ST)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; + case 0: + case 2: + return CP_ACCESS_TRAP; + case 3: + return CP_ACCESS_OK; + default: + g_assert_not_reached(); + } +} + +static uint64_t gt_get_countervalue(CPUARMState *env) +{ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; +} + +static void gt_recalc_timer(ARMCPU *cpu, int timeridx) +{ + ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; + + if (gt->ctl & 1) { + /* Timer enabled: calculate and set current ISTATUS, irq, and + * reset timer to when ISTATUS next has to change + */ + uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? + cpu->env.cp15.cntvoff_el2 : 0; + uint64_t count =3D gt_get_countervalue(&cpu->env); + /* Note that this must be unsigned 64 bit arithmetic: */ + int istatus =3D count - offset >=3D gt->cval; + uint64_t nexttick; + int irqstate; + + gt->ctl =3D deposit32(gt->ctl, 2, 1, istatus); + + irqstate =3D (istatus && !(gt->ctl & 2)); + qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); + + if (istatus) { + /* Next transition is when count rolls back over to zero */ + nexttick =3D UINT64_MAX; + } else { + /* Next transition is when we hit cval */ + nexttick =3D gt->cval + offset; + } + /* Note that the desired next expiry time might be beyond the + * signed-64-bit range of a QEMUTimer -- in this case we just + * set the timer for as far in the future as possible. When the + * timer expires we will reset the timer for any remaining period. + */ + if (nexttick > INT64_MAX / GTIMER_SCALE) { + nexttick =3D INT64_MAX / GTIMER_SCALE; + } + timer_mod(cpu->gt_timer[timeridx], nexttick); + trace_arm_gt_recalc(timeridx, irqstate, nexttick); + } else { + /* Timer disabled: ISTATUS and timer output always clear */ + gt->ctl &=3D ~4; + qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); + timer_del(cpu->gt_timer[timeridx]); + trace_arm_gt_recalc_disabled(timeridx); + } +} + +static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + timer_del(cpu->gt_timer[timeridx]); +} + +static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_get_countervalue(env); +} + +static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_get_countervalue(env) - env->cp15.cntvoff_el2; +} + +static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx, + uint64_t value) +{ + trace_arm_gt_cval_write(timeridx, value); + env->cp15.c14_timer[timeridx].cval =3D value; + gt_recalc_timer(arm_env_get_cpu(env), timeridx); +} + +static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx) +{ + uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; + + return (uint32_t)(env->cp15.c14_timer[timeridx].cval - + (gt_get_countervalue(env) - offset)); +} + +static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx, + uint64_t value) +{ + uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; + + trace_arm_gt_tval_write(timeridx, value); + env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + + sextract64(value, 0, 32); + gt_recalc_timer(arm_env_get_cpu(env), timeridx); +} + +static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint32_t oldval =3D env->cp15.c14_timer[timeridx].ctl; + + trace_arm_gt_ctl_write(timeridx, value); + env->cp15.c14_timer[timeridx].ctl =3D deposit64(oldval, 0, 2, value); + if ((oldval ^ value) & 1) { + /* Enable toggled */ + gt_recalc_timer(cpu, timeridx); + } else if ((oldval ^ value) & 2) { + /* IMASK toggled: don't need to recalculate, + * just set the interrupt line based on ISTATUS + */ + int irqstate =3D (oldval & 4) && !(value & 2); + + trace_arm_gt_imask_toggle(timeridx, irqstate); + qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); + } +} + +static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_PHYS); +} + +static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_PHYS, value); +} + +static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_PHYS); +} + +static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_PHYS, value); +} + +static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_PHYS, value); +} + +static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_VIRT); +} + +static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_VIRT, value); +} + +static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_VIRT); +} + +static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_VIRT, value); +} + +static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_VIRT, value); +} + +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + trace_arm_gt_cntvoff_write(value); + raw_write(env, ri, value); + gt_recalc_timer(cpu, GTIMER_VIRT); +} + +static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_HYP); +} + +static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYP, value); +} + +static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYP); +} + +static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYP, value); +} + +static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYP, value); +} + +static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_SEC); +} + +static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_SEC, value); +} + +static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_SEC); +} + +static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_SEC, value); +} + +static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_SEC, value); +} + +void arm_gt_ptimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_PHYS); +} + +void arm_gt_vtimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_VIRT); +} + +void arm_gt_htimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_HYP); +} + +void arm_gt_stimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_SEC); +} + +static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { + /* Note that CNTFRQ is purely reads-as-written for the benefit + * of software; writing it doesn't actually change the timer frequency. + * Our reset value matches the fixed frequency we implement the timer = at. + */ + { .name =3D "CNTFRQ", .cp =3D 15, .crn =3D 14, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_cntfrq), + }, + { .name =3D "CNTFRQ_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntfrq), + .resetvalue =3D (1000 * 1000 * 1000) / GTIMER_SCALE, + }, + /* overall control: mostly access permissions */ + { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), + .resetvalue =3D 0, + }, + /* per-timer control */ + { .name =3D "CNTP_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D= 0, .opc2 =3D 1, + .secure =3D ARM_CP_SECSTATE_NS, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_ptimer_access, + .fieldoffset =3D offsetoflow32(CPUARMState, + cp15.c14_timer[GTIMER_PHYS].ctl), + .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_CTL(S)", + .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, + .secure =3D ARM_CP_SECSTATE_S, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_ptimer_access, + .fieldoffset =3D offsetoflow32(CPUARMState, + cp15.c14_timer[GTIMER_SEC].ctl), + .writefn =3D gt_sec_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_CTL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .type =3D ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_ptimer_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), + .resetvalue =3D 0, + .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D= 0, .opc2 =3D 1, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_vtimer_access, + .fieldoffset =3D offsetoflow32(CPUARMState, + cp15.c14_timer[GTIMER_VIRT].ctl), + .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, + .type =3D ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_vtimer_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), + .resetvalue =3D 0, + .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, + }, + /* TimerValue views: a 32 bit downcounting view of the underlying stat= e */ + { .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 = =3D 0, .opc2 =3D 0, + .secure =3D ARM_CP_SECSTATE_NS, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_ptimer_access, + .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, + }, + { .name =3D "CNTP_TVAL(S)", + .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, + .secure =3D ARM_CP_SECSTATE_S, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_ptimer_access, + .readfn =3D gt_sec_tval_read, .writefn =3D gt_sec_tval_write, + }, + { .name =3D "CNTP_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset, + .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, + }, + { .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 = =3D 0, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_vtimer_access, + .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, + }, + { .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset, + .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, + }, + /* The counter itself */ + { .name =3D "CNTPCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, + .accessfn =3D gt_pct_access, + .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + }, + { .name =3D "CNTPCT_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 1, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D gt_pct_access, .readfn =3D gt_cnt_read, + }, + { .name =3D "CNTVCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 1, + .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, + .accessfn =3D gt_vct_access, + .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + }, + { .name =3D "CNTVCT_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 2, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D gt_vct_access, .readfn =3D gt_virt_cnt_read, + }, + /* Comparison value, indicating when the timer goes off */ + { .name =3D "CNTP_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, + .secure =3D ARM_CP_SECSTATE_NS, + .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), + .accessfn =3D gt_ptimer_access, + .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_CVAL(S)", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, + .secure =3D ARM_CP_SECSTATE_S, + .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), + .accessfn =3D gt_ptimer_access, + .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), + .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, + .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3, + .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), + .accessfn =3D gt_vtimer_access, + .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, + .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), + .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, + .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, + }, + /* Secure timer -- this is actually restricted to only EL3 + * and configurably Secure-EL1 via the accessfn. + */ + { .name =3D "CNTPS_TVAL_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW, + .accessfn =3D gt_stimer_access, + .readfn =3D gt_sec_tval_read, + .writefn =3D gt_sec_tval_write, + .resetfn =3D gt_sec_timer_reset, + }, + { .name =3D "CNTPS_CTL_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .type =3D ARM_CP_IO, .access =3D PL1_RW, + .accessfn =3D gt_stimer_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ct= l), + .resetvalue =3D 0, + .writefn =3D gt_sec_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTPS_CVAL_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .type =3D ARM_CP_IO, .access =3D PL1_RW, + .accessfn =3D gt_stimer_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), + .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, + }, + REGINFO_SENTINEL +}; + +#else +/* In user-mode none of the generic timer registers are accessible, + * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio ou= tputs, + * so instead just don't register any of them. + */ +static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { + REGINFO_SENTINEL +}; + +#endif + +static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + if (arm_feature(env, ARM_FEATURE_LPAE)) { + raw_write(env, ri, value); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + raw_write(env, ri, value & 0xfffff6ff); + } else { + raw_write(env, ri, value & 0xfffff1ff); + } +} + +#ifndef CONFIG_USER_ONLY +/* get_phys_addr() isn't present for user-mode-only targets */ + +static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (ri->opc2 & 4) { + /* The ATS12NSO* operations must trap to EL3 if executed in + * Secure EL1 (which can only happen if EL3 is AArch64). + * They are simply UNDEF if executed from NS EL1. + * They function normally from EL2 or EL3. + */ + if (arm_current_el(env) =3D=3D 1) { + if (arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; + } + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + } + return CP_ACCESS_OK; +} + +static uint64_t do_ats_write(CPUARMState *env, uint64_t value, + int access_type, ARMMMUIdx mmu_idx) +{ + hwaddr phys_addr; + target_ulong page_size; + int prot; + uint32_t fsr; + bool ret; + uint64_t par64; + MemTxAttrs attrs =3D {}; + ARMMMUFaultInfo fi =3D {}; + + ret =3D get_phys_addr(env, value, access_type, mmu_idx, + &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); + if (extended_addresses_enabled(env)) { + /* fsr is a DFSR/IFSR value for the long descriptor + * translation table format, but with WnR always clear. + * Convert it to a 64-bit PAR. + */ + par64 =3D (1 << 11); /* LPAE bit always set */ + if (!ret) { + par64 |=3D phys_addr & ~0xfffULL; + if (!attrs.secure) { + par64 |=3D (1 << 9); /* NS */ + } + /* We don't set the ATTR or SH fields in the PAR. */ + } else { + par64 |=3D 1; /* F */ + par64 |=3D (fsr & 0x3f) << 1; /* FS */ + /* Note that S2WLK and FSTAGE are always zero, because we don't + * implement virtualization and therefore there can't be a sta= ge 2 + * fault. + */ + } + } else { + /* fsr is a DFSR/IFSR value for the short descriptor + * translation table format (with WnR always clear). + * Convert it to a 32-bit PAR. + */ + if (!ret) { + /* We do not set any attribute bits in the PAR */ + if (page_size =3D=3D (1 << 24) + && arm_feature(env, ARM_FEATURE_V7)) { + par64 =3D (phys_addr & 0xff000000) | (1 << 1); + } else { + par64 =3D phys_addr & 0xfffff000; + } + if (!attrs.secure) { + par64 |=3D (1 << 9); /* NS */ + } + } else { + par64 =3D ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | + ((fsr & 0xf) << 1) | 1; + } + } + return par64; +} + +static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + int access_type =3D ri->opc2 & 1; + uint64_t par64; + ARMMMUIdx mmu_idx; + int el =3D arm_current_el(env); + bool secure =3D arm_is_secure_below_el3(env); + + switch (ri->opc2 & 6) { + case 0: + /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ + switch (el) { + case 3: + mmu_idx =3D ARMMMUIdx_S1E3; + break; + case 2: + mmu_idx =3D ARMMMUIdx_S1NSE1; + break; + case 1: + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + break; + default: + g_assert_not_reached(); + } + break; + case 2: + /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ + switch (el) { + case 3: + mmu_idx =3D ARMMMUIdx_S1SE0; + break; + case 2: + mmu_idx =3D ARMMMUIdx_S1NSE0; + break; + case 1: + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + break; + default: + g_assert_not_reached(); + } + break; + case 4: + /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ + mmu_idx =3D ARMMMUIdx_S12NSE1; + break; + case 6: + /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ + mmu_idx =3D ARMMMUIdx_S12NSE0; + break; + default: + g_assert_not_reached(); + } + + par64 =3D do_ats_write(env, value, access_type, mmu_idx); + + A32_BANKED_CURRENT_REG_SET(env, par, par64); +} + +static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int access_type =3D ri->opc2 & 1; + uint64_t par64; + + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); + + A32_BANKED_CURRENT_REG_SET(env, par, par64); +} + +static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 3 && !(env->cp15.scr_el3 & SCR_NS)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int access_type =3D ri->opc2 & 1; + ARMMMUIdx mmu_idx; + int secure =3D arm_is_secure_below_el3(env); + + switch (ri->opc2 & 6) { + case 0: + switch (ri->opc1) { + case 0: /* AT S1E1R, AT S1E1W */ + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + break; + case 4: /* AT S1E2R, AT S1E2W */ + mmu_idx =3D ARMMMUIdx_S1E2; + break; + case 6: /* AT S1E3R, AT S1E3W */ + mmu_idx =3D ARMMMUIdx_S1E3; + break; + default: + g_assert_not_reached(); + } + break; + case 2: /* AT S1E0R, AT S1E0W */ + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + break; + case 4: /* AT S12E1R, AT S12E1W */ + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; + break; + case 6: /* AT S12E0R, AT S12E0W */ + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; + break; + default: + g_assert_not_reached(); + } + + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); +} +#endif + +static const ARMCPRegInfo vapa_cp_reginfo[] =3D { + { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 =3D 0, .o= pc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.par_s), + offsetoflow32(CPUARMState, cp15.par_ns) }, + .writefn =3D par_write }, +#ifndef CONFIG_USER_ONLY + /* This underdecoding is safe because the reginfo is NO_RAW. */ + { .name =3D "ATS", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0, .o= pc2 =3D CP_ANY, + .access =3D PL1_W, .accessfn =3D ats_access, + .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW }, +#endif + REGINFO_SENTINEL +}; + +/* Return basic MPU access permission bits. */ +static uint32_t simple_mpu_ap_bits(uint32_t val) +{ + uint32_t ret; + uint32_t mask; + int i; + ret =3D 0; + mask =3D 3; + for (i =3D 0; i < 16; i +=3D 2) { + ret |=3D (val >> i) & mask; + mask <<=3D 2; + } + return ret; +} + +/* Pad basic MPU access permission bits to extended format. */ +static uint32_t extended_mpu_ap_bits(uint32_t val) +{ + uint32_t ret; + uint32_t mask; + int i; + ret =3D 0; + mask =3D 3; + for (i =3D 0; i < 16; i +=3D 2) { + ret |=3D (val & mask) << i; + mask <<=3D 2; + } + return ret; +} + +static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.pmsav5_data_ap =3D extended_mpu_ap_bits(value); +} + +static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *= ri) +{ + return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); +} + +static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.pmsav5_insn_ap =3D extended_mpu_ap_bits(value); +} + +static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *= ri) +{ + return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); +} + +static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); + + if (!u32p) { + return 0; + } + + u32p +=3D env->cp15.c6_rgnr; + return *u32p; +} + +static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); + + if (!u32p) { + return; + } + + u32p +=3D env->cp15.c6_rgnr; + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + *u32p =3D value; +} + +static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); + + if (!u32p) { + return; + } + + memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); +} + +static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint32_t nrgs =3D cpu->pmsav7_dregion; + + if (value >=3D nrgs) { + qemu_log_mask(LOG_GUEST_ERROR, + "PMSAv7 RGNR write >=3D # supported regions, %" PRIu= 32 + " > %" PRIu32 "\n", (uint32_t)value, nrgs); + return; + } + + raw_write(env, ri, value); +} + +static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { + { .name =3D "DRBAR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.drbar), + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + { .name =3D "DRSR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, .= opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.drsr), + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + { .name =3D "DRACR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.dracr), + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_rgnr), + .writefn =3D pmsav7_rgnr_write }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { + { .name =3D "DATA_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_data_ap), + .readfn =3D pmsav5_data_ap_read, .writefn =3D pmsav5_data_ap_write, = }, + { .name =3D "INSN_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_insn_ap), + .readfn =3D pmsav5_insn_ap_read, .writefn =3D pmsav5_insn_ap_write, = }, + { .name =3D "DATA_EXT_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_data_ap), + .resetvalue =3D 0, }, + { .name =3D "INSN_EXT_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_insn_ap), + .resetvalue =3D 0, }, + { .name =3D "DCACHE_CFG", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c2_data), .resetvalue = =3D 0, }, + { .name =3D "ICACHE_CFG", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c2_insn), .resetvalue = =3D 0, }, + /* Protection region base and size registers */ + { .name =3D "946_PRBS0", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[0]) }, + { .name =3D "946_PRBS1", .cp =3D 15, .crn =3D 6, .crm =3D 1, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[1]) }, + { .name =3D "946_PRBS2", .cp =3D 15, .crn =3D 6, .crm =3D 2, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[2]) }, + { .name =3D "946_PRBS3", .cp =3D 15, .crn =3D 6, .crm =3D 3, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[3]) }, + { .name =3D "946_PRBS4", .cp =3D 15, .crn =3D 6, .crm =3D 4, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[4]) }, + { .name =3D "946_PRBS5", .cp =3D 15, .crn =3D 6, .crm =3D 5, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[5]) }, + { .name =3D "946_PRBS6", .cp =3D 15, .crn =3D 6, .crm =3D 6, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[6]) }, + { .name =3D "946_PRBS7", .cp =3D 15, .crn =3D 6, .crm =3D 7, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, + REGINFO_SENTINEL +}; + +static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + TCR *tcr =3D raw_ptr(env, ri); + int maskshift =3D extract32(value, 0, 3); + + if (!arm_feature(env, ARM_FEATURE_V8)) { + if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { + /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when + * using Long-desciptor translation table format */ + value &=3D ~((7 << 19) | (3 << 14) | (0xf << 3)); + } else if (arm_feature(env, ARM_FEATURE_EL3)) { + /* In an implementation that includes the Security Extensions + * TTBCR has additional fields PD0 [4] and PD1 [5] for + * Short-descriptor translation table format. + */ + value &=3D TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; + } else { + value &=3D TTBCR_N; + } + } + + /* Update the masks corresponding to the TCR bank being written + * Note that we always calculate mask and base_mask, but + * they are only used for short-descriptor tables (ie if EAE is 0); + * for long-descriptor tables the TCR fields are used differently + * and the mask and base_mask values are meaningless. + */ + tcr->raw_tcr =3D value; + tcr->mask =3D ~(((uint32_t)0xffffffffu) >> maskshift); + tcr->base_mask =3D ~((uint32_t)0x3fffu >> maskshift); +} + +static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* With LPAE the TTBCR could result in a change of ASID + * via the TTBCR.A1 bit, so do a TLB flush. + */ + tlb_flush(CPU(cpu)); + } + vmsa_ttbcr_raw_write(env, ri, value); +} + +static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + TCR *tcr =3D raw_ptr(env, ri); + + /* Reset both the TCR as well as the masks corresponding to the bank of + * the TCR being reset. + */ + tcr->raw_tcr =3D 0; + tcr->mask =3D 0; + tcr->base_mask =3D 0xffffc000u; +} + +static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + TCR *tcr =3D raw_ptr(env, ri); + + /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ + tlb_flush(CPU(cpu)); + tcr->raw_tcr =3D value; +} + +static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* 64 bit accesses to the TTBRs can change the ASID and so we + * must flush the TLB. + */ + if (cpreg_field_is_64bit(ri)) { + ARMCPU *cpu =3D arm_env_get_cpu(env); + + tlb_flush(CPU(cpu)); + } + raw_write(env, ri, value); +} + +static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + + /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ + if (raw_read(env, ri) !=3D value) { + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, + ARMMMUIdx_S2NS, -1); + raw_write(env, ri, value); + } +} + +static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { + { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dfsr_s), + offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, + { .name =3D "IFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, + .access =3D PL1_RW, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.ifsr_s), + offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, + { .name =3D "DFAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 0, .= opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.dfar_s), + offsetof(CPUARMState, cp15.dfar_ns) } }, + { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[1]), + .resetvalue =3D 0, }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { + { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, + { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), + offsetof(CPUARMState, cp15.ttbr0_ns) } }, + { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), + offsetof(CPUARMState, cp15.ttbr1_ns) } }, + { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .writefn =3D vmsa_tcr_el1_write, + .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, + { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_= write, + .raw_writefn =3D vmsa_ttbcr_raw_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tcr_el[3]), + offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, + REGINFO_SENTINEL +}; + +static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_ticonfig =3D value & 0xe7; + /* The OS_TYPE bit in this register changes the reported CPUID! */ + env->cp15.c0_cpuid =3D (value & (1 << 5)) ? + ARM_CPUID_TI915T : ARM_CPUID_TI925T; +} + +static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_threadid =3D value & 0xffff; +} + +static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Wait-for-interrupt (deprecated) */ + cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); +} + +static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* On OMAP there are registers indicating the max/min index of dcache = lines + * containing a dirty line; cache flush operations have to reset these. + */ + env->cp15.c15_i_max =3D 0x000; + env->cp15.c15_i_min =3D 0xff0; +} + +static const ARMCPRegInfo omap_cp_reginfo[] =3D { + { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_OVERRIDE, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_el[1]), + .resetvalue =3D 0, }, + { .name =3D "", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 0, .opc= 2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + { .name =3D "TICONFIG", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ticonfig), .resetval= ue =3D 0, + .writefn =3D omap_ticonfig_write }, + { .name =3D "IMAX", .cp =3D 15, .crn =3D 15, .crm =3D 2, .opc1 =3D 0, = .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = =3D 0, }, + { .name =3D "IMIN", .cp =3D 15, .crn =3D 15, .crm =3D 3, .opc1 =3D 0, = .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0xff0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_min) }, + { .name =3D "THREADID", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_threadid), .resetval= ue =3D 0, + .writefn =3D omap_threadid_write }, + { .name =3D "TI925T_STATUS", .cp =3D 15, .crn =3D 15, + .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, + .type =3D ARM_CP_NO_RAW, + .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, + /* TODO: Peripheral port remap register: + * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller + * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), + * when MMU is off. + */ + { .name =3D "OMAP_CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, + .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, + .type =3D ARM_CP_OVERRIDE | ARM_CP_NO_RAW, + .writefn =3D omap_cachemaint_write }, + { .name =3D "C9", .cp =3D 15, .crn =3D 9, + .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, + .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_cpar =3D value & 0x3fff; +} + +static const ARMCPRegInfo xscale_cp_reginfo[] =3D { + { .name =3D "XSCALE_CPAR", + .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D 0, .opc2 =3D 0, .acce= ss =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = =3D 0, + .writefn =3D xscale_cpar_write, }, + { .name =3D "XSCALE_AUXCR", + .cp =3D 15, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, .acces= s =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c1_xscaleauxcr), + .resetvalue =3D 0, }, + /* XScale specific cache-lockdown: since we have no cache we NOP these + * and hope the guest does not really rely on cache behaviour. + */ + { .name =3D "XSCALE_LOCK_ICACHE_LINE", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "XSCALE_UNLOCK_ICACHE", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "XSCALE_DCACHE_LOCK", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + { .name =3D "XSCALE_UNLOCK_DCACHE", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { + /* RAZ/WI the whole crn=3D15 space, when we don't have a more specific + * implementation of this implementation-defined space. + * Ideally this should eventually disappear in favour of actually + * implementing the correct behaviour for all cores. + */ + { .name =3D "C15_IMPDEF", .cp =3D 15, .crn =3D 15, + .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, + .access =3D PL1_RW, + .type =3D ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] =3D { + /* Cache status: RAZ because we have no cache so it's always clean */ + { .name =3D "CDSR", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, = .opc2 =3D 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo cache_block_ops_cp_reginfo[] =3D { + /* We never have a a block transfer operation in progress */ + { .name =3D "BXSR", .cp =3D 15, .crn =3D 7, .crm =3D 12, .opc1 =3D 0, = .opc2 =3D 4, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D 0 }, + /* The cache ops themselves: these all NOP for QEMU */ + { .name =3D "IICR", .cp =3D 15, .crm =3D 5, .opc1 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "IDCR", .cp =3D 15, .crm =3D 6, .opc1 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "CDCR", .cp =3D 15, .crm =3D 12, .opc1 =3D 0, + .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "PIR", .cp =3D 15, .crm =3D 12, .opc1 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "PDR", .cp =3D 15, .crm =3D 12, .opc1 =3D 2, + .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { + /* The cache test-and-clean instructions always return (1 << 30) + * to indicate that there are no dirty cache lines. + */ + { .name =3D "TC_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 = =3D 0, .opc2 =3D 3, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D (1 << 30) }, + { .name =3D "TCI_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 3, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D (1 << 30) }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { + /* Ignore ReadBuffer accesses */ + { .name =3D "C9_READBUFFER", .cp =3D 15, .crn =3D 9, + .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, + .access =3D PL1_RW, .resetvalue =3D 0, + .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, + REGINFO_SENTINEL +}; + +static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + unsigned int cur_el =3D arm_current_el(env); + bool secure =3D arm_is_secure(env); + + if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el =3D= =3D 1) { + return env->cp15.vpidr_el2; + } + return raw_read(env, ri); +} + +static uint64_t mpidr_read_val(CPUARMState *env) +{ + ARMCPU *cpu =3D ARM_CPU(arm_env_get_cpu(env)); + uint64_t mpidr =3D cpu->mp_affinity; + + if (arm_feature(env, ARM_FEATURE_V7MP)) { + mpidr |=3D (1U << 31); + /* Cores which are uniprocessor (non-coherent) + * but still implement the MP extensions set + * bit 30. (For instance, Cortex-R5). + */ + if (cpu->mp_is_up) { + mpidr |=3D (1u << 30); + } + } + return mpidr; +} + +static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + unsigned int cur_el =3D arm_current_el(env); + bool secure =3D arm_is_secure(env); + + if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el =3D=3D 1) { + return env->cp15.vmpidr_el2; + } + return mpidr_read_val(env); +} + +static const ARMCPRegInfo mpidr_cp_reginfo[] =3D { + { .name =3D "MPIDR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 5, + .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo lpae_cp_reginfo[] =3D { + /* NOP AMAIR0/1 */ + { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ + { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "PAR", .cp =3D 15, .crm =3D 7, .opc1 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), + offsetof(CPUARMState, cp15.par_ns)} }, + { .name =3D "TTBR0", .cp =3D 15, .crm =3D 2, .opc1 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), + offsetof(CPUARMState, cp15.ttbr0_ns) }, + .writefn =3D vmsa_ttbr_write, }, + { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), + offsetof(CPUARMState, cp15.ttbr1_ns) }, + .writefn =3D vmsa_ttbr_write, }, + REGINFO_SENTINEL +}; + +/* Convert vfp exception flags to target form. */ +static inline int vfp_exceptbits_to_host(int target_bits) +{ + int host_bits =3D 0; + + if (target_bits & 1) + host_bits |=3D float_flag_invalid; + if (target_bits & 2) + host_bits |=3D float_flag_divbyzero; + if (target_bits & 4) + host_bits |=3D float_flag_overflow; + if (target_bits & 8) + host_bits |=3D float_flag_underflow; + if (target_bits & 0x10) + host_bits |=3D float_flag_inexact; + if (target_bits & 0x80) + host_bits |=3D float_flag_input_denormal; + return host_bits; +} + +void vfp_set_fpsr(CPUARMState *env, uint32_t val) +{ + uint32_t new_fpscr =3D (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR= _MASK); + vfp_set_fpscr(env, new_fpscr); +} + +void vfp_set_fpcr(CPUARMState *env, uint32_t val) +{ + uint32_t new_fpscr =3D (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR= _MASK); + vfp_set_fpscr(env, new_fpscr); +} + +void vfp_set_fpscr(CPUARMState *env, uint32_t val) +{ + int i; + uint32_t changed; + + changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; + env->vfp.xregs[ARM_VFP_FPSCR] =3D (val & 0xffc8ffff); + env->vfp.vec_len =3D (val >> 16) & 7; + env->vfp.vec_stride =3D (val >> 20) & 3; + + changed ^=3D val; + if (changed & (3 << 22)) { + i =3D (val >> 22) & 3; + switch (i) { + case FPROUNDING_TIEEVEN: + i =3D float_round_nearest_even; + break; + case FPROUNDING_POSINF: + i =3D float_round_up; + break; + case FPROUNDING_NEGINF: + i =3D float_round_down; + break; + case FPROUNDING_ZERO: + i =3D float_round_to_zero; + break; + } + set_float_rounding_mode(i, &env->vfp.fp_status); + } + if (changed & (1 << 24)) { + set_flush_to_zero((val & (1 << 24)) !=3D 0, &env->vfp.fp_status); + set_flush_inputs_to_zero((val & (1 << 24)) !=3D 0, &env->vfp.fp_st= atus); + } + if (changed & (1 << 25)) + set_default_nan_mode((val & (1 << 25)) !=3D 0, &env->vfp.fp_status= ); + + i =3D vfp_exceptbits_to_host(val); + set_float_exception_flags(i, &env->vfp.fp_status); + set_float_exception_flags(0, &env->vfp.standard_fp_status); +} + +static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return vfp_get_fpcr(env); +} + +static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + vfp_set_fpcr(env, value); +} + +static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return vfp_get_fpsr(env); +} + +static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + vfp_set_fpsr(env, value); +} + +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->daif =3D value & PSTATE_DAIF; +} + +static CPAccessResult aa64_cacheop_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless + * SCTLR_EL1.UCI is set. + */ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= I)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions + * Page D4-1736 (DDI0487A.b) + */ + +static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + + if (arm_is_secure_below_el3(env)) { + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); + } else { + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1); + } +} + +static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, + uint64_t value) +{ + bool sec =3D arm_is_secure_below_el3(env); + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + if (sec) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0= , -1); + } else { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, + ARMMMUIdx_S12NSE0, -1); + } + } +} + +static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Note that the 'ALL' scope must invalidate both stage 1 and + * stage 2 translations, whereas most other scopes only invalidate + * stage 1 translations. + */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + + if (arm_is_secure_below_el3(env)) { + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); + } else { + if (arm_feature(env, ARM_FEATURE_EL2)) { + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, + ARMMMUIdx_S2NS, -1); + } else { + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, = -1); + } + } +} + +static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); +} + +static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + + tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1); +} + +static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* Note that the 'ALL' scope must invalidate both stage 1 and + * stage 2 translations, whereas most other scopes only invalidate + * stage 1 translations. + */ + bool sec =3D arm_is_secure_below_el3(env); + bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + if (sec) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0= , -1); + } else if (has_el2) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, + ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); + } else { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, + ARMMMUIdx_S12NSE0, -1); + } + } +} + +static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); + } +} + +static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1); + } +} + +static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by VA, EL1&0 (AArch64 version). + * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + + if (arm_is_secure_below_el3(env)) { + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1, + ARMMMUIdx_S1SE0, -1); + } else { + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1, + ARMMMUIdx_S12NSE0, -1); + } +} + +static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by VA, EL2 + * Currently handles both VAE2 and VALE2, since we don't support + * flush-last-level-only. + */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); +} + +static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by VA, EL3 + * Currently handles both VAE3 and VALE3, since we don't support + * flush-last-level-only. + */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1); +} + +static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + bool sec =3D arm_is_secure_below_el3(env); + CPUState *other_cs; + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + + CPU_FOREACH(other_cs) { + if (sec) { + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1, + ARMMMUIdx_S1SE0, -1); + } else { + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1, + ARMMMUIdx_S12NSE0, -1); + } + } +} + +static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + CPUState *other_cs; + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + + CPU_FOREACH(other_cs) { + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); + } +} + +static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + CPUState *other_cs; + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + + CPU_FOREACH(other_cs) { + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1); + } +} + +static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* Invalidate by IPA. This has to invalidate any structures that + * contain only stage 2 translation information, but does not need + * to apply to structures that contain combined stage 1 and stage 2 + * translation information. + * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. + */ + ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + uint64_t pageaddr; + + if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { + return; + } + + pageaddr =3D sextract64(value << 12, 0, 48); + + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); +} + +static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, + uint64_t value) +{ + CPUState *other_cs; + uint64_t pageaddr; + + if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { + return; + } + + pageaddr =3D sextract64(value << 12, 0, 48); + + CPU_FOREACH(other_cs) { + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); + } +} + +static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + /* We don't implement EL2, so the only control on DC ZVA is the + * bit in the SCTLR which can prohibit access for EL0. + */ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZ= E)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + int dzp_bit =3D 1 << 4; + + /* DZP indicates whether DC ZVA access is allowed */ + if (aa64_zva_access(env, NULL, false) =3D=3D CP_ACCESS_OK) { + dzp_bit =3D 0; + } + return cpu->dcz_blocksize | dzp_bit; +} + +static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *= ri, + bool isread) +{ + if (!(env->pstate & PSTATE_SP)) { + /* Access to SP_EL0 is undefined if it's being used as + * the stack pointer. + */ + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + return CP_ACCESS_OK; +} + +static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_SP; +} + +static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t= val) +{ + update_spsel(env, val); +} + +static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + + if (raw_read(env, ri) =3D=3D value) { + /* Skip the TLB flush if nothing actually changed; Linux likes + * to do a lot of pointless SCTLR writes. + */ + return; + } + + raw_write(env, ri, value); + /* ??? Lots of these bits are not implemented. */ + /* This may enable/disable the MMU, so do a TLB flush. */ + tlb_flush(CPU(cpu)); +} + +static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) =3D=3D 2)= { + return CP_ACCESS_TRAP_FP_EL2; + } + if (env->cp15.cptr_el[3] & CPTR_TFP) { + return CP_ACCESS_TRAP_FP_EL3; + } + return CP_ACCESS_OK; +} + +static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.mdcr_el3 =3D value & SDCR_VALID_MASK; +} + +static const ARMCPRegInfo v8_cp_reginfo[] =3D { + /* Minimal set of EL0-visible registers. This will need to be expanded + * significantly for system emulation of AArch64 CPUs. + */ + { .name =3D "NZCV", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NZCV }, + { .name =3D "DAIF", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 2, + .type =3D ARM_CP_NO_RAW, + .access =3D PL0_RW, .accessfn =3D aa64_daif_access, + .fieldoffset =3D offsetof(CPUARMState, daif), + .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, + .access =3D PL0_RW, .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fp= cr_write }, + { .name =3D "FPSR", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 4, + .access =3D PL0_RW, .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fp= sr_write }, + { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, + .readfn =3D aa64_dczid_read }, + { .name =3D "DC_ZVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_DC_ZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, + { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 4, .crm =3D 2, + .access =3D PL1_R, .type =3D ARM_CP_CURRENTEL }, + /* Cache ops: all NOPs since we don't emulate caches */ + { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_access }, + { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_access }, + { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_access }, + { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_access }, + { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + /* TLBI operations */ + { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1_write }, + { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae1_write }, + { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1_write }, + { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae1_write }, + { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae1_write }, + { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae1_write }, + { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_ipas2e1is_write }, + { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_ipas2e1is_write }, + { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_ipas2e1_write }, + { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_ipas2e1_write }, + { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1_write }, + { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, +#ifndef CONFIG_USER_ONLY + /* 64 bit address translation operations */ + { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "AT_S12E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "AT_S12E0R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present= */ + { .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "AT_S1E3W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, + { .name =3D "PAR_EL1", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 7, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]), + .writefn =3D par_write }, +#endif + /* TLB invalidate last level of translation table walk */ + { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, + { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .writefn =3D tlbimvaa_is_write }, + { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, + { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbimva_hyp_write }, + { .name =3D "TLBIMVALHIS", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbimva_hyp_is_write }, + { .name =3D "TLBIIPAS2", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiipas2_write }, + { .name =3D "TLBIIPAS2IS", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiipas2_is_write }, + { .name =3D "TLBIIPAS2L", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiipas2_write }, + { .name =3D "TLBIIPAS2LIS", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiipas2_is_write }, + /* 32 bit cache operations */ + { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + /* MMU Domain access control / MPU write buffer control */ + { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .writefn =3D dacr_write, .raw_writefn =3D raw_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), + offsetoflow32(CPUARMState, cp15.dacr_ns) } }, + { .name =3D "ELR_EL1", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, + { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, + /* We rely on the access checks not allowing the guest to write to the + * state field when SPSel indicates that it's being used as the stack + * pointer. + */ + { .name =3D "SP_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D sp_el0_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, sp_el[0]) }, + { .name =3D "SP_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, sp_el[1]) }, + { .name =3D "SPSel", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, + { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), + .access =3D PL2_RW, .accessfn =3D fpexc32_access }, + { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D dacr_write, .raw_writefn =3D raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, + { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, + { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, + { .name =3D "SPSR_ABT", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, + { .name =3D "SPSR_UND", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 2, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_UND]) }, + { .name =3D "SPSR_FIQ", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 3, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, + { .name =3D "MDCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, + .resetvalue =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr= _el3) }, + { .name =3D "SDCR", .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, + .writefn =3D sdcr_write, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, + REGINFO_SENTINEL +}; + +/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ +static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { + { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, + .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, + { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_NO_RAW, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, + .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, + { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, + .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, + .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 6, .crm =3D 2, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, + { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint64_t valid_mask =3D HCR_MASK; + + if (arm_feature(env, ARM_FEATURE_EL3)) { + valid_mask &=3D ~HCR_HCD; + } else { + valid_mask &=3D ~HCR_TSC; + } + + /* Clear RES0 bits. */ + value &=3D valid_mask; + + /* These bits change the MMU setup: + * HCR_VM enables stage 2 translation + * HCR_PTW forbids certain page-table setups + * HCR_DC Disables stage1 and enables stage2 translation + */ + if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { + tlb_flush(CPU(cpu)); + } + raw_write(env, ri, value); +} + +static const ARMCPRegInfo el2_cp_reginfo[] =3D { + { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), + .writefn =3D hcr_write }, + { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, elr_el[2]) }, + { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[2]) }, + { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[2]) }, + { .name =3D "SPSR_EL2", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, + { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .writefn =3D vbar_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[2]), + .resetvalue =3D 0 }, + { .name =3D "SP_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, sp_el[2]) }, + { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, + .access =3D PL2_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[2]) }, + { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[2]), + .resetvalue =3D 0 }, + { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, + .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, + { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ + { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, + .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, + /* no .writefn needed as this can't cause an ASID change; + * no .raw_writefn or .resetfn needed as we never use mask/base_mask + */ + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, + { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, + .type =3D ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, + { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, + .access =3D PL2_RW, + /* no .writefn needed as this can't cause an ASID change; + * no .raw_writefn or .resetfn needed as we never use mask/base_mask + */ + .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, + { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 6, .crm =3D 2, + .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2), + .writefn =3D vttbr_write }, + { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .writefn =3D vttbr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2) }, + { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .raw_writefn =3D raw_write, .writefn =3D sctlr_w= rite, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[2]) }, + { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, + { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, + { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, + { .name =3D "TLBIALLNSNH", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiall_nsnh_write }, + { .name =3D "TLBIALLNSNHIS", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiall_nsnh_is_write }, + { .name =3D "TLBIALLH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiall_hyp_write }, + { .name =3D "TLBIALLHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiall_hyp_is_write }, + { .name =3D "TLBIMVAH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbimva_hyp_write }, + { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbimva_hyp_is_write }, + { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbi_aa64_alle2_write }, + { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbi_aa64_vae2_write }, + { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae2_write }, + { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbi_aa64_vae2is_write }, + { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae2is_write }, +#ifndef CONFIG_USER_ONLY + /* Unlike the other EL2-related AT operations, these must + * UNDEF from EL3 if EL2 is not implemented, which is why we + * define them here rather than with the rest of the AT ops. + */ + { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D at_s1e2_access, + .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64 }, + { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL2_W, .accessfn =3D at_s1e2_access, + .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64 }, + /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE + * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 + * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se + * to behave as if SCR.NS was 1. + */ + { .name =3D "ATS1HR", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 0, + .access =3D PL2_W, + .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW }, + { .name =3D "ATS1HW", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 1, + .access =3D PL2_W, + .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW }, + { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, + /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the + * reset values as IMPDEF. We choose to reset to 3 to comply with + * both ARMv7 and ARMv8. + */ + .access =3D PL2_RW, .resetvalue =3D 3, + .fieldoffset =3D offsetof(CPUARMState, cp15.cnthctl_el2) }, + { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_IO, .resetvalue =3D 0, + .writefn =3D gt_cntvoff_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, + { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_I= O, + .writefn =3D gt_cntvoff_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, + { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cv= al), + .type =3D ARM_CP_IO, .access =3D PL2_RW, + .writefn =3D gt_hyp_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cv= al), + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO, + .writefn =3D gt_hyp_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, + .resetfn =3D gt_hyp_timer_reset, + .readfn =3D gt_hyp_tval_read, .writefn =3D gt_hyp_tval_write }, + { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .type =3D ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ct= l), + .resetvalue =3D 0, + .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, +#endif + /* The only field of MDCR_EL2 that has a defined architectural reset v= alue + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but= we + * don't impelment any PMU event counters, so using zero as a reset + * value for MDCR_EL2 is okay + */ + { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, + { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, + { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, + { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 15, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 = =3D 3, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.hstr_el2) }, + REGINFO_SENTINEL +}; + +static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. + * At Secure EL1 it traps to EL3. + */ + if (arm_current_el(env) =3D=3D 3) { + return CP_ACCESS_OK; + } + if (arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_EL3; + } + /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads= . */ + if (isread) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_UNCATEGORIZED; +} + +static const ARMCPRegInfo el3_cp_reginfo[] =3D { + { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), + .resetvalue =3D 0, .writefn =3D scr_write }, + { .name =3D "SCR", .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.scr_el3), + .writefn =3D scr_write }, + { .name =3D "SDER32_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.sder) }, + { .name =3D "SDER", + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.sder) }, + { .name =3D "MVBAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0,= .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, + .writefn =3D vbar_write, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.mvbar) }, + { .name =3D "TTBR0_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[3]) }, + { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, + .access =3D PL3_RW, + /* no .writefn needed as this can't cause an ASID change; + * we must provide a .raw_writefn and .resetfn because we handle + * reset and migration for the AArch32 TTBCR(S), which might be + * using mask and base_mask. + */ + .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D vmsa_ttbcr_raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[3]) }, + { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, elr_el[3]) }, + { .name =3D "ESR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[3]) }, + { .name =3D "FAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[3]) }, + { .name =3D "SPSR_EL3", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_MON]) }, + { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_RW, .writefn =3D vbar_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[3]), + .resetvalue =3D 0 }, + { .name =3D "CPTR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, + .access =3D PL3_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[3]) }, + { .name =3D "TPIDR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, + .access =3D PL3_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[3]) }, + { .name =3D "AMAIR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR0_EL3", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR1_EL3", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "TLBI_ALLE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + { .name =3D "TLBI_VAE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3is_write }, + { .name =3D "TLBI_VALE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3is_write }, + { .name =3D "TLBI_ALLE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3_write }, + { .name =3D "TLBI_VAE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3_write }, + { .name =3D "TLBI_VALE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3_write }, + REGINFO_SENTINEL +}; + +static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, + * but the AArch32 CTR has its own reginfo struct) + */ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= T)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Writes to OSLAR_EL1 may update the OS lock status, which can be + * read via a bit in OSLSR_EL1. + */ + int oslock; + + if (ri->state =3D=3D ARM_CP_STATE_AA32) { + oslock =3D (value =3D=3D 0xC5ACCE55); + } else { + oslock =3D value & 1; + } + + env->cp15.oslsr_el1 =3D deposit32(env->cp15.oslsr_el1, 1, 1, oslock); +} + +static const ARMCPRegInfo debug_cp_reginfo[] =3D { + /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped + * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; + * unlike DBGDRAR it is never accessible from EL0. + * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 + * accessor. + */ + { .name =3D "DBGDRAR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "MDRAR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DBGDSAR", .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* Monitor debug system control register; the 32-bit alias is DBGDSCRe= xt. */ + { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), + .resetvalue =3D 0 }, + /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. + * We don't implement the configurable EL0 access. + */ + { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 = =3D 0, + .type =3D ARM_CP_ALIAS, + .access =3D PL1_R, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), }, + { .name =3D "OSLAR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_tdosa, + .writefn =3D oslar_write }, + { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, + .access =3D PL1_R, .resetvalue =3D 10, + .accessfn =3D access_tdosa, + .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, + /* Dummy OSDLR_EL1: 32-bit Linux will read this */ + { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, + .access =3D PL1_RW, .accessfn =3D access_tdosa, + .type =3D ARM_CP_NOP }, + /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't + * implement vector catch debug events yet. + */ + { .name =3D "DBGVCR", + .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP }, + /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + * to save and restore a 32-bit guest's DBGVCR) + */ + { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP }, + /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications + * Channel but Linux may try to access this register. The 32-bit + * alias is DBGDCCINT. + */ + { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { + /* 64 bit access versions of the (dummy) debug registers */ + { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, + { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, + REGINFO_SENTINEL +}; + +void hw_watchpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + vaddr len =3D 0; + vaddr wvr =3D env->cp15.dbgwvr[n]; + uint64_t wcr =3D env->cp15.dbgwcr[n]; + int mask; + int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + + if (env->cpu_watchpoint[n]) { + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); + env->cpu_watchpoint[n] =3D NULL; + } + + if (!extract64(wcr, 0, 1)) { + /* E bit clear : watchpoint disabled */ + return; + } + + switch (extract64(wcr, 3, 2)) { + case 0: + /* LSC 00 is reserved and must behave as if the wp is disabled */ + return; + case 1: + flags |=3D BP_MEM_READ; + break; + case 2: + flags |=3D BP_MEM_WRITE; + break; + case 3: + flags |=3D BP_MEM_ACCESS; + break; + } + + /* Attempts to use both MASK and BAS fields simultaneously are + * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, + * thus generating a watchpoint for every byte in the masked region. + */ + mask =3D extract64(wcr, 24, 4); + if (mask =3D=3D 1 || mask =3D=3D 2) { + /* Reserved values of MASK; we must act as if the mask value was + * some non-reserved value, or as if the watchpoint were disabled. + * We choose the latter. + */ + return; + } else if (mask) { + /* Watchpoint covers an aligned area up to 2GB in size */ + len =3D 1ULL << mask; + /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE + * whether the watchpoint fires when the unmasked bits match; we o= pt + * to generate the exceptions. + */ + wvr &=3D ~(len - 1); + } else { + /* Watchpoint covers bytes defined by the byte address select bits= */ + int bas =3D extract64(wcr, 5, 8); + int basstart; + + if (bas =3D=3D 0) { + /* This must act as if the watchpoint is disabled */ + return; + } + + if (extract64(wvr, 2, 1)) { + /* Deprecated case of an only 4-aligned address. BAS[7:4] are + * ignored, and BAS[3:0] define which bytes to watch. + */ + bas &=3D 0xf; + } + /* The BAS bits are supposed to be programmed to indicate a contig= uous + * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er + * we fire for each byte in the word/doubleword addressed by the W= VR. + * We choose to ignore any non-zero bits after the first range of = 1s. + */ + basstart =3D ctz32(bas); + len =3D cto32(bas >> basstart); + wvr +=3D basstart; + } + + cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, + &env->cpu_watchpoint[n]); +} + +void hw_watchpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; + + /* Completely clear out existing QEMU watchpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { + hw_watchpoint_update(cpu, i); + } +} + +static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + int i =3D ri->crm; + + /* Bits [63:49] are hardwired to the value of bit [48]; that is, the + * register reads and behaves as if values written are sign extended. + * Bits [1:0] are RES0. + */ + value =3D sextract64(value, 0, 49) & ~3ULL; + + raw_write(env, ri, value); + hw_watchpoint_update(cpu, i); +} + +static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + int i =3D ri->crm; + + raw_write(env, ri, value); + hw_watchpoint_update(cpu, i); +} + +void hw_breakpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + uint64_t bvr =3D env->cp15.dbgbvr[n]; + uint64_t bcr =3D env->cp15.dbgbcr[n]; + vaddr addr; + int bt; + int flags =3D BP_CPU; + + if (env->cpu_breakpoint[n]) { + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); + env->cpu_breakpoint[n] =3D NULL; + } + + if (!extract64(bcr, 0, 1)) { + /* E bit clear : watchpoint disabled */ + return; + } + + bt =3D extract64(bcr, 20, 4); + + switch (bt) { + case 4: /* unlinked address mismatch (reserved if AArch64) */ + case 5: /* linked address mismatch (reserved if AArch64) */ + qemu_log_mask(LOG_UNIMP, + "arm: address mismatch breakpoint types not implemen= ted"); + return; + case 0: /* unlinked address match */ + case 1: /* linked address match */ + { + /* Bits [63:49] are hardwired to the value of bit [48]; that is, + * we behave as if the register was sign extended. Bits [1:0] are + * RES0. The BAS field is used to allow setting breakpoints on 16 + * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether + * a bp will fire if the addresses covered by the bp and the addre= sses + * covered by the insn overlap but the insn doesn't start at the + * start of the bp address range. We choose to require the insn and + * the bp to have the same address. The constraints on writing to + * BAS enforced in dbgbcr_write mean we have only four cases: + * 0b0000 =3D> no breakpoint + * 0b0011 =3D> breakpoint on addr + * 0b1100 =3D> breakpoint on addr + 2 + * 0b1111 =3D> breakpoint on addr + * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). + */ + int bas =3D extract64(bcr, 5, 4); + addr =3D sextract64(bvr, 0, 49) & ~3ULL; + if (bas =3D=3D 0) { + return; + } + if (bas =3D=3D 0xc) { + addr +=3D 2; + } + break; + } + case 2: /* unlinked context ID match */ + case 8: /* unlinked VMID match (reserved if no EL2) */ + case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ + qemu_log_mask(LOG_UNIMP, + "arm: unlinked context breakpoint types not implemen= ted"); + return; + case 9: /* linked VMID match (reserved if no EL2) */ + case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 3: /* linked context ID match */ + default: + /* We must generate no events for Linked context matches (unless + * they are linked to by some other bp/wp, which is handled in + * updates for the linking bp/wp). We choose to also generate no e= vents + * for reserved values. + */ + return; + } + + cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); +} + +void hw_breakpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; + + /* Completely clear out existing QEMU breakpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { + hw_breakpoint_update(cpu, i); + } +} + +static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + int i =3D ri->crm; + + raw_write(env, ri, value); + hw_breakpoint_update(cpu, i); +} + +static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + int i =3D ri->crm; + + /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only + * copy of BAS[0]. + */ + value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); + value =3D deposit64(value, 8, 1, extract64(value, 7, 1)); + + raw_write(env, ri, value); + hw_breakpoint_update(cpu, i); +} + +static void define_debug_regs(ARMCPU *cpu) +{ + /* Define v7 and v8 architectural debug registers. + * These are just dummy implementations for now. + */ + int i; + int wrps, brps, ctx_cmps; + ARMCPRegInfo dbgdidr =3D { + .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->dbgdidr, + }; + + /* Note that all these register fields hold "number of Xs minus 1". */ + brps =3D extract32(cpu->dbgdidr, 24, 4); + wrps =3D extract32(cpu->dbgdidr, 28, 4); + ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); + + assert(ctx_cmps <=3D brps); + + /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties + * of the debug registers such as number of breakpoints; + * check that if they both exist then they agree. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + assert(extract32(cpu->id_aa64dfr0, 12, 4) =3D=3D brps); + assert(extract32(cpu->id_aa64dfr0, 20, 4) =3D=3D wrps); + assert(extract32(cpu->id_aa64dfr0, 28, 4) =3D=3D ctx_cmps); + } + + define_one_arm_cp_reg(cpu, &dbgdidr); + define_arm_cp_regs(cpu, debug_cp_reginfo); + + if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { + define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); + } + + for (i =3D 0; i < brps + 1; i++) { + ARMCPRegInfo dbgregs[] =3D { + { .name =3D "DBGBVR", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), + .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write + }, + { .name =3D "DBGBCR", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), + .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write + }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, dbgregs); + } + + for (i =3D 0; i < wrps + 1; i++) { + ARMCPRegInfo dbgregs[] =3D { + { .name =3D "DBGWVR", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), + .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write + }, + { .name =3D "DBGWCR", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), + .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write + }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, dbgregs); + } +} + +void register_cp_regs_for_features(ARMCPU *cpu) +{ + /* Register all the coprocessor registers based on feature bits */ + CPUARMState *env =3D &cpu->env; + if (arm_feature(env, ARM_FEATURE_M)) { + /* M profile has no coprocessor registers */ + return; + } + + define_arm_cp_regs(cpu, cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_V8)) { + /* Must go early as it is full of wildcards that may be + * overridden by later definitions. + */ + define_arm_cp_regs(cpu, not_v8_cp_reginfo); + } + + if (arm_feature(env, ARM_FEATURE_V6)) { + /* The ID registers all have impdef reset values */ + ARMCPRegInfo v6_idregs[] =3D { + { .name =3D "ID_PFR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_pfr0 }, + { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_pfr1 }, + { .name =3D "ID_DFR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_dfr0 }, + { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_afr0 }, + { .name =3D "ID_MMFR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_mmfr0 }, + { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_mmfr1 }, + { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_mmfr2 }, + { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_mmfr3 }, + { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_isar0 }, + { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_isar1 }, + { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_isar2 }, + { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_isar3 }, + { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_isar4 }, + { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_isar5 }, + { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_mmfr4 }, + /* 7 is as yet unallocated and must RAZ */ + { .name =3D "ID_ISAR7_RESERVED", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, v6_idregs); + define_arm_cp_regs(cpu, v6_cp_reginfo); + } else { + define_arm_cp_regs(cpu, not_v6_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V6K)) { + define_arm_cp_regs(cpu, v6k_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V7MP) && + !arm_feature(env, ARM_FEATURE_MPU)) { + define_arm_cp_regs(cpu, v7mp_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V7)) { + /* v7 performance monitor control register: same implementor + * field as main ID register, and we implement only the cycle + * count register. + */ +#ifndef CONFIG_USER_ONLY + ARMCPRegInfo pmcr =3D { + .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL0_RW, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), + .accessfn =3D pmreg_access, .writefn =3D pmcr_write, + .raw_writefn =3D raw_write, + }; + ARMCPRegInfo pmcr64 =3D { + .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), + .resetvalue =3D cpu->midr & 0xff000000, + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, + }; + define_one_arm_cp_reg(cpu, &pmcr); + define_one_arm_cp_reg(cpu, &pmcr64); +#endif + ARMCPRegInfo clidr =3D { + .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu= ->clidr + }; + define_one_arm_cp_reg(cpu, &clidr); + define_arm_cp_regs(cpu, v7_cp_reginfo); + define_debug_regs(cpu); + } else { + define_arm_cp_regs(cpu, not_v7_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V8)) { + /* AArch64 ID registers, which all have impdef reset values. + * Note that within the ID register ranges the unused slots + * must all RAZ, not UNDEF; future architecture versions may + * define new registers here. + */ + ARMCPRegInfo v8_idregs[] =3D { + { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64pfr0 }, + { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64pfr1}, + { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR4_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR5_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR7_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64dfr0 }, + { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64dfr1 }, + { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64DFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64AFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64afr0 }, + { .name =3D "ID_AA64AFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64afr1 }, + { .name =3D "ID_AA64AFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64AFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64isar0 }, + { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64isar1 }, + { .name =3D "ID_AA64ISAR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64mmfr0 }, + { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->id_aa64mmfr1 }, + { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "MVFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->mvfr0 }, + { .name =3D "MVFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->mvfr1 }, + { .name =3D "MVFR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->mvfr2 }, + { .name =3D "MVFR3_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "MVFR4_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "MVFR5_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "MVFR6_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "MVFR7_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D cpu->pmceid0 }, + { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D cpu->pmceid0 }, + { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D cpu->pmceid1 }, + { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D cpu->pmceid1 }, + REGINFO_SENTINEL + }; + /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ + if (!arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2)) { + ARMCPRegInfo rvbar =3D { + .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, + .type =3D ARM_CP_CONST, .access =3D PL1_R, .resetvalue =3D= cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); + } + define_arm_cp_regs(cpu, v8_idregs); + define_arm_cp_regs(cpu, v8_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL2)) { + uint64_t vmpidr_def =3D mpidr_read_val(env); + ARMCPRegInfo vpidr_regs[] =3D { + { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .resetvalue =3D cpu->midr, + .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, + { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, + .access =3D PL2_RW, .resetvalue =3D cpu->midr, + .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, + { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .resetvalue =3D vmpidr_def, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, + { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 5, + .access =3D PL2_RW, + .resetvalue =3D vmpidr_def, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vpidr_regs); + define_arm_cp_regs(cpu, el2_cp_reginfo); + /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + ARMCPRegInfo rvbar =3D { + .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, + .type =3D ARM_CP_CONST, .access =3D PL2_R, .resetvalue =3D= cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); + } + } else { + /* If EL2 is missing but higher ELs are enabled, we need to + * register the no_el2 reginfos. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value + * of MIDR_EL1 and MPIDR_EL1. + */ + ARMCPRegInfo vpidr_regs[] =3D { + { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64= any, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, + .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, + { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64= any, + .type =3D ARM_CP_NO_RAW, + .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vpidr_regs); + define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); + } + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_arm_cp_regs(cpu, el3_cp_reginfo); + ARMCPRegInfo el3_regs[] =3D { + { .name =3D "RVBAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D= 1, + .type =3D ARM_CP_CONST, .access =3D PL3_R, .resetvalue =3D c= pu->rvbar }, + { .name =3D "SCTLR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 0, + .access =3D PL3_RW, + .raw_writefn =3D raw_write, .writefn =3D sctlr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), + .resetvalue =3D cpu->reset_sctlr }, + REGINFO_SENTINEL + }; + + define_arm_cp_regs(cpu, el3_regs); + } + /* The behaviour of NSACR is sufficiently various that we don't + * try to describe it in a single reginfo: + * if EL3 is 64 bit, then trap to EL3 from S EL1, + * reads as constant 0xc00 from NS EL1 and NS EL2 + * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 + * if v7 without EL3, register doesn't exist + * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + ARMCPRegInfo nsacr =3D { + .name =3D "NSACR", .type =3D ARM_CP_CONST, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, + .access =3D PL1_RW, .accessfn =3D nsacr_access, + .resetvalue =3D 0xc00 + }; + define_one_arm_cp_reg(cpu, &nsacr); + } else { + ARMCPRegInfo nsacr =3D { + .name =3D "NSACR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, + .access =3D PL3_RW | PL1_R, + .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.nsacr) + }; + define_one_arm_cp_reg(cpu, &nsacr); + } + } else { + if (arm_feature(env, ARM_FEATURE_V8)) { + ARMCPRegInfo nsacr =3D { + .name =3D "NSACR", .type =3D ARM_CP_CONST, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, + .access =3D PL1_R, + .resetvalue =3D 0xc00 + }; + define_one_arm_cp_reg(cpu, &nsacr); + } + } + + if (arm_feature(env, ARM_FEATURE_MPU)) { + if (arm_feature(env, ARM_FEATURE_V6)) { + /* PMSAv6 not implemented */ + assert(arm_feature(env, ARM_FEATURE_V7)); + define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); + define_arm_cp_regs(cpu, pmsav7_cp_reginfo); + } else { + define_arm_cp_regs(cpu, pmsav5_cp_reginfo); + } + } else { + define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); + define_arm_cp_regs(cpu, vmsa_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + define_arm_cp_regs(cpu, t2ee_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + define_arm_cp_regs(cpu, generic_timer_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_VAPA)) { + define_arm_cp_regs(cpu, vapa_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { + define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { + define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { + define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_OMAPCP)) { + define_arm_cp_regs(cpu, omap_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_STRONGARM)) { + define_arm_cp_regs(cpu, strongarm_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + define_arm_cp_regs(cpu, xscale_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { + define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_LPAE)) { + define_arm_cp_regs(cpu, lpae_cp_reginfo); + } + /* Slightly awkwardly, the OMAP and StrongARM cores need all of + * cp15 crn=3D0 to be writes-ignored, whereas for other cores they sho= uld + * be read-only (ie write causes UNDEF exception). + */ + { + ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] =3D { + /* Pre-v8 MIDR space. + * Note that the MIDR isn't a simple constant register because + * of the TI925 behaviour where writes to another register can + * cause the MIDR value to change. + * + * Unimplemented registers in the c15 0 0 0 space default to + * MIDR. Define MIDR first as this entire space, then CTR, TCM= TR + * and friends override accordingly. + */ + { .name =3D "MIDR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .resetvalue =3D cpu->midr, + .writefn =3D arm_cp_write_ignore, .raw_writefn =3D raw_write, + .readfn =3D midr_read, + .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), + .type =3D ARM_CP_OVERRIDE }, + /* crn =3D 0 op1 =3D 0 crm =3D 3..7 : currently unassigned; we= RAZ. */ + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 3, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 4, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 5, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 6, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 7, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + REGINFO_SENTINEL + }; + ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { + { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, + .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), + .readfn =3D midr_read }, + /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ + { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .resetvalue =3D cpu->midr }, + { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, + .access =3D PL1_R, .resetvalue =3D cpu->midr }, + { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->revidr }, + REGINFO_SENTINEL + }; + ARMCPRegInfo id_cp_reginfo[] =3D { + /* These are common to v8 and pre-v8 */ + { .name =3D "CTR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->ctr }, + { .name =3D "CTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 0, .crm =3D = 0, + .access =3D PL0_R, .accessfn =3D ctr_el0_access, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, + /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ + { .name =3D "TCMTR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + REGINFO_SENTINEL + }; + /* TLBTR is specific to VMSA */ + ARMCPRegInfo id_tlbtr_reginfo =3D { + .name =3D "TLBTR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0, + }; + /* MPUIR is specific to PMSA V6+ */ + ARMCPRegInfo id_mpuir_reginfo =3D { + .name =3D "MPUIR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->pmsav7_dregion << 8 + }; + ARMCPRegInfo crn0_wi_reginfo =3D { + .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, + .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE + }; + if (arm_feature(env, ARM_FEATURE_OMAPCP) || + arm_feature(env, ARM_FEATURE_STRONGARM)) { + ARMCPRegInfo *r; + /* Register the blanket "writes ignored" value first to cover = the + * whole space. Then update the specific ID registers to allow= write + * access, so that they ignore writes rather than causing them= to + * UNDEF. + */ + define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); + for (r =3D id_pre_v8_midr_cp_reginfo; + r->type !=3D ARM_CP_SENTINEL; r++) { + r->access =3D PL1_RW; + } + for (r =3D id_cp_reginfo; r->type !=3D ARM_CP_SENTINEL; r++) { + r->access =3D PL1_RW; + } + id_tlbtr_reginfo.access =3D PL1_RW; + id_tlbtr_reginfo.access =3D PL1_RW; + } + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); + } else { + define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); + } + define_arm_cp_regs(cpu, id_cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_MPU)) { + define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + } + } + + if (arm_feature(env, ARM_FEATURE_MPIDR)) { + define_arm_cp_regs(cpu, mpidr_cp_reginfo); + } + + if (arm_feature(env, ARM_FEATURE_AUXCR)) { + ARMCPRegInfo auxcr_reginfo[] =3D { + { .name =3D "ACTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->reset_auxcr }, + { .name =3D "ACTLR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ACTLR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, auxcr_reginfo); + } + + if (arm_feature(env, ARM_FEATURE_CBAR)) { + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* 32 bit view is [31:18] 0...0 [43:32]. */ + uint32_t cbar32 =3D (extract64(cpu->reset_cbar, 18, 14) << 18) + | extract64(cpu->reset_cbar, 32, 12); + ARMCPRegInfo cbar_reginfo[] =3D { + { .name =3D "CBAR", + .type =3D ARM_CP_CONST, + .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 4, .opc2 = =3D 0, + .access =3D PL1_R, .resetvalue =3D cpu->reset_cbar }, + { .name =3D "CBAR_EL1", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_CONST, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2= =3D 0, + .access =3D PL1_R, .resetvalue =3D cbar32 }, + REGINFO_SENTINEL + }; + /* We don't implement a r/w 64 bit CBAR currently */ + assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); + define_arm_cp_regs(cpu, cbar_reginfo); + } else { + ARMCPRegInfo cbar =3D { + .name =3D "CBAR", + .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 4, .opc2 = =3D 0, + .access =3D PL1_R|PL3_W, .resetvalue =3D cpu->reset_cbar, + .fieldoffset =3D offsetof(CPUARMState, + cp15.c15_config_base_address) + }; + if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { + cbar.access =3D PL1_R; + cbar.fieldoffset =3D 0; + cbar.type =3D ARM_CP_CONST; + } + define_one_arm_cp_reg(cpu, &cbar); + } + } + + if (arm_feature(env, ARM_FEATURE_VBAR)) { + ARMCPRegInfo vbar_cp_reginfo[] =3D { + { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, + .access =3D PL1_RW, .writefn =3D vbar_write, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), + offsetof(CPUARMState, cp15.vbar_ns) }, + .resetvalue =3D 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vbar_cp_reginfo); + } + + /* Generic registers whose values depend on the implementation */ + { + ARMCPRegInfo sctlr =3D { + .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), + offsetof(CPUARMState, cp15.sctlr_ns) }, + .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, + .raw_writefn =3D raw_write, + }; + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + /* Normally we would always end the TB on an SCTLR write, but = Linux + * arch/arm/mach-pxa/sleep.S expects two instructions following + * an MMU enable to execute from cache. Imitate this behaviou= r. + */ + sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; + } + define_one_arm_cp_reg(cpu, &sctlr); + } +} + +ARMCPU *cpu_arm_init(const char *cpu_model) +{ + return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); +} + +void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, + aarch64_fpu_gdb_set_reg, + 34, "aarch64-fpu.xml", 0); + } else if (arm_feature(env, ARM_FEATURE_NEON)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 51, "arm-neon.xml", 0); + } else if (arm_feature(env, ARM_FEATURE_VFP3)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 35, "arm-vfp3.xml", 0); + } else if (arm_feature(env, ARM_FEATURE_VFP)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 19, "arm-vfp.xml", 0); + } +} + +/* Sort alphabetically by type name, except for "any". */ +static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) +{ + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; + const char *name_a, *name_b; + + name_a =3D object_class_get_name(class_a); + name_b =3D object_class_get_name(class_b); + if (strcmp(name_a, "any-" TYPE_ARM_CPU) =3D=3D 0) { + return 1; + } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) =3D=3D 0) { + return -1; + } else { + return strcmp(name_a, name_b); + } +} + +static void arm_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CPUListState *s =3D user_data; + const char *typename; + char *name; + + typename =3D object_class_get_name(oc); + name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CP= U)); + (*s->cpu_fprintf)(s->file, " %s\n", + name); + g_free(name); +} + +void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + CPUListState s =3D { + .file =3D f, + .cpu_fprintf =3D cpu_fprintf, + }; + GSList *list; + + list =3D object_class_get_list(TYPE_ARM_CPU, false); + list =3D g_slist_sort(list, arm_cpu_list_compare); + (*cpu_fprintf)(f, "Available CPUs:\n"); + g_slist_foreach(list, arm_cpu_list_entry, &s); + g_slist_free(list); +#ifdef CONFIG_KVM + /* The 'host' CPU type is dynamically registered only if KVM is + * enabled, so we have to special-case it here: + */ + (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); +#endif +} + +static void arm_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CpuDefinitionInfoList **cpu_list =3D user_data; + CpuDefinitionInfoList *entry; + CpuDefinitionInfo *info; + const char *typename; + + typename =3D object_class_get_name(oc); + info =3D g_malloc0(sizeof(*info)); + info->name =3D g_strndup(typename, + strlen(typename) - strlen("-" TYPE_ARM_CPU)); + info->q_typename =3D g_strdup(typename); + + entry =3D g_malloc0(sizeof(*entry)); + entry->value =3D info; + entry->next =3D *cpu_list; + *cpu_list =3D entry; +} + +CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list =3D NULL; + GSList *list; + + list =3D object_class_get_list(TYPE_ARM_CPU, false); + g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +} + +static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, + void *opaque, int state, int secstate, + int crm, int opc1, int opc2) +{ + /* Private utility function for define_one_arm_cp_reg_with_opaque(): + * add a single reginfo struct to the hash table. + */ + uint32_t *key =3D g_new(uint32_t, 1); + ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); + int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; + int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + + /* Reset the secure state to the specific incoming state. This is + * necessary as the register may have been defined with both states. + */ + r2->secure =3D secstate; + + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* Register is banked (using both entries in array). + * Overwriting fieldoffset as the array is only used to define + * banked registers but later only fieldoffset is used. + */ + r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + } + + if (state =3D=3D ARM_CP_STATE_AA32) { + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* If the register is banked then we don't need to migrate or + * reset the 32-bit instance in certain cases: + * + * 1) If the register has both 32-bit and 64-bit instances the= n we + * can count on the 64-bit instance taking care of the + * non-secure bank. + * 2) If ARMv8 is enabled then we can count on a 64-bit version + * taking care of the secure bank. This requires that sepa= rate + * 32 and 64-bit definitions are provided. + */ + if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || + (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { + r2->type |=3D ARM_CP_ALIAS; + } + } else if ((secstate !=3D r->secure) && !ns) { + /* The register is not banked so we only want to allow migrati= on of + * the non-secure instance. + */ + r2->type |=3D ARM_CP_ALIAS; + } + + if (r->state =3D=3D ARM_CP_STATE_BOTH) { + /* We assume it is a cp15 register if the .cp field is left un= set. + */ + if (r2->cp =3D=3D 0) { + r2->cp =3D 15; + } + +#ifdef HOST_WORDS_BIGENDIAN + if (r2->fieldoffset) { + r2->fieldoffset +=3D sizeof(uint32_t); + } +#endif + } + } + if (state =3D=3D ARM_CP_STATE_AA64) { + /* To allow abbreviation of ARMCPRegInfo + * definitions, we treat cp =3D=3D 0 as equivalent to + * the value for "standard guest-visible sysreg". + * STATE_BOTH definitions are also always "standard + * sysreg" in their AArch64 view (the .cp value may + * be non-zero for the benefit of the AArch32 view). + */ + if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { + r2->cp =3D CP_REG_ARM64_SYSREG_CP; + } + *key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, + r2->opc0, opc1, opc2); + } else { + *key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); + } + if (opaque) { + r2->opaque =3D opaque; + } + /* reginfo passed to helpers is correct for the actual access, + * and is never ARM_CP_STATE_BOTH: + */ + r2->state =3D state; + /* Make sure reginfo passed to helpers for wildcarded regs + * has the correct crm/opc1/opc2 for this reg, not CP_ANY: + */ + r2->crm =3D crm; + r2->opc1 =3D opc1; + r2->opc2 =3D opc2; + /* By convention, for wildcarded registers only the first + * entry is used for migration; the others are marked as + * ALIAS so we don't try to transfer the register + * multiple times. Special registers (ie NOP/WFI) are + * never migratable and not even raw-accessible. + */ + if ((r->type & ARM_CP_SPECIAL)) { + r2->type |=3D ARM_CP_NO_RAW; + } + if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || + ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || + ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { + r2->type |=3D ARM_CP_ALIAS; + } + + /* Check that raw accesses are either forbidden or handled. Note that + * we can't assert this earlier because the setup of fieldoffset for + * banked registers has to be done first. + */ + if (!(r2->type & ARM_CP_NO_RAW)) { + assert(!raw_accessors_invalid(r2)); + } + + /* Overriding of an existing definition must be explicitly + * requested. + */ + if (!(r->type & ARM_CP_OVERRIDE)) { + ARMCPRegInfo *oldreg; + oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); + if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { + fprintf(stderr, "Register redefined: cp=3D%d %d bit " + "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " + "was %s, now %s\n", r2->cp, 32 + 32 * is64, + r2->crn, r2->crm, r2->opc1, r2->opc2, + oldreg->name, r2->name); + g_assert_not_reached(); + } + } + g_hash_table_insert(cpu->cp_regs, key, r2); +} + + +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *r, void *opaque) +{ + /* Define implementations of coprocessor registers. + * We store these in a hashtable because typically + * there are less than 150 registers in a space which + * is 16*16*16*8*8 =3D 262144 in size. + * Wildcarding is supported for the crm, opc1 and opc2 fields. + * If a register is defined twice then the second definition is + * used, so this can be used to define some generic registers and + * then override them with implementation specific variations. + * At least one of the original and the second definition should + * include ARM_CP_OVERRIDE in its type bits -- this is just a guard + * against accidental use. + * + * The state field defines whether the register is to be + * visible in the AArch32 or AArch64 execution state. If the + * state is set to ARM_CP_STATE_BOTH then we synthesise a + * reginfo structure for the AArch32 view, which sees the lower + * 32 bits of the 64 bit register. + * + * Only registers visible in AArch64 may set r->opc0; opc0 cannot + * be wildcarded. AArch64 registers are always considered to be 64 + * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of + * the register, if any. + */ + int crm, opc1, opc2, state; + int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; + int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; + int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; + int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; + int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; + int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; + /* 64 bit registers have only CRm and Opc1 fields */ + assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); + /* op0 only exists in the AArch64 encodings */ + assert((r->state !=3D ARM_CP_STATE_AA32) || (r->opc0 =3D=3D 0)); + /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ + assert((r->state !=3D ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); + /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 + * encodes a minimum access level for the register. We roll this + * runtime check into our general permission check code, so check + * here that the reginfo's specified permissions are strict enough + * to encompass the generic architectural permission check. + */ + if (r->state !=3D ARM_CP_STATE_AA32) { + int mask =3D 0; + switch (r->opc1) { + case 0: case 1: case 2: + /* min_EL EL1 */ + mask =3D PL1_RW; + break; + case 3: + /* min_EL EL0 */ + mask =3D PL0_RW; + break; + case 4: + /* min_EL EL2 */ + mask =3D PL2_RW; + break; + case 5: + /* unallocated encoding, so not possible */ + assert(false); + break; + case 6: + /* min_EL EL3 */ + mask =3D PL3_RW; + break; + case 7: + /* min_EL EL1, secure mode only (we don't check the latter) */ + mask =3D PL1_RW; + break; + default: + /* broken reginfo with out-of-range opc1 */ + assert(false); + break; + } + /* assert our permissions are not too lax (stricter is fine) */ + assert((r->access & ~mask) =3D=3D 0); + } + + /* Check that the register definition has enough info to handle + * reads and writes if they are permitted. + */ + if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { + if (r->access & PL3_R) { + assert((r->fieldoffset || + (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || + r->readfn); + } + if (r->access & PL3_W) { + assert((r->fieldoffset || + (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || + r->writefn); + } + } + /* Bad type field probably means missing sentinel at end of reg list */ + assert(cptype_valid(r->type)); + for (crm =3D crmmin; crm <=3D crmmax; crm++) { + for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { + for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { + for (state =3D ARM_CP_STATE_AA32; + state <=3D ARM_CP_STATE_AA64; state++) { + if (r->state !=3D state && r->state !=3D ARM_CP_STATE_= BOTH) { + continue; + } + if (state =3D=3D ARM_CP_STATE_AA32) { + /* Under AArch32 CP registers can be common + * (same for secure and non-secure world) or banke= d. + */ + switch (r->secure) { + case ARM_CP_SECSTATE_S: + case ARM_CP_SECSTATE_NS: + add_cpreg_to_hashtable(cpu, r, opaque, state, + r->secure, crm, opc1, o= pc2); + break; + default: + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_S, + crm, opc1, opc2); + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_NS, + crm, opc1, opc2); + break; + } + } else { + /* AArch64 registers get mapped to non-secure inst= ance + * of AArch32 */ + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_NS, + crm, opc1, opc2); + } + } + } + } + } +} + +void define_arm_cp_regs_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opaque) +{ + /* Define a whole list of registers */ + const ARMCPRegInfo *r; + for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { + define_one_arm_cp_reg_with_opaque(cpu, r, opaque); + } +} + +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Helper coprocessor write function for write-ignore registers */ +} + +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Helper coprocessor write function for read-as-zero registers */ + return 0; +} + +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) +{ + /* Helper coprocessor reset function for do-nothing-on-reset registers= */ +} + +static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) +{ + /* Return true if it is not valid for us to switch to + * this CPU mode (ie all the UNPREDICTABLE cases in + * the ARM ARM CPSRWriteByInstr pseudocode). + */ + + /* Changes to or from Hyp via MSR and CPS are illegal. */ + if (write_type =3D=3D CPSRWriteByInstr && + ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_HYP || + mode =3D=3D ARM_CPU_MODE_HYP)) { + return 1; + } + + switch (mode) { + case ARM_CPU_MODE_USR: + return 0; + case ARM_CPU_MODE_SYS: + case ARM_CPU_MODE_SVC: + case ARM_CPU_MODE_ABT: + case ARM_CPU_MODE_UND: + case ARM_CPU_MODE_IRQ: + case ARM_CPU_MODE_FIQ: + /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 + * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) + */ + /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR + * and CPS are treated as illegal mode changes. + */ + if (write_type =3D=3D CPSRWriteByInstr && + (env->cp15.hcr_el2 & HCR_TGE) && + (env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON && + !arm_is_secure_below_el3(env)) { + return 1; + } + return 0; + case ARM_CPU_MODE_HYP: + return !arm_feature(env, ARM_FEATURE_EL2) + || arm_current_el(env) < 2 || arm_is_secure(env); + case ARM_CPU_MODE_MON: + return arm_current_el(env) < 3; + default: + return 1; + } +} + +uint32_t cpsr_read(CPUARMState *env) +{ + int ZF; + ZF =3D (env->ZF =3D=3D 0); + return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | + (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) + | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) + | ((env->condexec_bits & 0xfc) << 8) + | (env->GE << 16) | (env->daif & CPSR_AIF); +} + +void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, + CPSRWriteType write_type) +{ + uint32_t changed_daif; + + if (mask & CPSR_NZCV) { + env->ZF =3D (~val) & CPSR_Z; + env->NF =3D val; + env->CF =3D (val >> 29) & 1; + env->VF =3D (val << 3) & 0x80000000; + } + if (mask & CPSR_Q) + env->QF =3D ((val & CPSR_Q) !=3D 0); + if (mask & CPSR_T) + env->thumb =3D ((val & CPSR_T) !=3D 0); + if (mask & CPSR_IT_0_1) { + env->condexec_bits &=3D ~3; + env->condexec_bits |=3D (val >> 25) & 3; + } + if (mask & CPSR_IT_2_7) { + env->condexec_bits &=3D 3; + env->condexec_bits |=3D (val >> 8) & 0xfc; + } + if (mask & CPSR_GE) { + env->GE =3D (val >> 16) & 0xf; + } + + /* In a V7 implementation that includes the security extensions but do= es + * not include Virtualization Extensions the SCR.FW and SCR.AW bits co= ntrol + * whether non-secure software is allowed to change the CPSR_F and CPS= R_A + * bits respectively. + * + * In a V8 implementation, it is permitted for privileged software to + * change the CPSR A/F bits regardless of the SCR.AW/FW bits. + */ + if (write_type !=3D CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) = && + arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2) && + !arm_is_secure(env)) { + + changed_daif =3D (env->daif ^ val) & mask; + + if (changed_daif & CPSR_A) { + /* Check to see if we are allowed to change the masking of asy= nc + * abort exceptions from a non-secure state. + */ + if (!(env->cp15.scr_el3 & SCR_AW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_A flag from= " + "non-secure world with SCR.AW bit clear\n"); + mask &=3D ~CPSR_A; + } + } + + if (changed_daif & CPSR_F) { + /* Check to see if we are allowed to change the masking of FIQ + * exceptions from a non-secure state. + */ + if (!(env->cp15.scr_el3 & SCR_FW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_F flag from= " + "non-secure world with SCR.FW bit clear\n"); + mask &=3D ~CPSR_F; + } + + /* Check whether non-maskable FIQ (NMFI) support is enabled. + * If this bit is set software is not allowed to mask + * FIQs, but is allowed to set CPSR_F to 0. + */ + if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && + (val & CPSR_F)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to enable CPSR_F flag " + "(non-maskable FIQ [NMFI] support enabled)\n= "); + mask &=3D ~CPSR_F; + } + } + } + + env->daif &=3D ~(CPSR_AIF & mask); + env->daif |=3D val & CPSR_AIF & mask; + + if (write_type !=3D CPSRWriteRaw && + ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_USR) { + /* Note that we can only get here in USR mode if this is a + * gdb stub write; for this case we follow the architectural + * behaviour for guest writes in USR mode of ignoring an attem= pt + * to switch mode. (Those are caught by translate.c for writes + * triggered by guest instructions.) + */ + mask &=3D ~CPSR_M; + } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { + /* Attempt to switch to an invalid mode: this is UNPREDICTABLE= in + * v7, and has defined behaviour in v8: + * + leave CPSR.M untouched + * + allow changes to the other CPSR fields + * + set PSTATE.IL + * For user changes via the GDB stub, we don't set PSTATE.IL, + * as this would be unnecessarily harsh for a user error. + */ + mask &=3D ~CPSR_M; + if (write_type !=3D CPSRWriteByGDBStub && + arm_feature(env, ARM_FEATURE_V8)) { + mask |=3D CPSR_IL; + val |=3D CPSR_IL; + } + } else { + switch_mode(env, val & CPSR_M); + } + } + mask &=3D ~CACHED_CPSR_BITS; + env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); +} diff --git a/target/arm/helper.c b/target/arm/helper.c index d4075d2afb..8e0d442198 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1,5753 +1,20 @@ #include "qemu/osdep.h" -#include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" -#include "sysemu/arch_init.h" -#include "sysemu/sysemu.h" -#include "qemu/bitops.h" #include "qemu/crc32c.h" -#include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "arm_ldst.h" #include /* For crc32 */ #include "exec/semihost.h" #include "sysemu/kvm.h" =20 -#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ - -#ifndef CONFIG_USER_ONLY -static bool get_phys_addr(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr, - ARMMMUFaultInfo *fi); - -static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, - target_ulong *page_size_ptr, uint32_t *fsr, - ARMMMUFaultInfo *fi); - -/* Definitions for the PMCCNTR and PMCR registers */ -#define PMCRD 0x8 -#define PMCRC 0x4 -#define PMCRE 0x1 -#endif - -static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) -{ - int nregs; - - /* VFP data registers are always little-endian. */ - nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; - if (reg < nregs) { - stfq_le_p(buf, env->vfp.regs[reg]); - return 8; - } - if (arm_feature(env, ARM_FEATURE_NEON)) { - /* Aliases for Q regs. */ - nregs +=3D 16; - if (reg < nregs) { - stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); - stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); - return 16; - } - } - switch (reg - nregs) { - case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; - case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; - case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; - } - return 0; -} - -static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) -{ - int nregs; - - nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; - if (reg < nregs) { - env->vfp.regs[reg] =3D ldfq_le_p(buf); - return 8; - } - if (arm_feature(env, ARM_FEATURE_NEON)) { - nregs +=3D 16; - if (reg < nregs) { - env->vfp.regs[(reg - 32) * 2] =3D ldfq_le_p(buf); - env->vfp.regs[(reg - 32) * 2 + 1] =3D ldfq_le_p(buf + 8); - return 16; - } - } - switch (reg - nregs) { - case 0: env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); return 4; - case 1: env->vfp.xregs[ARM_VFP_FPSCR] =3D ldl_p(buf); return 4; - case 2: env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf) & (1 << 30); retu= rn 4; - } - return 0; -} - -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) -{ - switch (reg) { - case 0 ... 31: - /* 128 bit FP register */ - stfq_le_p(buf, env->vfp.regs[reg * 2]); - stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); - return 16; - case 32: - /* FPSR */ - stl_p(buf, vfp_get_fpsr(env)); - return 4; - case 33: - /* FPCR */ - stl_p(buf, vfp_get_fpcr(env)); - return 4; - default: - return 0; - } -} - -static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) -{ - switch (reg) { - case 0 ... 31: - /* 128 bit FP register */ - env->vfp.regs[reg * 2] =3D ldfq_le_p(buf); - env->vfp.regs[reg * 2 + 1] =3D ldfq_le_p(buf + 8); - return 16; - case 32: - /* FPSR */ - vfp_set_fpsr(env, ldl_p(buf)); - return 4; - case 33: - /* FPCR */ - vfp_set_fpcr(env, ldl_p(buf)); - return 4; - default: - return 0; - } -} - -static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { - return CPREG_FIELD64(env, ri); - } else { - return CPREG_FIELD32(env, ri); - } -} - -static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { - CPREG_FIELD64(env, ri) =3D value; - } else { - CPREG_FIELD32(env, ri) =3D value; - } -} - -static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return (char *)env + ri->fieldoffset; -} - -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* Raw read of a coprocessor register (as needed for migration, etc). = */ - if (ri->type & ARM_CP_CONST) { - return ri->resetvalue; - } else if (ri->raw_readfn) { - return ri->raw_readfn(env, ri); - } else if (ri->readfn) { - return ri->readfn(env, ri); - } else { - return raw_read(env, ri); - } -} - -static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t v) -{ - /* Raw write of a coprocessor register (as needed for migration, etc). - * Note that constant registers are treated as write-ignored; the - * caller should check for success by whether a readback gives the - * value written. - */ - if (ri->type & ARM_CP_CONST) { - return; - } else if (ri->raw_writefn) { - ri->raw_writefn(env, ri, v); - } else if (ri->writefn) { - ri->writefn(env, ri, v); - } else { - raw_write(env, ri, v); - } -} - -static bool raw_accessors_invalid(const ARMCPRegInfo *ri) -{ - /* Return true if the regdef would cause an assertion if you called - * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a - * program bug for it not to have the NO_RAW flag). - * NB that returning false here doesn't necessarily mean that calling - * read/write_raw_cp_reg() is safe, because we can't distinguish "has - * read/write access functions which are safe for raw use" from "has - * read/write access functions which have side effects but has forgotten - * to provide raw access functions". - * The tests here line up with the conditions in read/write_raw_cp_reg() - * and assertions in raw_read()/raw_write(). - */ - if ((ri->type & ARM_CP_CONST) || - ri->fieldoffset || - ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn= ))) { - return false; - } - return true; -} - -bool write_cpustate_to_list(ARMCPU *cpu) -{ - /* Write the coprocessor state from cpu->env to the (index,value) list= . */ - int i; - bool ok =3D true; - - for (i =3D 0; i < cpu->cpreg_array_len; i++) { - uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); - const ARMCPRegInfo *ri; - - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); - if (!ri) { - ok =3D false; - continue; - } - if (ri->type & ARM_CP_NO_RAW) { - continue; - } - cpu->cpreg_values[i] =3D read_raw_cp_reg(&cpu->env, ri); - } - return ok; -} - -bool write_list_to_cpustate(ARMCPU *cpu) -{ - int i; - bool ok =3D true; - - for (i =3D 0; i < cpu->cpreg_array_len; i++) { - uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); - uint64_t v =3D cpu->cpreg_values[i]; - const ARMCPRegInfo *ri; - - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); - if (!ri) { - ok =3D false; - continue; - } - if (ri->type & ARM_CP_NO_RAW) { - continue; - } - /* Write value and confirm it reads back as written - * (to catch read-only registers and partially read-only - * registers where the incoming migration value doesn't match) - */ - write_raw_cp_reg(&cpu->env, ri, v); - if (read_raw_cp_reg(&cpu->env, ri) !=3D v) { - ok =3D false; - } - } - return ok; -} - -static void add_cpreg_to_list(gpointer key, gpointer opaque) -{ - ARMCPU *cpu =3D opaque; - uint64_t regidx; - const ARMCPRegInfo *ri; - - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); - - if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { - cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); - /* The value array need not be initialized at this point */ - cpu->cpreg_array_len++; - } -} - -static void count_cpreg(gpointer key, gpointer opaque) -{ - ARMCPU *cpu =3D opaque; - uint64_t regidx; - const ARMCPRegInfo *ri; - - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); - - if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { - cpu->cpreg_array_len++; - } -} - -static gint cpreg_key_compare(gconstpointer a, gconstpointer b) -{ - uint64_t aidx =3D cpreg_to_kvm_id(*(uint32_t *)a); - uint64_t bidx =3D cpreg_to_kvm_id(*(uint32_t *)b); - - if (aidx > bidx) { - return 1; - } - if (aidx < bidx) { - return -1; - } - return 0; -} - -void init_cpreg_list(ARMCPU *cpu) -{ - /* Initialise the cpreg_tuples[] array based on the cp_regs hash. - * Note that we require cpreg_tuples[] to be sorted by key ID. - */ - GList *keys; - int arraylen; - - keys =3D g_hash_table_get_keys(cpu->cp_regs); - keys =3D g_list_sort(keys, cpreg_key_compare); - - cpu->cpreg_array_len =3D 0; - - g_list_foreach(keys, count_cpreg, cpu); - - arraylen =3D cpu->cpreg_array_len; - cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_values =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; - cpu->cpreg_array_len =3D 0; - - g_list_foreach(keys, add_cpreg_to_list, cpu); - - assert(cpu->cpreg_array_len =3D=3D arraylen); - - g_list_free(keys); -} - -/* - * Some registers are not accessible if EL3.NS=3D0 and EL3 is using AArch3= 2 but - * they are accessible when EL3 is using AArch64 regardless of EL3.NS. - * - * access_el3_aa32ns: Used to check AArch32 register views. - * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. - */ -static CPAccessResult access_el3_aa32ns(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - bool secure =3D arm_is_secure_below_el3(env); - - assert(!arm_el_is_aa64(env, 3)); - if (secure) { - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - return CP_ACCESS_OK; -} - -static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - if (!arm_el_is_aa64(env, 3)) { - return access_el3_aa32ns(env, ri, isread); - } - return CP_ACCESS_OK; -} - -/* Some secure-only AArch32 registers trap to EL3 if used from - * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). - * Note that an access from Secure EL1 can only happen if EL3 is AArch64. - * We assume that the .access field is set to PL1_RW. - */ -static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 3) { - return CP_ACCESS_OK; - } - if (arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_EL3; - } - /* This will be EL1 NS and EL2 NS, which just UNDEF */ - return CP_ACCESS_TRAP_UNCATEGORIZED; -} - -/* Check for traps to "powerdown debug" registers, which are controlled - * by MDCR.TDOSA - */ -static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - int el =3D arm_current_el(env); - - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) - && !arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -/* Check for traps to "debug ROM" registers, which are controlled - * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. - */ -static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) - && !arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -/* Check for traps to general debug registers, which are controlled - * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. - */ -static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) - && !arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -/* Check for traps to performance monitor registers, which are controlled - * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. - */ -static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) - && !arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - raw_write(env, ri, value); - tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ -} - -static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - if (raw_read(env, ri) !=3D value) { - /* Unlike real hardware the qemu TLB uses virtual addresses, - * not modified virtual addresses, so this causes a TLB flush. - */ - tlb_flush(CPU(cpu)); - raw_write(env, ri, value); - } -} - -static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_MPU) - && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table - * format) this register includes the ASID, so do a TLB flush. - * For PMSA it is purely a process ID and no action is needed. - */ - tlb_flush(CPU(cpu)); - } - raw_write(env, ri, value); -} - -static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - tlb_flush(CPU(cpu)); -} - -static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); -} - -static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - tlb_flush(CPU(cpu)); -} - -static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); -} - -/* IS variants of TLB operations must affect all cores */ -static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush(other_cs); - } -} - -static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush(other_cs); - } -} - -static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); - } -} - -static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); - } -} - -static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D ENV_GET_CPU(env); - - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, - ARMMMUIdx_S2NS, -1); -} - -static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, - ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); - } -} - -static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate by IPA. This has to invalidate any structures that - * contain only stage 2 translation information, but does not need - * to apply to structures that contain combined stage 1 and stage 2 - * translation information. - * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. - */ - CPUState *cs =3D ENV_GET_CPU(env); - uint64_t pageaddr; - - if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { - return; - } - - pageaddr =3D sextract64(value << 12, 0, 40); - - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); -} - -static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *other_cs; - uint64_t pageaddr; - - if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { - return; - } - - pageaddr =3D sextract64(value << 12, 0, 40); - - CPU_FOREACH(other_cs) { - tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); - } -} - -static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D ENV_GET_CPU(env); - - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); -} - -static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); - } -} - -static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D ENV_GET_CPU(env); - uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); - - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); -} - -static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *other_cs; - uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); - - CPU_FOREACH(other_cs) { - tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); - } -} - -static const ARMCPRegInfo cp_reginfo[] =3D { - /* Define the secure and non-secure FCSE identifier CP registers - * separately because there is no secure bank in V8 (no _EL3). This a= llows - * the secure register to be properly reset and migrated. There is als= o no - * v8 EL1 version of the register so the non-secure instance stands al= one. - */ - { .name =3D "FCSEIDR(NS)", - .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, - .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_ns), - .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - { .name =3D "FCSEIDR(S)", - .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, - .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), - .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - /* Define the secure and non-secure context identifier CP registers - * separately because there is no secure bank in V8 (no _EL3). This a= llows - * the secure register to be properly reset and migrated. In the - * non-secure case, the 32-bit register will have reset and migration - * disabled during registration as it is handled by the 64-bit instanc= e. - */ - { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), - .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - { .name =3D "CONTEXTIDR(S)", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), - .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { - /* NB: Some of these registers exist in v8 but with more precise - * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginf= o[]). - */ - /* MMU Domain access control / MPU write buffer control */ - { .name =3D "DACR", - .cp =3D 15, .opc1 =3D CP_ANY, .crn =3D 3, .crm =3D CP_ANY, .opc2 =3D= CP_ANY, - .access =3D PL1_RW, .resetvalue =3D 0, - .writefn =3D dacr_write, .raw_writefn =3D raw_write, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), - offsetoflow32(CPUARMState, cp15.dacr_ns) } }, - /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. - * For v6 and v5, these mappings are overly broad. - */ - { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 0, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, - { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 1, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, - { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 4, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, - { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 8, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, - /* Cache maintenance ops; some of this space may be overridden later. = */ - { .name =3D "CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, - .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, - .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { - /* Not all pre-v6 cores implemented this WFI, so this is slightly - * over-broad. - */ - { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_WFI }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { - /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which - * is UNPREDICTABLE; we choose to NOP as most implementations do). - */ - { .name =3D "WFI_v6", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0,= .opc2 =3D 4, - .access =3D PL1_W, .type =3D ARM_CP_WFI }, - /* L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice - * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM a= nd - * OMAPCP will override this space. - */ - { .name =3D "DLOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_d= ata), - .resetvalue =3D 0 }, - { .name =3D "ILOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 1, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_i= nsn), - .resetvalue =3D 0 }, - /* v6 doesn't have the cache ID registers but Linux reads them anyway = */ - { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, = .opc2 =3D CP_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D 0 }, - /* We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; - * implementing it as RAZ means the "debug architecture version" bits - * will read as a reserved value, which should cause Linux to not try - * to use the debug hardware. - */ - { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* MMU TLB control. Note that the wildcarding means we cover not just - * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. - */ - { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, .writefn =3D tlbia= ll_write, - .type =3D ARM_CP_NO_RAW }, - { .name =3D "TLBIMVA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, .writefn =3D tlbim= va_write, - .type =3D ARM_CP_NO_RAW }, - { .name =3D "TLBIASID", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, .writefn =3D tlbia= sid_write, - .type =3D ARM_CP_NO_RAW }, - { .name =3D "TLBIMVAA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim= vaa_write, - .type =3D ARM_CP_NO_RAW }, - { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, - .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, - .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint32_t mask =3D 0; - - /* In ARMv8 most bits of CPACR_EL1 are RES0. */ - if (!arm_feature(env, ARM_FEATURE_V8)) { - /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. - * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. - * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. - */ - if (arm_feature(env, ARM_FEATURE_VFP)) { - /* VFP coprocessor: cp10 & cp11 [23:20] */ - mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); - - if (!arm_feature(env, ARM_FEATURE_NEON)) { - /* ASEDIS [31] bit is RAO/WI */ - value |=3D (1 << 31); - } - - /* VFPv3 and upwards with NEON implement 32 double precision - * registers (D0-D31). - */ - if (!arm_feature(env, ARM_FEATURE_NEON) || - !arm_feature(env, ARM_FEATURE_VFP3)) { - /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ - value |=3D (1 << 30); - } - } - value &=3D mask; - } - env->cp15.cpacr_el1 =3D value; -} - -static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - if (arm_feature(env, ARM_FEATURE_V8)) { - /* Check if CPACR accesses are to be trapped to EL2 */ - if (arm_current_el(env) =3D=3D 1 && - (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { - return CP_ACCESS_TRAP_EL2; - /* Check if CPACR accesses are to be trapped to EL3 */ - } else if (arm_current_el(env) < 3 && - (env->cp15.cptr_el[3] & CPTR_TCPAC)) { - return CP_ACCESS_TRAP_EL3; - } - } - - return CP_ACCESS_OK; -} - -static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - /* Check if CPTR accesses are set to trap to EL3 */ - if (arm_current_el(env) =3D=3D 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC= )) { - return CP_ACCESS_TRAP_EL3; - } - - return CP_ACCESS_OK; -} - -static const ARMCPRegInfo v6_cp_reginfo[] =3D { - /* prefetch by MVA in v6, NOP in v7 */ - { .name =3D "MVA_prefetch", - .cp =3D 15, .crn =3D 7, .crm =3D 13, .opc1 =3D 0, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* We need to break the TB after ISB to execute self-modifying code - * correctly and also to take any pending interrupts immediately. - * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. - */ - { .name =3D "ISB", .cp =3D 15, .crn =3D 7, .crm =3D 5, .opc1 =3D 0, .o= pc2 =3D 4, - .access =3D PL0_W, .type =3D ARM_CP_NO_RAW, .writefn =3D arm_cp_writ= e_ignore }, - { .name =3D "DSB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 4, - .access =3D PL0_W, .type =3D ARM_CP_NOP }, - { .name =3D "DMB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 5, - .access =3D PL0_W, .type =3D ARM_CP_NOP }, - { .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 2, - .access =3D PL1_RW, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), - offsetof(CPUARMState, cp15.ifar_ns) }, - .resetvalue =3D 0, }, - /* Watchpoint Fault Address Register : should actually only be present - * for 1136, 1176, 11MPCore. - */ - { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, - { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, - .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), - .resetvalue =3D 0, .writefn =3D cpacr_write }, - REGINFO_SENTINEL -}; - -static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* Performance monitor registers user accessibility is controlled - * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable - * trapping to EL2 or EL3 for other accesses. - */ - int el =3D arm_current_el(env); - - if (el =3D=3D 0 && !env->cp15.c9_pmuserenr) { - return CP_ACCESS_TRAP; - } - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) - && !arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL3; - } - - return CP_ACCESS_OK; -} - -#ifndef CONFIG_USER_ONLY - -static inline bool arm_ccnt_enabled(CPUARMState *env) -{ - /* This does not support checking PMCCFILTR_EL0 register */ - - if (!(env->cp15.c9_pmcr & PMCRE)) { - return false; - } - - return true; -} - -void pmccntr_sync(CPUARMState *env) -{ - uint64_t temp_ticks; - - temp_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - temp_ticks /=3D 64; - } - - if (arm_ccnt_enabled(env)) { - env->cp15.c15_ccnt =3D temp_ticks - env->cp15.c15_ccnt; - } -} - -static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmccntr_sync(env); - - if (value & PMCRC) { - /* The counter has been reset */ - env->cp15.c15_ccnt =3D 0; - } - - /* only the DP, X, D and E bits are writable */ - env->cp15.c9_pmcr &=3D ~0x39; - env->cp15.c9_pmcr |=3D (value & 0x39); - - pmccntr_sync(env); -} - -static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, do not change value */ - return env->cp15.c15_ccnt; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - return total_ticks - env->cp15.c15_ccnt; -} - -static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and - * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the - * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are - * accessed. - */ - env->cp15.c9_pmselr =3D value & 0x1f; -} - -static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, set the absolute value */ - env->cp15.c15_ccnt =3D value; - return; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - env->cp15.c15_ccnt =3D total_ticks - value; -} - -static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint64_t cur_val =3D pmccntr_read(env, NULL); - - pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); -} - -#else /* CONFIG_USER_ONLY */ - -void pmccntr_sync(CPUARMState *env) -{ -} - -#endif - -static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmccntr_sync(env); - env->cp15.pmccfiltr_el0 =3D value & 0x7E000000; - pmccntr_sync(env); -} - -static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D (1 << 31); - env->cp15.c9_pmcnten |=3D value; -} - -static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D (1 << 31); - env->cp15.c9_pmcnten &=3D ~value; -} - -static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c9_pmovsr &=3D ~value; -} - -static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when - * PMSELR value is equal to or greater than the number of implemented - * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. - */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - pmccfiltr_write(env, ri, value); - } -} - -static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER - * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). - */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - return env->cp15.pmccfiltr_el0; - } else { - return 0; - } -} - -static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c9_pmuserenr =3D value & 1; -} - -static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* We have no event counters so only the C bit can be changed */ - value &=3D (1 << 31); - env->cp15.c9_pminten |=3D value; -} - -static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D (1 << 31); - env->cp15.c9_pminten &=3D ~value; -} - -static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Note that even though the AArch64 view of this register has bits - * [10:0] all RES0 we can only mask the bottom 5, to comply with the - * architectural requirements for bits which are RES0 only in some - * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 - * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP= .) - */ - raw_write(env, ri, value & ~0x1FULL); -} - -static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ - /* We only mask off bits that are RES0 both for AArch64 and AArch32. - * For bits that vary between AArch32/64, code needs to check the - * current execution mode before directly using the feature bit. - */ - uint32_t valid_mask =3D SCR_AARCH64_MASK | SCR_AARCH32_MASK; - - if (!arm_feature(env, ARM_FEATURE_EL2)) { - valid_mask &=3D ~SCR_HCE; - - /* On ARMv7, SMD (or SCD as it is called in v7) is only - * supported if EL2 exists. The bit is UNK/SBZP when - * EL2 is unavailable. In QEMU ARMv7, we force it to always zero - * when EL2 is unavailable. - * On ARMv8, this bit is always available. - */ - if (arm_feature(env, ARM_FEATURE_V7) && - !arm_feature(env, ARM_FEATURE_V8)) { - valid_mask &=3D ~SCR_SMD; - } - } - - /* Clear all-context RES0 bits. */ - value &=3D valid_mask; - raw_write(env, ri, value); -} - -static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - /* Acquire the CSSELR index from the bank corresponding to the CCSIDR - * bank - */ - uint32_t index =3D A32_BANKED_REG_GET(env, csselr, - ri->secure & ARM_CP_SECSTATE_S); - - return cpu->ccsidr[index]; -} - -static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - raw_write(env, ri, value & 0xf); -} - -static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - CPUState *cs =3D ENV_GET_CPU(env); - uint64_t ret =3D 0; - - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - ret |=3D CPSR_I; - } - if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { - ret |=3D CPSR_F; - } - /* External aborts are not possible in QEMU so A bit is always clear */ - return ret; -} - -static const ARMCPRegInfo v7_cp_reginfo[] =3D { - /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ - { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* Performance monitors are implementation defined in v7, - * but with an ARM recommended set of registers, which we - * follow (although we don't actually implement any counters) - * - * Performance registers fall into three categories: - * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) - * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) - * (c) UNDEF in PL0 if PMUSERENR.EN=3D=3D0, otherwise accessible (all= others) - * For the cases controlled by PMUSERENR we must set .access to PL0_RW - * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. - */ - { .name =3D "PMCNTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), - .writefn =3D pmcntenset_write, - .accessfn =3D pmreg_access, - .raw_writefn =3D raw_write }, - { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, - .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, - { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), - .accessfn =3D pmreg_access, - .writefn =3D pmcntenclr_write, - .type =3D ARM_CP_ALIAS }, - { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), - .writefn =3D pmcntenclr_write }, - { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, - .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_p= movsr), - .accessfn =3D pmreg_access, - .writefn =3D pmovsr_write, - .raw_writefn =3D raw_write }, - { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), - .writefn =3D pmovsr_write, - .raw_writefn =3D raw_write }, - /* Unimplemented so WI. */ - { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access, .type =3D ARM_CP_NOP = }, -#ifndef CONFIG_USER_ONLY - { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, - .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), - .accessfn =3D pmreg_access, .writefn =3D pmselr_write, - .raw_writefn =3D raw_write}, - { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), - .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, - { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, - .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_IO, - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, - .accessfn =3D pmreg_access }, - { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_IO, - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, -#endif - { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, - .writefn =3D pmccfiltr_write, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), - .resetvalue =3D 0, }, - { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, - .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, - .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - /* Unimplemented, RAZ/WI. */ - { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, - .accessfn =3D pmreg_access }, - { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), - .resetvalue =3D 0, - .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, - { .name =3D "PMUSERENR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 0, - .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_= CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), - .resetvalue =3D 0, - .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, - { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), - .resetvalue =3D 0, - .writefn =3D pmintenset_write, .raw_writefn =3D raw_write }, - { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, - .resetvalue =3D 0x0 }, - { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write, }, - { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write }, - { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, - .access =3D PL1_R, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW = }, - { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D csselr_write, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), - offsetof(CPUARMState, cp15.csselr_ns) } }, - /* Auxiliary ID register: this actually has an IMPDEF value but for now - * just RAZ for all cores: - */ - { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* Auxiliary fault status registers: these also are IMPDEF, and we - * choose to RAZ/WI for all cores. - */ - { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* MAIR can just read-as-written because we don't implement caches - * and so don't need to care about memory attributes. - */ - { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[1]), - .resetvalue =3D 0 }, - { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[3]), - .resetvalue =3D 0 }, - /* For non-long-descriptor page tables these are PRRR and NMRR; - * regardless they still act as reads-as-written for QEMU. - */ - /* MAIR0/1 are defined separately from their 64-bit counterpart which - * allows them to assign the correct fieldoffset based on the endiann= ess - * handled in the field definitions. - */ - { .name =3D "MAIR0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .acce= ss =3D PL1_RW, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair0_s), - offsetof(CPUARMState, cp15.mair0_ns) }, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "MAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .acce= ss =3D PL1_RW, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair1_s), - offsetof(CPUARMState, cp15.mair1_ns) }, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "ISR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, - /* 32 bit ITLB invalidates */ - { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, - { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, - { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 5, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, - /* 32 bit DTLB invalidates */ - { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, - { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, - { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 6, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, - /* 32 bit TLB invalidates */ - { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, - { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, - { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, - { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { - /* 32 bit TLB invalidates, Inner Shareable */ - { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_is_= write }, - { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, - { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, - .writefn =3D tlbiasid_is_write }, - { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, - .writefn =3D tlbimvaa_is_write }, - REGINFO_SENTINEL -}; - -static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D 1; - env->teecr =3D value; -} - -static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *= ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 0 && (env->teecr & 1)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -static const ARMCPRegInfo t2ee_cp_reginfo[] =3D { - { .name =3D "TEECR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 6, = .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, teecr), - .resetvalue =3D 0, - .writefn =3D teecr_write }, - { .name =3D "TEEHBR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 6,= .opc2 =3D 0, - .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, teehbr), - .accessfn =3D teehbr_access, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo v6k_cp_reginfo[] =3D { - { .name =3D "TPIDR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 2, .crn =3D 13, .crm =3D 0, - .access =3D PL0_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalu= e =3D 0 }, - { .name =3D "TPIDRURW", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 2, - .access =3D PL0_RW, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrurw_s), - offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = }, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, - .access =3D PL0_R|PL1_W, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el[0]), - .resetvalue =3D 0}, - { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, - .access =3D PL0_R|PL1_W, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), - offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D 13, .crm =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalu= e =3D 0 }, - { .name =3D "TPIDRPRW", .opc1 =3D 0, .cp =3D 15, .crn =3D 13, .crm =3D= 0, .opc2 =3D 4, - .access =3D PL1_RW, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrprw_s), - offsetoflow32(CPUARMState, cp15.tpidrprw_ns) = }, - .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -#ifndef CONFIG_USER_ONLY - -static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. - * Writable only at the highest implemented exception level. - */ - int el =3D arm_current_el(env); - - switch (el) { - case 0: - if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { - return CP_ACCESS_TRAP; - } - break; - case 1: - if (!isread && ri->state =3D=3D ARM_CP_STATE_AA32 && - arm_is_secure_below_el3(env)) { - /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) = */ - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - break; - case 2: - case 3: - break; - } - - if (!isread && el < arm_highest_el(env)) { - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - - return CP_ACCESS_OK; -} - -static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, - bool isread) -{ - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); - - /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ - if (cur_el =3D=3D 0 && - !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { - return CP_ACCESS_TRAP; - } - - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 && - !extract32(env->cp15.cnthctl_el2, 0, 1)) { - return CP_ACCESS_TRAP_EL2; - } - return CP_ACCESS_OK; -} - -static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, - bool isread) -{ - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); - - /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if - * EL0[PV]TEN is zero. - */ - if (cur_el =3D=3D 0 && - !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { - return CP_ACCESS_TRAP; - } - - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 && - !extract32(env->cp15.cnthctl_el2, 1, 1)) { - return CP_ACCESS_TRAP_EL2; - } - return CP_ACCESS_OK; -} - -static CPAccessResult gt_pct_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - return gt_counter_access(env, GTIMER_PHYS, isread); -} - -static CPAccessResult gt_vct_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - return gt_counter_access(env, GTIMER_VIRT, isread); -} - -static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - return gt_timer_access(env, GTIMER_PHYS, isread); -} - -static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - return gt_timer_access(env, GTIMER_VIRT, isread); -} - -static CPAccessResult gt_stimer_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* The AArch64 register view of the secure physical timer is - * always accessible from EL3, and configurably accessible from - * Secure EL1. - */ - switch (arm_current_el(env)) { - case 1: - if (!arm_is_secure(env)) { - return CP_ACCESS_TRAP; - } - if (!(env->cp15.scr_el3 & SCR_ST)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; - case 0: - case 2: - return CP_ACCESS_TRAP; - case 3: - return CP_ACCESS_OK; - default: - g_assert_not_reached(); - } -} - -static uint64_t gt_get_countervalue(CPUARMState *env) -{ - return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; -} - -static void gt_recalc_timer(ARMCPU *cpu, int timeridx) -{ - ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; - - if (gt->ctl & 1) { - /* Timer enabled: calculate and set current ISTATUS, irq, and - * reset timer to when ISTATUS next has to change - */ - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? - cpu->env.cp15.cntvoff_el2 : 0; - uint64_t count =3D gt_get_countervalue(&cpu->env); - /* Note that this must be unsigned 64 bit arithmetic: */ - int istatus =3D count - offset >=3D gt->cval; - uint64_t nexttick; - int irqstate; - - gt->ctl =3D deposit32(gt->ctl, 2, 1, istatus); - - irqstate =3D (istatus && !(gt->ctl & 2)); - qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); - - if (istatus) { - /* Next transition is when count rolls back over to zero */ - nexttick =3D UINT64_MAX; - } else { - /* Next transition is when we hit cval */ - nexttick =3D gt->cval + offset; - } - /* Note that the desired next expiry time might be beyond the - * signed-64-bit range of a QEMUTimer -- in this case we just - * set the timer for as far in the future as possible. When the - * timer expires we will reset the timer for any remaining period. - */ - if (nexttick > INT64_MAX / GTIMER_SCALE) { - nexttick =3D INT64_MAX / GTIMER_SCALE; - } - timer_mod(cpu->gt_timer[timeridx], nexttick); - trace_arm_gt_recalc(timeridx, irqstate, nexttick); - } else { - /* Timer disabled: ISTATUS and timer output always clear */ - gt->ctl &=3D ~4; - qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); - timer_del(cpu->gt_timer[timeridx]); - trace_arm_gt_recalc_disabled(timeridx); - } -} - -static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - timer_del(cpu->gt_timer[timeridx]); -} - -static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_get_countervalue(env); -} - -static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_get_countervalue(env) - env->cp15.cntvoff_el2; -} - -static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx, - uint64_t value) -{ - trace_arm_gt_cval_write(timeridx, value); - env->cp15.c14_timer[timeridx].cval =3D value; - gt_recalc_timer(arm_env_get_cpu(env), timeridx); -} - -static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx) -{ - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; - - return (uint32_t)(env->cp15.c14_timer[timeridx].cval - - (gt_get_countervalue(env) - offset)); -} - -static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx, - uint64_t value) -{ - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; - - trace_arm_gt_tval_write(timeridx, value); - env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + - sextract64(value, 0, 32); - gt_recalc_timer(arm_env_get_cpu(env), timeridx); -} - -static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - uint32_t oldval =3D env->cp15.c14_timer[timeridx].ctl; - - trace_arm_gt_ctl_write(timeridx, value); - env->cp15.c14_timer[timeridx].ctl =3D deposit64(oldval, 0, 2, value); - if ((oldval ^ value) & 1) { - /* Enable toggled */ - gt_recalc_timer(cpu, timeridx); - } else if ((oldval ^ value) & 2) { - /* IMASK toggled: don't need to recalculate, - * just set the interrupt line based on ISTATUS - */ - int irqstate =3D (oldval & 4) && !(value & 2); - - trace_arm_gt_imask_toggle(timeridx, irqstate); - qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); - } -} - -static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_PHYS); -} - -static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_PHYS, value); -} - -static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_PHYS); -} - -static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_PHYS, value); -} - -static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_PHYS, value); -} - -static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_VIRT); -} - -static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_VIRT, value); -} - -static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_VIRT); -} - -static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_VIRT, value); -} - -static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_VIRT, value); -} - -static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - trace_arm_gt_cntvoff_write(value); - raw_write(env, ri, value); - gt_recalc_timer(cpu, GTIMER_VIRT); -} - -static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_HYP); -} - -static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_HYP, value); -} - -static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_HYP); -} - -static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_HYP, value); -} - -static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_HYP, value); -} - -static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_SEC); -} - -static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_SEC, value); -} - -static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_SEC); -} - -static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_SEC, value); -} - -static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_SEC, value); -} - -void arm_gt_ptimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_PHYS); -} - -void arm_gt_vtimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_VIRT); -} - -void arm_gt_htimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_HYP); -} - -void arm_gt_stimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_SEC); -} - -static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { - /* Note that CNTFRQ is purely reads-as-written for the benefit - * of software; writing it doesn't actually change the timer frequency. - * Our reset value matches the fixed frequency we implement the timer = at. - */ - { .name =3D "CNTFRQ", .cp =3D 15, .crn =3D 14, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .type =3D ARM_CP_ALIAS, - .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_cntfrq), - }, - { .name =3D "CNTFRQ_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntfrq), - .resetvalue =3D (1000 * 1000 * 1000) / GTIMER_SCALE, - }, - /* overall control: mostly access permissions */ - { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), - .resetvalue =3D 0, - }, - /* per-timer control */ - { .name =3D "CNTP_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D= 0, .opc2 =3D 1, - .secure =3D ARM_CP_SECSTATE_NS, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_ptimer_access, - .fieldoffset =3D offsetoflow32(CPUARMState, - cp15.c14_timer[GTIMER_PHYS].ctl), - .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTP_CTL(S)", - .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, - .secure =3D ARM_CP_SECSTATE_S, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_ptimer_access, - .fieldoffset =3D offsetoflow32(CPUARMState, - cp15.c14_timer[GTIMER_SEC].ctl), - .writefn =3D gt_sec_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTP_CTL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_ptimer_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), - .resetvalue =3D 0, - .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D= 0, .opc2 =3D 1, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_vtimer_access, - .fieldoffset =3D offsetoflow32(CPUARMState, - cp15.c14_timer[GTIMER_VIRT].ctl), - .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_vtimer_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), - .resetvalue =3D 0, - .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, - }, - /* TimerValue views: a 32 bit downcounting view of the underlying stat= e */ - { .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 = =3D 0, .opc2 =3D 0, - .secure =3D ARM_CP_SECSTATE_NS, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_ptimer_access, - .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, - }, - { .name =3D "CNTP_TVAL(S)", - .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, - .secure =3D ARM_CP_SECSTATE_S, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_ptimer_access, - .readfn =3D gt_sec_tval_read, .writefn =3D gt_sec_tval_write, - }, - { .name =3D "CNTP_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset, - .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, - }, - { .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 = =3D 0, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_vtimer_access, - .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, - }, - { .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, - .accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset, - .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, - }, - /* The counter itself */ - { .name =3D "CNTPCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, - .accessfn =3D gt_pct_access, - .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore, - }, - { .name =3D "CNTPCT_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 1, - .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D gt_pct_access, .readfn =3D gt_cnt_read, - }, - { .name =3D "CNTVCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 1, - .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, - .accessfn =3D gt_vct_access, - .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore, - }, - { .name =3D "CNTVCT_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 2, - .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D gt_vct_access, .readfn =3D gt_virt_cnt_read, - }, - /* Comparison value, indicating when the timer goes off */ - { .name =3D "CNTP_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, - .secure =3D ARM_CP_SECSTATE_NS, - .access =3D PL1_RW | PL0_R, - .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), - .accessfn =3D gt_ptimer_access, - .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTP_CVAL(S)", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, - .secure =3D ARM_CP_SECSTATE_S, - .access =3D PL1_RW | PL0_R, - .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), - .accessfn =3D gt_ptimer_access, - .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTP_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW | PL0_R, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), - .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, - .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3, - .access =3D PL1_RW | PL0_R, - .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), - .accessfn =3D gt_vtimer_access, - .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_RW | PL0_R, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), - .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, - .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, - }, - /* Secure timer -- this is actually restricted to only EL3 - * and configurably Secure-EL1 via the accessfn. - */ - { .name =3D "CNTPS_TVAL_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW, - .accessfn =3D gt_stimer_access, - .readfn =3D gt_sec_tval_read, - .writefn =3D gt_sec_tval_write, - .resetfn =3D gt_sec_timer_reset, - }, - { .name =3D "CNTPS_CTL_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL1_RW, - .accessfn =3D gt_stimer_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ct= l), - .resetvalue =3D 0, - .writefn =3D gt_sec_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTPS_CVAL_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .type =3D ARM_CP_IO, .access =3D PL1_RW, - .accessfn =3D gt_stimer_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), - .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, - }, - REGINFO_SENTINEL -}; - -#else -/* In user-mode none of the generic timer registers are accessible, - * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio ou= tputs, - * so instead just don't register any of them. - */ -static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { - REGINFO_SENTINEL -}; - -#endif - -static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ - if (arm_feature(env, ARM_FEATURE_LPAE)) { - raw_write(env, ri, value); - } else if (arm_feature(env, ARM_FEATURE_V7)) { - raw_write(env, ri, value & 0xfffff6ff); - } else { - raw_write(env, ri, value & 0xfffff1ff); - } -} - -#ifndef CONFIG_USER_ONLY -/* get_phys_addr() isn't present for user-mode-only targets */ - -static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (ri->opc2 & 4) { - /* The ATS12NSO* operations must trap to EL3 if executed in - * Secure EL1 (which can only happen if EL3 is AArch64). - * They are simply UNDEF if executed from NS EL1. - * They function normally from EL2 or EL3. - */ - if (arm_current_el(env) =3D=3D 1) { - if (arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; - } - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - } - return CP_ACCESS_OK; -} - -static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - int access_type, ARMMMUIdx mmu_idx) -{ - hwaddr phys_addr; - target_ulong page_size; - int prot; - uint32_t fsr; - bool ret; - uint64_t par64; - MemTxAttrs attrs =3D {}; - ARMMMUFaultInfo fi =3D {}; - - ret =3D get_phys_addr(env, value, access_type, mmu_idx, - &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); - if (extended_addresses_enabled(env)) { - /* fsr is a DFSR/IFSR value for the long descriptor - * translation table format, but with WnR always clear. - * Convert it to a 64-bit PAR. - */ - par64 =3D (1 << 11); /* LPAE bit always set */ - if (!ret) { - par64 |=3D phys_addr & ~0xfffULL; - if (!attrs.secure) { - par64 |=3D (1 << 9); /* NS */ - } - /* We don't set the ATTR or SH fields in the PAR. */ - } else { - par64 |=3D 1; /* F */ - par64 |=3D (fsr & 0x3f) << 1; /* FS */ - /* Note that S2WLK and FSTAGE are always zero, because we don't - * implement virtualization and therefore there can't be a sta= ge 2 - * fault. - */ - } - } else { - /* fsr is a DFSR/IFSR value for the short descriptor - * translation table format (with WnR always clear). - * Convert it to a 32-bit PAR. - */ - if (!ret) { - /* We do not set any attribute bits in the PAR */ - if (page_size =3D=3D (1 << 24) - && arm_feature(env, ARM_FEATURE_V7)) { - par64 =3D (phys_addr & 0xff000000) | (1 << 1); - } else { - par64 =3D phys_addr & 0xfffff000; - } - if (!attrs.secure) { - par64 |=3D (1 << 9); /* NS */ - } - } else { - par64 =3D ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | - ((fsr & 0xf) << 1) | 1; - } - } - return par64; -} - -static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ - int access_type =3D ri->opc2 & 1; - uint64_t par64; - ARMMMUIdx mmu_idx; - int el =3D arm_current_el(env); - bool secure =3D arm_is_secure_below_el3(env); - - switch (ri->opc2 & 6) { - case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ - switch (el) { - case 3: - mmu_idx =3D ARMMMUIdx_S1E3; - break; - case 2: - mmu_idx =3D ARMMMUIdx_S1NSE1; - break; - case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; - break; - default: - g_assert_not_reached(); - } - break; - case 2: - /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ - switch (el) { - case 3: - mmu_idx =3D ARMMMUIdx_S1SE0; - break; - case 2: - mmu_idx =3D ARMMMUIdx_S1NSE0; - break; - case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; - break; - default: - g_assert_not_reached(); - } - break; - case 4: - /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ - mmu_idx =3D ARMMMUIdx_S12NSE1; - break; - case 6: - /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ - mmu_idx =3D ARMMMUIdx_S12NSE0; - break; - default: - g_assert_not_reached(); - } - - par64 =3D do_ats_write(env, value, access_type, mmu_idx); - - A32_BANKED_CURRENT_REG_SET(env, par, par64); -} - -static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - int access_type =3D ri->opc2 & 1; - uint64_t par64; - - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); - - A32_BANKED_CURRENT_REG_SET(env, par, par64); -} - -static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 3 && !(env->cp15.scr_el3 & SCR_NS)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - int access_type =3D ri->opc2 & 1; - ARMMMUIdx mmu_idx; - int secure =3D arm_is_secure_below_el3(env); - - switch (ri->opc2 & 6) { - case 0: - switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; - break; - case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_S1E2; - break; - case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_S1E3; - break; - default: - g_assert_not_reached(); - } - break; - case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; - break; - case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; - break; - case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; - break; - default: - g_assert_not_reached(); - } - - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); -} -#endif - -static const ARMCPRegInfo vapa_cp_reginfo[] =3D { - { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 =3D 0, .o= pc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.par_s), - offsetoflow32(CPUARMState, cp15.par_ns) }, - .writefn =3D par_write }, -#ifndef CONFIG_USER_ONLY - /* This underdecoding is safe because the reginfo is NO_RAW. */ - { .name =3D "ATS", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0, .o= pc2 =3D CP_ANY, - .access =3D PL1_W, .accessfn =3D ats_access, - .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW }, -#endif - REGINFO_SENTINEL -}; - -/* Return basic MPU access permission bits. */ -static uint32_t simple_mpu_ap_bits(uint32_t val) -{ - uint32_t ret; - uint32_t mask; - int i; - ret =3D 0; - mask =3D 3; - for (i =3D 0; i < 16; i +=3D 2) { - ret |=3D (val >> i) & mask; - mask <<=3D 2; - } - return ret; -} - -/* Pad basic MPU access permission bits to extended format. */ -static uint32_t extended_mpu_ap_bits(uint32_t val) -{ - uint32_t ret; - uint32_t mask; - int i; - ret =3D 0; - mask =3D 3; - for (i =3D 0; i < 16; i +=3D 2) { - ret |=3D (val & mask) << i; - mask <<=3D 2; - } - return ret; -} - -static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.pmsav5_data_ap =3D extended_mpu_ap_bits(value); -} - -static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); -} - -static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.pmsav5_insn_ap =3D extended_mpu_ap_bits(value); -} - -static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); -} - -static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return 0; - } - - u32p +=3D env->cp15.c6_rgnr; - return *u32p; -} - -static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return; - } - - u32p +=3D env->cp15.c6_rgnr; - tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ - *u32p =3D value; -} - -static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return; - } - - memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); -} - -static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - uint32_t nrgs =3D cpu->pmsav7_dregion; - - if (value >=3D nrgs) { - qemu_log_mask(LOG_GUEST_ERROR, - "PMSAv7 RGNR write >=3D # supported regions, %" PRIu= 32 - " > %" PRIu32 "\n", (uint32_t)value, nrgs); - return; - } - - raw_write(env, ri, value); -} - -static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { - { .name =3D "DRBAR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, - .fieldoffset =3D offsetof(CPUARMState, pmsav7.drbar), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, - { .name =3D "DRSR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, .= opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, - .fieldoffset =3D offsetof(CPUARMState, pmsav7.drsr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, - { .name =3D "DRACR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 4, - .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, - .fieldoffset =3D offsetof(CPUARMState, pmsav7.dracr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, - { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_rgnr), - .writefn =3D pmsav7_rgnr_write }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { - { .name =3D "DATA_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_data_ap), - .readfn =3D pmsav5_data_ap_read, .writefn =3D pmsav5_data_ap_write, = }, - { .name =3D "INSN_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_insn_ap), - .readfn =3D pmsav5_insn_ap_read, .writefn =3D pmsav5_insn_ap_write, = }, - { .name =3D "DATA_EXT_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_data_ap), - .resetvalue =3D 0, }, - { .name =3D "INSN_EXT_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_insn_ap), - .resetvalue =3D 0, }, - { .name =3D "DCACHE_CFG", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c2_data), .resetvalue = =3D 0, }, - { .name =3D "ICACHE_CFG", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c2_insn), .resetvalue = =3D 0, }, - /* Protection region base and size registers */ - { .name =3D "946_PRBS0", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[0]) }, - { .name =3D "946_PRBS1", .cp =3D 15, .crn =3D 6, .crm =3D 1, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[1]) }, - { .name =3D "946_PRBS2", .cp =3D 15, .crn =3D 6, .crm =3D 2, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[2]) }, - { .name =3D "946_PRBS3", .cp =3D 15, .crn =3D 6, .crm =3D 3, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[3]) }, - { .name =3D "946_PRBS4", .cp =3D 15, .crn =3D 6, .crm =3D 4, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[4]) }, - { .name =3D "946_PRBS5", .cp =3D 15, .crn =3D 6, .crm =3D 5, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[5]) }, - { .name =3D "946_PRBS6", .cp =3D 15, .crn =3D 6, .crm =3D 6, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[6]) }, - { .name =3D "946_PRBS7", .cp =3D 15, .crn =3D 6, .crm =3D 7, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, - REGINFO_SENTINEL -}; - -static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - TCR *tcr =3D raw_ptr(env, ri); - int maskshift =3D extract32(value, 0, 3); - - if (!arm_feature(env, ARM_FEATURE_V8)) { - if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { - /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when - * using Long-desciptor translation table format */ - value &=3D ~((7 << 19) | (3 << 14) | (0xf << 3)); - } else if (arm_feature(env, ARM_FEATURE_EL3)) { - /* In an implementation that includes the Security Extensions - * TTBCR has additional fields PD0 [4] and PD1 [5] for - * Short-descriptor translation table format. - */ - value &=3D TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; - } else { - value &=3D TTBCR_N; - } - } - - /* Update the masks corresponding to the TCR bank being written - * Note that we always calculate mask and base_mask, but - * they are only used for short-descriptor tables (ie if EAE is 0); - * for long-descriptor tables the TCR fields are used differently - * and the mask and base_mask values are meaningless. - */ - tcr->raw_tcr =3D value; - tcr->mask =3D ~(((uint32_t)0xffffffffu) >> maskshift); - tcr->base_mask =3D ~((uint32_t)0x3fffu >> maskshift); -} - -static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* With LPAE the TTBCR could result in a change of ASID - * via the TTBCR.A1 bit, so do a TLB flush. - */ - tlb_flush(CPU(cpu)); - } - vmsa_ttbcr_raw_write(env, ri, value); -} - -static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - TCR *tcr =3D raw_ptr(env, ri); - - /* Reset both the TCR as well as the masks corresponding to the bank of - * the TCR being reset. - */ - tcr->raw_tcr =3D 0; - tcr->mask =3D 0; - tcr->base_mask =3D 0xffffc000u; -} - -static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - TCR *tcr =3D raw_ptr(env, ri); - - /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ - tlb_flush(CPU(cpu)); - tcr->raw_tcr =3D value; -} - -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* 64 bit accesses to the TTBRs can change the ASID and so we - * must flush the TLB. - */ - if (cpreg_field_is_64bit(ri)) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - - tlb_flush(CPU(cpu)); - } - raw_write(env, ri, value); -} - -static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - - /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ - if (raw_read(env, ri) !=3D value) { - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, - ARMMMUIdx_S2NS, -1); - raw_write(env, ri, value); - } -} - -static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { - { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dfsr_s), - offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, - { .name =3D "IFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, - .access =3D PL1_RW, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.ifsr_s), - offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, - { .name =3D "DFAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.dfar_s), - offsetof(CPUARMState, cp15.dfar_ns) } }, - { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[1]), - .resetvalue =3D 0, }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { - { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, - { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), - offsetof(CPUARMState, cp15.ttbr0_ns) } }, - { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), - offsetof(CPUARMState, cp15.ttbr1_ns) } }, - { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .writefn =3D vmsa_tcr_el1_write, - .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, - { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_= write, - .raw_writefn =3D vmsa_ttbcr_raw_write, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tcr_el[3]), - offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, - REGINFO_SENTINEL -}; - -static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_ticonfig =3D value & 0xe7; - /* The OS_TYPE bit in this register changes the reported CPUID! */ - env->cp15.c0_cpuid =3D (value & (1 << 5)) ? - ARM_CPUID_TI915T : ARM_CPUID_TI925T; -} - -static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_threadid =3D value & 0xffff; -} - -static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Wait-for-interrupt (deprecated) */ - cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); -} - -static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* On OMAP there are registers indicating the max/min index of dcache = lines - * containing a dirty line; cache flush operations have to reset these. - */ - env->cp15.c15_i_max =3D 0x000; - env->cp15.c15_i_min =3D 0xff0; -} - -static const ARMCPRegInfo omap_cp_reginfo[] =3D { - { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_OVERRIDE, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_el[1]), - .resetvalue =3D 0, }, - { .name =3D "", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 0, .opc= 2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - { .name =3D "TICONFIG", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ticonfig), .resetval= ue =3D 0, - .writefn =3D omap_ticonfig_write }, - { .name =3D "IMAX", .cp =3D 15, .crn =3D 15, .crm =3D 2, .opc1 =3D 0, = .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = =3D 0, }, - { .name =3D "IMIN", .cp =3D 15, .crn =3D 15, .crm =3D 3, .opc1 =3D 0, = .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0xff0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_min) }, - { .name =3D "THREADID", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_threadid), .resetval= ue =3D 0, - .writefn =3D omap_threadid_write }, - { .name =3D "TI925T_STATUS", .cp =3D 15, .crn =3D 15, - .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, - .type =3D ARM_CP_NO_RAW, - .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, - /* TODO: Peripheral port remap register: - * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller - * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), - * when MMU is off. - */ - { .name =3D "OMAP_CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, - .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, - .type =3D ARM_CP_OVERRIDE | ARM_CP_NO_RAW, - .writefn =3D omap_cachemaint_write }, - { .name =3D "C9", .cp =3D 15, .crn =3D 9, - .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, - .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_cpar =3D value & 0x3fff; -} - -static const ARMCPRegInfo xscale_cp_reginfo[] =3D { - { .name =3D "XSCALE_CPAR", - .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D 0, .opc2 =3D 0, .acce= ss =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = =3D 0, - .writefn =3D xscale_cpar_write, }, - { .name =3D "XSCALE_AUXCR", - .cp =3D 15, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, .acces= s =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c1_xscaleauxcr), - .resetvalue =3D 0, }, - /* XScale specific cache-lockdown: since we have no cache we NOP these - * and hope the guest does not really rely on cache behaviour. - */ - { .name =3D "XSCALE_LOCK_ICACHE_LINE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_UNLOCK_ICACHE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_DCACHE_LOCK", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_UNLOCK_DCACHE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { - /* RAZ/WI the whole crn=3D15 space, when we don't have a more specific - * implementation of this implementation-defined space. - * Ideally this should eventually disappear in favour of actually - * implementing the correct behaviour for all cores. - */ - { .name =3D "C15_IMPDEF", .cp =3D 15, .crn =3D 15, - .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, - .access =3D PL1_RW, - .type =3D ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, - .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] =3D { - /* Cache status: RAZ because we have no cache so it's always clean */ - { .name =3D "CDSR", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, = .opc2 =3D 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo cache_block_ops_cp_reginfo[] =3D { - /* We never have a a block transfer operation in progress */ - { .name =3D "BXSR", .cp =3D 15, .crn =3D 7, .crm =3D 12, .opc1 =3D 0, = .opc2 =3D 4, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D 0 }, - /* The cache ops themselves: these all NOP for QEMU */ - { .name =3D "IICR", .cp =3D 15, .crm =3D 5, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "IDCR", .cp =3D 15, .crm =3D 6, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "CDCR", .cp =3D 15, .crm =3D 12, .opc1 =3D 0, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "PIR", .cp =3D 15, .crm =3D 12, .opc1 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "PDR", .cp =3D 15, .crm =3D 12, .opc1 =3D 2, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { - /* The cache test-and-clean instructions always return (1 << 30) - * to indicate that there are no dirty cache lines. - */ - { .name =3D "TC_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 = =3D 0, .opc2 =3D 3, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D (1 << 30) }, - { .name =3D "TCI_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 3, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D (1 << 30) }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { - /* Ignore ReadBuffer accesses */ - { .name =3D "C9_READBUFFER", .cp =3D 15, .crn =3D 9, - .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, - .access =3D PL1_RW, .resetvalue =3D 0, - .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, - REGINFO_SENTINEL -}; - -static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); - - if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el =3D= =3D 1) { - return env->cp15.vpidr_el2; - } - return raw_read(env, ri); -} - -static uint64_t mpidr_read_val(CPUARMState *env) -{ - ARMCPU *cpu =3D ARM_CPU(arm_env_get_cpu(env)); - uint64_t mpidr =3D cpu->mp_affinity; - - if (arm_feature(env, ARM_FEATURE_V7MP)) { - mpidr |=3D (1U << 31); - /* Cores which are uniprocessor (non-coherent) - * but still implement the MP extensions set - * bit 30. (For instance, Cortex-R5). - */ - if (cpu->mp_is_up) { - mpidr |=3D (1u << 30); - } - } - return mpidr; -} - -static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); - - if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el =3D=3D 1) { - return env->cp15.vmpidr_el2; - } - return mpidr_read_val(env); -} - -static const ARMCPRegInfo mpidr_cp_reginfo[] =3D { - { .name =3D "MPIDR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 5, - .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo lpae_cp_reginfo[] =3D { - /* NOP AMAIR0/1 */ - { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ - { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "PAR", .cp =3D 15, .crm =3D 7, .opc1 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), - offsetof(CPUARMState, cp15.par_ns)} }, - { .name =3D "TTBR0", .cp =3D 15, .crm =3D 2, .opc1 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), - offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, - { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), - offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, - REGINFO_SENTINEL -}; - -static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return vfp_get_fpcr(env); -} - -static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - vfp_set_fpcr(env, value); -} - -static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return vfp_get_fpsr(env); -} - -static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - vfp_set_fpsr(env, value); -} - -static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->daif =3D value & PSTATE_DAIF; -} - -static CPAccessResult aa64_cacheop_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless - * SCTLR_EL1.UCI is set. - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= I)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions - * Page D4-1736 (DDI0487A.b) - */ - -static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); - } else { - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1); - } -} - -static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, - uint64_t value) -{ - bool sec =3D arm_is_secure_below_el3(env); - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - if (sec) { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0= , -1); - } else { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, - ARMMMUIdx_S12NSE0, -1); - } - } -} - -static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); - } else { - if (arm_feature(env, ARM_FEATURE_EL2)) { - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, - ARMMMUIdx_S2NS, -1); - } else { - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, = -1); - } - } -} - -static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); -} - -static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - - tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1); -} - -static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ - bool sec =3D arm_is_secure_below_el3(env); - bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - if (sec) { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0= , -1); - } else if (has_el2) { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, - ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); - } else { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, - ARMMMUIdx_S12NSE0, -1); - } - } -} - -static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); - } -} - -static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1); - } -} - -static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate by VA, EL1&0 (AArch64 version). - * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, - * since we don't support flush-for-specific-ASID-only or - * flush-last-level-only. - */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - - if (arm_is_secure_below_el3(env)) { - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1, - ARMMMUIdx_S1SE0, -1); - } else { - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1, - ARMMMUIdx_S12NSE0, -1); - } -} - -static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate by VA, EL2 - * Currently handles both VAE2 and VALE2, since we don't support - * flush-last-level-only. - */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); -} - -static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate by VA, EL3 - * Currently handles both VAE3 and VALE3, since we don't support - * flush-last-level-only. - */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1); -} - -static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, - uint64_t value) -{ - bool sec =3D arm_is_secure_below_el3(env); - CPUState *other_cs; - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - - CPU_FOREACH(other_cs) { - if (sec) { - tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1, - ARMMMUIdx_S1SE0, -1); - } else { - tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1, - ARMMMUIdx_S12NSE0, -1); - } - } -} - -static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, - uint64_t value) -{ - CPUState *other_cs; - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - - CPU_FOREACH(other_cs) { - tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); - } -} - -static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, - uint64_t value) -{ - CPUState *other_cs; - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - - CPU_FOREACH(other_cs) { - tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1); - } -} - -static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - /* Invalidate by IPA. This has to invalidate any structures that - * contain only stage 2 translation information, but does not need - * to apply to structures that contain combined stage 1 and stage 2 - * translation information. - * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. - */ - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - uint64_t pageaddr; - - if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { - return; - } - - pageaddr =3D sextract64(value << 12, 0, 48); - - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); -} - -static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, - uint64_t value) -{ - CPUState *other_cs; - uint64_t pageaddr; - - if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { - return; - } - - pageaddr =3D sextract64(value << 12, 0, 48); - - CPU_FOREACH(other_cs) { - tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); - } -} - -static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, - bool isread) -{ - /* We don't implement EL2, so the only control on DC ZVA is the - * bit in the SCTLR which can prohibit access for EL0. - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZ= E)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - int dzp_bit =3D 1 << 4; - - /* DZP indicates whether DC ZVA access is allowed */ - if (aa64_zva_access(env, NULL, false) =3D=3D CP_ACCESS_OK) { - dzp_bit =3D 0; - } - return cpu->dcz_blocksize | dzp_bit; -} - -static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *= ri, - bool isread) -{ - if (!(env->pstate & PSTATE_SP)) { - /* Access to SP_EL0 is undefined if it's being used as - * the stack pointer. - */ - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - return CP_ACCESS_OK; -} - -static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return env->pstate & PSTATE_SP; -} - -static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t= val) -{ - update_spsel(env, val); -} - -static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - - if (raw_read(env, ri) =3D=3D value) { - /* Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - - raw_write(env, ri, value); - /* ??? Lots of these bits are not implemented. */ - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); -} - -static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) =3D=3D 2)= { - return CP_ACCESS_TRAP_FP_EL2; - } - if (env->cp15.cptr_el[3] & CPTR_TFP) { - return CP_ACCESS_TRAP_FP_EL3; - } - return CP_ACCESS_OK; -} - -static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.mdcr_el3 =3D value & SDCR_VALID_MASK; -} - -static const ARMCPRegInfo v8_cp_reginfo[] =3D { - /* Minimal set of EL0-visible registers. This will need to be expanded - * significantly for system emulation of AArch64 CPUs. - */ - { .name =3D "NZCV", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_NZCV }, - { .name =3D "DAIF", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 2, - .type =3D ARM_CP_NO_RAW, - .access =3D PL0_RW, .accessfn =3D aa64_daif_access, - .fieldoffset =3D offsetof(CPUARMState, daif), - .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fp= cr_write }, - { .name =3D "FPSR", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fp= sr_write }, - { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, - .readfn =3D aa64_dczid_read }, - { .name =3D "DC_ZVA", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_DC_ZVA, -#ifndef CONFIG_USER_ONLY - /* Avoid overhead of an access check that always passes in user-mode= */ - .accessfn =3D aa64_zva_access, -#endif - }, - { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 4, .crm =3D 2, - .access =3D PL1_R, .type =3D ARM_CP_CURRENTEL }, - /* Cache ops: all NOPs since we don't emulate caches */ - { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, - { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, - { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, - { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, - { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* TLBI operations */ - { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vmalle1_write }, - { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vmalle1_write }, - { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1is_write }, - { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1is_write }, - { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1_write }, - { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_ipas2e1_write }, - { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1_write }, - { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, -#ifndef CONFIG_USER_ONLY - /* 64 bit address translation operations */ - { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "AT_S12E1W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "AT_S12E0R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present= */ - { .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "AT_S1E3W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64= }, - { .name =3D "PAR_EL1", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 7, .crm =3D 4, .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]), - .writefn =3D par_write }, -#endif - /* TLB invalidate last level of translation table walk */ - { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, - { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, - .writefn =3D tlbimvaa_is_write }, - { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, - { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, - { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_write }, - { .name =3D "TLBIMVALHIS", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_is_write }, - { .name =3D "TLBIIPAS2", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_write }, - { .name =3D "TLBIIPAS2IS", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_is_write }, - { .name =3D "TLBIIPAS2L", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_write }, - { .name =3D "TLBIIPAS2LIS", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiipas2_is_write }, - /* 32 bit cache operations */ - { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - /* MMU Domain access control / MPU write buffer control */ - { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .writefn =3D dacr_write, .raw_writefn =3D raw_write, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), - offsetoflow32(CPUARMState, cp15.dacr_ns) } }, - { .name =3D "ELR_EL1", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, - { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, - /* We rely on the access checks not allowing the guest to write to the - * state field when SPSel indicates that it's being used as the stack - * pointer. - */ - { .name =3D "SP_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D sp_el0_access, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, sp_el[0]) }, - { .name =3D "SP_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, sp_el[1]) }, - { .name =3D "SPSel", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, - .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, - { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), - .access =3D PL2_RW, .accessfn =3D fpexc32_access }, - { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, - .writefn =3D dacr_write, .raw_writefn =3D raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, - { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, - { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, - { .name =3D "SPSR_ABT", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, - { .name =3D "SPSR_UND", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 2, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_UND]) }, - { .name =3D "SPSR_FIQ", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 3, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, - { .name =3D "MDCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, - .resetvalue =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr= _el3) }, - { .name =3D "SDCR", .type =3D ARM_CP_ALIAS, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, - .writefn =3D sdcr_write, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, - REGINFO_SENTINEL -}; - -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_NO_RAW, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, - { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - uint64_t valid_mask =3D HCR_MASK; - - if (arm_feature(env, ARM_FEATURE_EL3)) { - valid_mask &=3D ~HCR_HCD; - } else { - valid_mask &=3D ~HCR_TSC; - } - - /* Clear RES0 bits. */ - value &=3D valid_mask; - - /* These bits change the MMU setup: - * HCR_VM enables stage 2 translation - * HCR_PTW forbids certain page-table setups - * HCR_DC Disables stage1 and enables stage2 translation - */ - if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { - tlb_flush(CPU(cpu)); - } - raw_write(env, ri, value); -} - -static const ARMCPRegInfo el2_cp_reginfo[] =3D { - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_write }, - { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, elr_el[2]) }, - { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[2]) }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[2]) }, - { .name =3D "SPSR_EL2", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .writefn =3D vbar_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[2]), - .resetvalue =3D 0 }, - { .name =3D "SP_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, sp_el[2]) }, - { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[2]) }, - { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[2]), - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, - { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ - .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, - { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .type =3D ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, - { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ - .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, - { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2), - .writefn =3D vttbr_write }, - { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .writefn =3D vttbr_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2) }, - { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .raw_writefn =3D raw_write, .writefn =3D sctlr_w= rite, - .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[2]) }, - { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, - { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, - { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, - { .name =3D "TLBIALLNSNH", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_nsnh_write }, - { .name =3D "TLBIALLNSNHIS", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_nsnh_is_write }, - { .name =3D "TLBIALLH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_hyp_write }, - { .name =3D "TLBIALLHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_hyp_is_write }, - { .name =3D "TLBIMVAH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_write }, - { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_is_write }, - { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbi_aa64_alle2_write }, - { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbi_aa64_vae2_write }, - { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae2_write }, - { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle2is_write }, - { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae2is_write }, -#ifndef CONFIG_USER_ONLY - /* Unlike the other EL2-related AT operations, these must - * UNDEF from EL3 if EL2 is not implemented, which is why we - * define them here rather than with the rest of the AT ops. - */ - { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64 }, - { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW, .writefn =3D ats_write64 }, - /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE - * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 - * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se - * to behave as if SCR.NS was 1. - */ - { .name =3D "ATS1HR", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 0, - .access =3D PL2_W, - .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW }, - { .name =3D "ATS1HW", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 1, - .access =3D PL2_W, - .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW }, - { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the - * reset values as IMPDEF. We choose to reset to 3 to comply with - * both ARMv7 and ARMv8. - */ - .access =3D PL2_RW, .resetvalue =3D 3, - .fieldoffset =3D offsetof(CPUARMState, cp15.cnthctl_el2) }, - { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_IO, .resetvalue =3D 0, - .writefn =3D gt_cntvoff_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, - { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_I= O, - .writefn =3D gt_cntvoff_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, - { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cv= al), - .type =3D ARM_CP_IO, .access =3D PL2_RW, - .writefn =3D gt_hyp_cval_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cv= al), - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO, - .writefn =3D gt_hyp_cval_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, - .resetfn =3D gt_hyp_timer_reset, - .readfn =3D gt_hyp_tval_read, .writefn =3D gt_hyp_tval_write }, - { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .type =3D ARM_CP_IO, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ct= l), - .resetvalue =3D 0, - .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, -#endif - /* The only field of MDCR_EL2 that has a defined architectural reset v= alue - * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but= we - * don't impelment any PMU event counters, so using zero as a reset - * value for MDCR_EL2 is okay - */ - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, - { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, - { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, - { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 15, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 = =3D 3, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.hstr_el2) }, - REGINFO_SENTINEL -}; - -static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. - * At Secure EL1 it traps to EL3. - */ - if (arm_current_el(env) =3D=3D 3) { - return CP_ACCESS_OK; - } - if (arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_EL3; - } - /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads= . */ - if (isread) { - return CP_ACCESS_OK; - } - return CP_ACCESS_TRAP_UNCATEGORIZED; -} - -static const ARMCPRegInfo el3_cp_reginfo[] =3D { - { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), - .resetvalue =3D 0, .writefn =3D scr_write }, - { .name =3D "SCR", .type =3D ARM_CP_ALIAS, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.scr_el3), - .writefn =3D scr_write }, - { .name =3D "SDER32_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.sder) }, - { .name =3D "SDER", - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.sder) }, - { .name =3D "MVBAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0,= .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, - .writefn =3D vbar_write, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.mvbar) }, - { .name =3D "TTBR0_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[3]) }, - { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL3_RW, - /* no .writefn needed as this can't cause an ASID change; - * we must provide a .raw_writefn and .resetfn because we handle - * reset and migration for the AArch32 TTBCR(S), which might be - * using mask and base_mask. - */ - .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D vmsa_ttbcr_raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[3]) }, - { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL3_RW, - .fieldoffset =3D offsetof(CPUARMState, elr_el[3]) }, - { .name =3D "ESR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[3]) }, - { .name =3D "FAR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[3]) }, - { .name =3D "SPSR_EL3", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_MON]) }, - { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .writefn =3D vbar_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[3]), - .resetvalue =3D 0 }, - { .name =3D "CPTR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL3_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[3]) }, - { .name =3D "TPIDR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL3_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[3]) }, - { .name =3D "AMAIR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL3", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL3", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TLBI_ALLE3IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3is_write }, - { .name =3D "TLBI_VAE3IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, - { .name =3D "TLBI_VALE3IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, - { .name =3D "TLBI_ALLE3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3_write }, - { .name =3D "TLBI_VAE3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3_write }, - { .name =3D "TLBI_VALE3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3_write }, - REGINFO_SENTINEL -}; - -static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, - * but the AArch32 CTR has its own reginfo struct) - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= T)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Writes to OSLAR_EL1 may update the OS lock status, which can be - * read via a bit in OSLSR_EL1. - */ - int oslock; - - if (ri->state =3D=3D ARM_CP_STATE_AA32) { - oslock =3D (value =3D=3D 0xC5ACCE55); - } else { - oslock =3D value & 1; - } - - env->cp15.oslsr_el1 =3D deposit32(env->cp15.oslsr_el1, 1, 1, oslock); -} - -static const ARMCPRegInfo debug_cp_reginfo[] =3D { - /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped - * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; - * unlike DBGDRAR it is never accessible from EL0. - * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 - * accessor. - */ - { .name =3D "DBGDRAR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDRAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "DBGDSAR", .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* Monitor debug system control register; the 32-bit alias is DBGDSCRe= xt. */ - { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), - .resetvalue =3D 0 }, - /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. - * We don't implement the configurable EL0 access. - */ - { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 = =3D 0, - .type =3D ARM_CP_ALIAS, - .access =3D PL1_R, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), }, - { .name =3D "OSLAR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_tdosa, - .writefn =3D oslar_write }, - { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, - .access =3D PL1_R, .resetvalue =3D 10, - .accessfn =3D access_tdosa, - .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, - /* Dummy OSDLR_EL1: 32-bit Linux will read this */ - { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, - .access =3D PL1_RW, .accessfn =3D access_tdosa, - .type =3D ARM_CP_NOP }, - /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't - * implement vector catch debug events yet. - */ - { .name =3D "DBGVCR", - .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, - /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor - * to save and restore a 32-bit guest's DBGVCR) - */ - { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, - /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications - * Channel but Linux may try to access this register. The 32-bit - * alias is DBGDCCINT. - */ - { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { - /* 64 bit access versions of the (dummy) debug registers */ - { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, - { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, - REGINFO_SENTINEL -}; - -void hw_watchpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - vaddr len =3D 0; - vaddr wvr =3D env->cp15.dbgwvr[n]; - uint64_t wcr =3D env->cp15.dbgwcr[n]; - int mask; - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - - if (env->cpu_watchpoint[n]) { - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); - env->cpu_watchpoint[n] =3D NULL; - } - - if (!extract64(wcr, 0, 1)) { - /* E bit clear : watchpoint disabled */ - return; - } - - switch (extract64(wcr, 3, 2)) { - case 0: - /* LSC 00 is reserved and must behave as if the wp is disabled */ - return; - case 1: - flags |=3D BP_MEM_READ; - break; - case 2: - flags |=3D BP_MEM_WRITE; - break; - case 3: - flags |=3D BP_MEM_ACCESS; - break; - } - - /* Attempts to use both MASK and BAS fields simultaneously are - * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, - * thus generating a watchpoint for every byte in the masked region. - */ - mask =3D extract64(wcr, 24, 4); - if (mask =3D=3D 1 || mask =3D=3D 2) { - /* Reserved values of MASK; we must act as if the mask value was - * some non-reserved value, or as if the watchpoint were disabled. - * We choose the latter. - */ - return; - } else if (mask) { - /* Watchpoint covers an aligned area up to 2GB in size */ - len =3D 1ULL << mask; - /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE - * whether the watchpoint fires when the unmasked bits match; we o= pt - * to generate the exceptions. - */ - wvr &=3D ~(len - 1); - } else { - /* Watchpoint covers bytes defined by the byte address select bits= */ - int bas =3D extract64(wcr, 5, 8); - int basstart; - - if (bas =3D=3D 0) { - /* This must act as if the watchpoint is disabled */ - return; - } - - if (extract64(wvr, 2, 1)) { - /* Deprecated case of an only 4-aligned address. BAS[7:4] are - * ignored, and BAS[3:0] define which bytes to watch. - */ - bas &=3D 0xf; - } - /* The BAS bits are supposed to be programmed to indicate a contig= uous - * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er - * we fire for each byte in the word/doubleword addressed by the W= VR. - * We choose to ignore any non-zero bits after the first range of = 1s. - */ - basstart =3D ctz32(bas); - len =3D cto32(bas >> basstart); - wvr +=3D basstart; - } - - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, - &env->cpu_watchpoint[n]); -} - -void hw_watchpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* Completely clear out existing QEMU watchpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { - hw_watchpoint_update(cpu, i); - } -} - -static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - int i =3D ri->crm; - - /* Bits [63:49] are hardwired to the value of bit [48]; that is, the - * register reads and behaves as if values written are sign extended. - * Bits [1:0] are RES0. - */ - value =3D sextract64(value, 0, 49) & ~3ULL; - - raw_write(env, ri, value); - hw_watchpoint_update(cpu, i); -} - -static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - int i =3D ri->crm; - - raw_write(env, ri, value); - hw_watchpoint_update(cpu, i); -} - -void hw_breakpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - uint64_t bvr =3D env->cp15.dbgbvr[n]; - uint64_t bcr =3D env->cp15.dbgbcr[n]; - vaddr addr; - int bt; - int flags =3D BP_CPU; - - if (env->cpu_breakpoint[n]) { - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); - env->cpu_breakpoint[n] =3D NULL; - } - - if (!extract64(bcr, 0, 1)) { - /* E bit clear : watchpoint disabled */ - return; - } - - bt =3D extract64(bcr, 20, 4); - - switch (bt) { - case 4: /* unlinked address mismatch (reserved if AArch64) */ - case 5: /* linked address mismatch (reserved if AArch64) */ - qemu_log_mask(LOG_UNIMP, - "arm: address mismatch breakpoint types not implemen= ted"); - return; - case 0: /* unlinked address match */ - case 1: /* linked address match */ - { - /* Bits [63:49] are hardwired to the value of bit [48]; that is, - * we behave as if the register was sign extended. Bits [1:0] are - * RES0. The BAS field is used to allow setting breakpoints on 16 - * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether - * a bp will fire if the addresses covered by the bp and the addre= sses - * covered by the insn overlap but the insn doesn't start at the - * start of the bp address range. We choose to require the insn and - * the bp to have the same address. The constraints on writing to - * BAS enforced in dbgbcr_write mean we have only four cases: - * 0b0000 =3D> no breakpoint - * 0b0011 =3D> breakpoint on addr - * 0b1100 =3D> breakpoint on addr + 2 - * 0b1111 =3D> breakpoint on addr - * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). - */ - int bas =3D extract64(bcr, 5, 4); - addr =3D sextract64(bvr, 0, 49) & ~3ULL; - if (bas =3D=3D 0) { - return; - } - if (bas =3D=3D 0xc) { - addr +=3D 2; - } - break; - } - case 2: /* unlinked context ID match */ - case 8: /* unlinked VMID match (reserved if no EL2) */ - case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ - qemu_log_mask(LOG_UNIMP, - "arm: unlinked context breakpoint types not implemen= ted"); - return; - case 9: /* linked VMID match (reserved if no EL2) */ - case 11: /* linked context ID and VMID match (reserved if no EL2) */ - case 3: /* linked context ID match */ - default: - /* We must generate no events for Linked context matches (unless - * they are linked to by some other bp/wp, which is handled in - * updates for the linking bp/wp). We choose to also generate no e= vents - * for reserved values. - */ - return; - } - - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); -} - -void hw_breakpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* Completely clear out existing QEMU breakpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { - hw_breakpoint_update(cpu, i); - } -} - -static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - int i =3D ri->crm; - - raw_write(env, ri, value); - hw_breakpoint_update(cpu, i); -} - -static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - int i =3D ri->crm; - - /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only - * copy of BAS[0]. - */ - value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); - value =3D deposit64(value, 8, 1, extract64(value, 7, 1)); - - raw_write(env, ri, value); - hw_breakpoint_update(cpu, i); -} - -static void define_debug_regs(ARMCPU *cpu) -{ - /* Define v7 and v8 architectural debug registers. - * These are just dummy implementations for now. - */ - int i; - int wrps, brps, ctx_cmps; - ARMCPRegInfo dbgdidr =3D { - .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->dbgdidr, - }; - - /* Note that all these register fields hold "number of Xs minus 1". */ - brps =3D extract32(cpu->dbgdidr, 24, 4); - wrps =3D extract32(cpu->dbgdidr, 28, 4); - ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); - - assert(ctx_cmps <=3D brps); - - /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties - * of the debug registers such as number of breakpoints; - * check that if they both exist then they agree. - */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(extract32(cpu->id_aa64dfr0, 12, 4) =3D=3D brps); - assert(extract32(cpu->id_aa64dfr0, 20, 4) =3D=3D wrps); - assert(extract32(cpu->id_aa64dfr0, 28, 4) =3D=3D ctx_cmps); - } - - define_one_arm_cp_reg(cpu, &dbgdidr); - define_arm_cp_regs(cpu, debug_cp_reginfo); - - if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { - define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); - } - - for (i =3D 0; i < brps + 1; i++) { - ARMCPRegInfo dbgregs[] =3D { - { .name =3D "DBGBVR", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), - .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write - }, - { .name =3D "DBGBCR", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), - .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write - }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, dbgregs); - } - - for (i =3D 0; i < wrps + 1; i++) { - ARMCPRegInfo dbgregs[] =3D { - { .name =3D "DBGWVR", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), - .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write - }, - { .name =3D "DBGWCR", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), - .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write - }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, dbgregs); - } -} - -void register_cp_regs_for_features(ARMCPU *cpu) -{ - /* Register all the coprocessor registers based on feature bits */ - CPUARMState *env =3D &cpu->env; - if (arm_feature(env, ARM_FEATURE_M)) { - /* M profile has no coprocessor registers */ - return; - } - - define_arm_cp_regs(cpu, cp_reginfo); - if (!arm_feature(env, ARM_FEATURE_V8)) { - /* Must go early as it is full of wildcards that may be - * overridden by later definitions. - */ - define_arm_cp_regs(cpu, not_v8_cp_reginfo); - } - - if (arm_feature(env, ARM_FEATURE_V6)) { - /* The ID registers all have impdef reset values */ - ARMCPRegInfo v6_idregs[] =3D { - { .name =3D "ID_PFR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_pfr0 }, - { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_pfr1 }, - { .name =3D "ID_DFR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_dfr0 }, - { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_afr0 }, - { .name =3D "ID_MMFR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_mmfr0 }, - { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_mmfr1 }, - { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_mmfr2 }, - { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_mmfr3 }, - { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_isar0 }, - { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_isar1 }, - { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_isar2 }, - { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_isar3 }, - { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_isar4 }, - { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_isar5 }, - { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_mmfr4 }, - /* 7 is as yet unallocated and must RAZ */ - { .name =3D "ID_ISAR7_RESERVED", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, v6_idregs); - define_arm_cp_regs(cpu, v6_cp_reginfo); - } else { - define_arm_cp_regs(cpu, not_v6_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V6K)) { - define_arm_cp_regs(cpu, v6k_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V7MP) && - !arm_feature(env, ARM_FEATURE_MPU)) { - define_arm_cp_regs(cpu, v7mp_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V7)) { - /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement only the cycle - * count register. - */ #ifndef CONFIG_USER_ONLY - ARMCPRegInfo pmcr =3D { - .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL0_RW, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn =3D pmreg_access, .writefn =3D pmcr_write, - .raw_writefn =3D raw_write, - }; - ARMCPRegInfo pmcr64 =3D { - .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->midr & 0xff000000, - .writefn =3D pmcr_write, .raw_writefn =3D raw_write, - }; - define_one_arm_cp_reg(cpu, &pmcr); - define_one_arm_cp_reg(cpu, &pmcr64); -#endif - ARMCPRegInfo clidr =3D { - .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu= ->clidr - }; - define_one_arm_cp_reg(cpu, &clidr); - define_arm_cp_regs(cpu, v7_cp_reginfo); - define_debug_regs(cpu); - } else { - define_arm_cp_regs(cpu, not_v7_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V8)) { - /* AArch64 ID registers, which all have impdef reset values. - * Note that within the ID register ranges the unused slots - * must all RAZ, not UNDEF; future architecture versions may - * define new registers here. - */ - ARMCPRegInfo v8_idregs[] =3D { - { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64pfr0 }, - { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64pfr1}, - { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64PFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64PFR4_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64PFR5_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64PFR7_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64dfr0 }, - { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64dfr1 }, - { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64DFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64AFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64afr0 }, - { .name =3D "ID_AA64AFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64afr1 }, - { .name =3D "ID_AA64AFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64AFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64isar0 }, - { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64isar1 }, - { .name =3D "ID_AA64ISAR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64mmfr0 }, - { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64mmfr1 }, - { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "MVFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->mvfr0 }, - { .name =3D "MVFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->mvfr1 }, - { .name =3D "MVFR2_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->mvfr2 }, - { .name =3D "MVFR3_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "MVFR4_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "MVFR5_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "MVFR6_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "MVFR7_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid0 }, - { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid0 }, - { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid1 }, - { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid1 }, - REGINFO_SENTINEL - }; - /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ - if (!arm_feature(env, ARM_FEATURE_EL3) && - !arm_feature(env, ARM_FEATURE_EL2)) { - ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, - .type =3D ARM_CP_CONST, .access =3D PL1_R, .resetvalue =3D= cpu->rvbar - }; - define_one_arm_cp_reg(cpu, &rvbar); - } - define_arm_cp_regs(cpu, v8_idregs); - define_arm_cp_regs(cpu, v8_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_EL2)) { - uint64_t vmpidr_def =3D mpidr_read_val(env); - ARMCPRegInfo vpidr_regs[] =3D { - { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL2_RW, .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D vmpidr_def, - .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, - { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 5, - .access =3D PL2_RW, - .resetvalue =3D vmpidr_def, - .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, vpidr_regs); - define_arm_cp_regs(cpu, el2_cp_reginfo); - /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ - if (!arm_feature(env, ARM_FEATURE_EL3)) { - ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, - .type =3D ARM_CP_CONST, .access =3D PL2_R, .resetvalue =3D= cpu->rvbar - }; - define_one_arm_cp_reg(cpu, &rvbar); - } - } else { - /* If EL2 is missing but higher ELs are enabled, we need to - * register the no_el2 reginfos. - */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value - * of MIDR_EL1 and MPIDR_EL1. - */ - ARMCPRegInfo vpidr_regs[] =3D { - { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64= any, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64= any, - .type =3D ARM_CP_NO_RAW, - .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, vpidr_regs); - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); - } - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - define_arm_cp_regs(cpu, el3_cp_reginfo); - ARMCPRegInfo el3_regs[] =3D { - { .name =3D "RVBAR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D= 1, - .type =3D ARM_CP_CONST, .access =3D PL3_R, .resetvalue =3D c= pu->rvbar }, - { .name =3D "SCTLR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL3_RW, - .raw_writefn =3D raw_write, .writefn =3D sctlr_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), - .resetvalue =3D cpu->reset_sctlr }, - REGINFO_SENTINEL - }; - - define_arm_cp_regs(cpu, el3_regs); - } - /* The behaviour of NSACR is sufficiently various that we don't - * try to describe it in a single reginfo: - * if EL3 is 64 bit, then trap to EL3 from S EL1, - * reads as constant 0xc00 from NS EL1 and NS EL2 - * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 - * if v7 without EL3, register doesn't exist - * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 - */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - ARMCPRegInfo nsacr =3D { - .name =3D "NSACR", .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, - .access =3D PL1_RW, .accessfn =3D nsacr_access, - .resetvalue =3D 0xc00 - }; - define_one_arm_cp_reg(cpu, &nsacr); - } else { - ARMCPRegInfo nsacr =3D { - .name =3D "NSACR", - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, - .access =3D PL3_RW | PL1_R, - .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.nsacr) - }; - define_one_arm_cp_reg(cpu, &nsacr); - } - } else { - if (arm_feature(env, ARM_FEATURE_V8)) { - ARMCPRegInfo nsacr =3D { - .name =3D "NSACR", .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, - .access =3D PL1_R, - .resetvalue =3D 0xc00 - }; - define_one_arm_cp_reg(cpu, &nsacr); - } - } - - if (arm_feature(env, ARM_FEATURE_MPU)) { - if (arm_feature(env, ARM_FEATURE_V6)) { - /* PMSAv6 not implemented */ - assert(arm_feature(env, ARM_FEATURE_V7)); - define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); - define_arm_cp_regs(cpu, pmsav7_cp_reginfo); - } else { - define_arm_cp_regs(cpu, pmsav5_cp_reginfo); - } - } else { - define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); - define_arm_cp_regs(cpu, vmsa_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { - define_arm_cp_regs(cpu, t2ee_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - define_arm_cp_regs(cpu, generic_timer_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_VAPA)) { - define_arm_cp_regs(cpu, vapa_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { - define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { - define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { - define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_OMAPCP)) { - define_arm_cp_regs(cpu, omap_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_STRONGARM)) { - define_arm_cp_regs(cpu, strongarm_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - define_arm_cp_regs(cpu, xscale_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { - define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_LPAE)) { - define_arm_cp_regs(cpu, lpae_cp_reginfo); - } - /* Slightly awkwardly, the OMAP and StrongARM cores need all of - * cp15 crn=3D0 to be writes-ignored, whereas for other cores they sho= uld - * be read-only (ie write causes UNDEF exception). - */ - { - ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] =3D { - /* Pre-v8 MIDR space. - * Note that the MIDR isn't a simple constant register because - * of the TI925 behaviour where writes to another register can - * cause the MIDR value to change. - * - * Unimplemented registers in the c15 0 0 0 space default to - * MIDR. Define MIDR first as this entire space, then CTR, TCM= TR - * and friends override accordingly. - */ - { .name =3D "MIDR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .resetvalue =3D cpu->midr, - .writefn =3D arm_cp_write_ignore, .raw_writefn =3D raw_write, - .readfn =3D midr_read, - .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), - .type =3D ARM_CP_OVERRIDE }, - /* crn =3D 0 op1 =3D 0 crm =3D 3..7 : currently unassigned; we= RAZ. */ - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 3, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 4, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 5, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 6, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 7, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - REGINFO_SENTINEL - }; - ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { - { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), - .readfn =3D midr_read }, - /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, - { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->revidr }, - REGINFO_SENTINEL - }; - ARMCPRegInfo id_cp_reginfo[] =3D { - /* These are common to v8 and pre-v8 */ - { .name =3D "CTR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->ctr }, - { .name =3D "CTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 0, .crm =3D = 0, - .access =3D PL0_R, .accessfn =3D ctr_el0_access, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, - /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ - { .name =3D "TCMTR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - REGINFO_SENTINEL - }; - /* TLBTR is specific to VMSA */ - ARMCPRegInfo id_tlbtr_reginfo =3D { - .name =3D "TLBTR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0, - }; - /* MPUIR is specific to PMSA V6+ */ - ARMCPRegInfo id_mpuir_reginfo =3D { - .name =3D "MPUIR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->pmsav7_dregion << 8 - }; - ARMCPRegInfo crn0_wi_reginfo =3D { - .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, - .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE - }; - if (arm_feature(env, ARM_FEATURE_OMAPCP) || - arm_feature(env, ARM_FEATURE_STRONGARM)) { - ARMCPRegInfo *r; - /* Register the blanket "writes ignored" value first to cover = the - * whole space. Then update the specific ID registers to allow= write - * access, so that they ignore writes rather than causing them= to - * UNDEF. - */ - define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); - for (r =3D id_pre_v8_midr_cp_reginfo; - r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; - } - for (r =3D id_cp_reginfo; r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; - } - id_tlbtr_reginfo.access =3D PL1_RW; - id_tlbtr_reginfo.access =3D PL1_RW; - } - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); - } else { - define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); - } - define_arm_cp_regs(cpu, id_cp_reginfo); - if (!arm_feature(env, ARM_FEATURE_MPU)) { - define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); - } else if (arm_feature(env, ARM_FEATURE_V7)) { - define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); - } - } - - if (arm_feature(env, ARM_FEATURE_MPIDR)) { - define_arm_cp_regs(cpu, mpidr_cp_reginfo); - } - - if (arm_feature(env, ARM_FEATURE_AUXCR)) { - ARMCPRegInfo auxcr_reginfo[] =3D { - { .name =3D "ACTLR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->reset_auxcr }, - { .name =3D "ACTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ACTLR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, auxcr_reginfo); - } - - if (arm_feature(env, ARM_FEATURE_CBAR)) { - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - /* 32 bit view is [31:18] 0...0 [43:32]. */ - uint32_t cbar32 =3D (extract64(cpu->reset_cbar, 18, 14) << 18) - | extract64(cpu->reset_cbar, 32, 12); - ARMCPRegInfo cbar_reginfo[] =3D { - { .name =3D "CBAR", - .type =3D ARM_CP_CONST, - .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 4, .opc2 = =3D 0, - .access =3D PL1_R, .resetvalue =3D cpu->reset_cbar }, - { .name =3D "CBAR_EL1", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_CONST, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2= =3D 0, - .access =3D PL1_R, .resetvalue =3D cbar32 }, - REGINFO_SENTINEL - }; - /* We don't implement a r/w 64 bit CBAR currently */ - assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); - define_arm_cp_regs(cpu, cbar_reginfo); - } else { - ARMCPRegInfo cbar =3D { - .name =3D "CBAR", - .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 4, .opc2 = =3D 0, - .access =3D PL1_R|PL3_W, .resetvalue =3D cpu->reset_cbar, - .fieldoffset =3D offsetof(CPUARMState, - cp15.c15_config_base_address) - }; - if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { - cbar.access =3D PL1_R; - cbar.fieldoffset =3D 0; - cbar.type =3D ARM_CP_CONST; - } - define_one_arm_cp_reg(cpu, &cbar); - } - } - - if (arm_feature(env, ARM_FEATURE_VBAR)) { - ARMCPRegInfo vbar_cp_reginfo[] =3D { - { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, - .access =3D PL1_RW, .writefn =3D vbar_write, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), - offsetof(CPUARMState, cp15.vbar_ns) }, - .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, vbar_cp_reginfo); - } - - /* Generic registers whose values depend on the implementation */ - { - ARMCPRegInfo sctlr =3D { - .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), - offsetof(CPUARMState, cp15.sctlr_ns) }, - .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, - .raw_writefn =3D raw_write, - }; - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - /* Normally we would always end the TB on an SCTLR write, but = Linux - * arch/arm/mach-pxa/sleep.S expects two instructions following - * an MMU enable to execute from cache. Imitate this behaviou= r. - */ - sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; - } - define_one_arm_cp_reg(cpu, &sctlr); - } -} - -ARMCPU *cpu_arm_init(const char *cpu_model) -{ - return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); -} - -void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) -{ - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; - - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, - 34, "aarch64-fpu.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_NEON)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 51, "arm-neon.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP3)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 35, "arm-vfp3.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 19, "arm-vfp.xml", 0); - } -} - -/* Sort alphabetically by type name, except for "any". */ -static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) -{ - ObjectClass *class_a =3D (ObjectClass *)a; - ObjectClass *class_b =3D (ObjectClass *)b; - const char *name_a, *name_b; - - name_a =3D object_class_get_name(class_a); - name_b =3D object_class_get_name(class_b); - if (strcmp(name_a, "any-" TYPE_ARM_CPU) =3D=3D 0) { - return 1; - } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) =3D=3D 0) { - return -1; - } else { - return strcmp(name_a, name_b); - } -} - -static void arm_cpu_list_entry(gpointer data, gpointer user_data) -{ - ObjectClass *oc =3D data; - CPUListState *s =3D user_data; - const char *typename; - char *name; - - typename =3D object_class_get_name(oc); - name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CP= U)); - (*s->cpu_fprintf)(s->file, " %s\n", - name); - g_free(name); -} - -void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) -{ - CPUListState s =3D { - .file =3D f, - .cpu_fprintf =3D cpu_fprintf, - }; - GSList *list; - - list =3D object_class_get_list(TYPE_ARM_CPU, false); - list =3D g_slist_sort(list, arm_cpu_list_compare); - (*cpu_fprintf)(f, "Available CPUs:\n"); - g_slist_foreach(list, arm_cpu_list_entry, &s); - g_slist_free(list); -#ifdef CONFIG_KVM - /* The 'host' CPU type is dynamically registered only if KVM is - * enabled, so we have to special-case it here: - */ - (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); -#endif -} - -static void arm_cpu_add_definition(gpointer data, gpointer user_data) -{ - ObjectClass *oc =3D data; - CpuDefinitionInfoList **cpu_list =3D user_data; - CpuDefinitionInfoList *entry; - CpuDefinitionInfo *info; - const char *typename; - - typename =3D object_class_get_name(oc); - info =3D g_malloc0(sizeof(*info)); - info->name =3D g_strndup(typename, - strlen(typename) - strlen("-" TYPE_ARM_CPU)); - info->q_typename =3D g_strdup(typename); - - entry =3D g_malloc0(sizeof(*entry)); - entry->value =3D info; - entry->next =3D *cpu_list; - *cpu_list =3D entry; -} - -CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) -{ - CpuDefinitionInfoList *cpu_list =3D NULL; - GSList *list; - - list =3D object_class_get_list(TYPE_ARM_CPU, false); - g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); - g_slist_free(list); - - return cpu_list; -} - -static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, int state, int secstate, - int crm, int opc1, int opc2) -{ - /* Private utility function for define_one_arm_cp_reg_with_opaque(): - * add a single reginfo struct to the hash table. - */ - uint32_t *key =3D g_new(uint32_t, 1); - ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); - int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; - int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; - - /* Reset the secure state to the specific incoming state. This is - * necessary as the register may have been defined with both states. - */ - r2->secure =3D secstate; - - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { - /* Register is banked (using both entries in array). - * Overwriting fieldoffset as the array is only used to define - * banked registers but later only fieldoffset is used. - */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; - } - - if (state =3D=3D ARM_CP_STATE_AA32) { - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { - /* If the register is banked then we don't need to migrate or - * reset the 32-bit instance in certain cases: - * - * 1) If the register has both 32-bit and 64-bit instances the= n we - * can count on the 64-bit instance taking care of the - * non-secure bank. - * 2) If ARMv8 is enabled then we can count on a 64-bit version - * taking care of the secure bank. This requires that sepa= rate - * 32 and 64-bit definitions are provided. - */ - if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { - r2->type |=3D ARM_CP_ALIAS; - } - } else if ((secstate !=3D r->secure) && !ns) { - /* The register is not banked so we only want to allow migrati= on of - * the non-secure instance. - */ - r2->type |=3D ARM_CP_ALIAS; - } - - if (r->state =3D=3D ARM_CP_STATE_BOTH) { - /* We assume it is a cp15 register if the .cp field is left un= set. - */ - if (r2->cp =3D=3D 0) { - r2->cp =3D 15; - } - -#ifdef HOST_WORDS_BIGENDIAN - if (r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); - } +static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, + int access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, + target_ulong *page_size_ptr, uint32_t *fsr, + ARMMMUFaultInfo *fi); #endif - } - } - if (state =3D=3D ARM_CP_STATE_AA64) { - /* To allow abbreviation of ARMCPRegInfo - * definitions, we treat cp =3D=3D 0 as equivalent to - * the value for "standard guest-visible sysreg". - * STATE_BOTH definitions are also always "standard - * sysreg" in their AArch64 view (the .cp value may - * be non-zero for the benefit of the AArch32 view). - */ - if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { - r2->cp =3D CP_REG_ARM64_SYSREG_CP; - } - *key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); - } else { - *key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); - } - if (opaque) { - r2->opaque =3D opaque; - } - /* reginfo passed to helpers is correct for the actual access, - * and is never ARM_CP_STATE_BOTH: - */ - r2->state =3D state; - /* Make sure reginfo passed to helpers for wildcarded regs - * has the correct crm/opc1/opc2 for this reg, not CP_ANY: - */ - r2->crm =3D crm; - r2->opc1 =3D opc1; - r2->opc2 =3D opc2; - /* By convention, for wildcarded registers only the first - * entry is used for migration; the others are marked as - * ALIAS so we don't try to transfer the register - * multiple times. Special registers (ie NOP/WFI) are - * never migratable and not even raw-accessible. - */ - if ((r->type & ARM_CP_SPECIAL)) { - r2->type |=3D ARM_CP_NO_RAW; - } - if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || - ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || - ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS; - } - - /* Check that raw accesses are either forbidden or handled. Note that - * we can't assert this earlier because the setup of fieldoffset for - * banked registers has to be done first. - */ - if (!(r2->type & ARM_CP_NO_RAW)) { - assert(!raw_accessors_invalid(r2)); - } - - /* Overriding of an existing definition must be explicitly - * requested. - */ - if (!(r->type & ARM_CP_OVERRIDE)) { - ARMCPRegInfo *oldreg; - oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); - if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { - fprintf(stderr, "Register redefined: cp=3D%d %d bit " - "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " - "was %s, now %s\n", r2->cp, 32 + 32 * is64, - r2->crn, r2->crm, r2->opc1, r2->opc2, - oldreg->name, r2->name); - g_assert_not_reached(); - } - } - g_hash_table_insert(cpu->cp_regs, key, r2); -} - - -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *r, void *opaque) -{ - /* Define implementations of coprocessor registers. - * We store these in a hashtable because typically - * there are less than 150 registers in a space which - * is 16*16*16*8*8 =3D 262144 in size. - * Wildcarding is supported for the crm, opc1 and opc2 fields. - * If a register is defined twice then the second definition is - * used, so this can be used to define some generic registers and - * then override them with implementation specific variations. - * At least one of the original and the second definition should - * include ARM_CP_OVERRIDE in its type bits -- this is just a guard - * against accidental use. - * - * The state field defines whether the register is to be - * visible in the AArch32 or AArch64 execution state. If the - * state is set to ARM_CP_STATE_BOTH then we synthesise a - * reginfo structure for the AArch32 view, which sees the lower - * 32 bits of the 64 bit register. - * - * Only registers visible in AArch64 may set r->opc0; opc0 cannot - * be wildcarded. AArch64 registers are always considered to be 64 - * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of - * the register, if any. - */ - int crm, opc1, opc2, state; - int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; - int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; - int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; - int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; - int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; - int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; - /* 64 bit registers have only CRm and Opc1 fields */ - assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); - /* op0 only exists in the AArch64 encodings */ - assert((r->state !=3D ARM_CP_STATE_AA32) || (r->opc0 =3D=3D 0)); - /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ - assert((r->state !=3D ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); - /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 - * encodes a minimum access level for the register. We roll this - * runtime check into our general permission check code, so check - * here that the reginfo's specified permissions are strict enough - * to encompass the generic architectural permission check. - */ - if (r->state !=3D ARM_CP_STATE_AA32) { - int mask =3D 0; - switch (r->opc1) { - case 0: case 1: case 2: - /* min_EL EL1 */ - mask =3D PL1_RW; - break; - case 3: - /* min_EL EL0 */ - mask =3D PL0_RW; - break; - case 4: - /* min_EL EL2 */ - mask =3D PL2_RW; - break; - case 5: - /* unallocated encoding, so not possible */ - assert(false); - break; - case 6: - /* min_EL EL3 */ - mask =3D PL3_RW; - break; - case 7: - /* min_EL EL1, secure mode only (we don't check the latter) */ - mask =3D PL1_RW; - break; - default: - /* broken reginfo with out-of-range opc1 */ - assert(false); - break; - } - /* assert our permissions are not too lax (stricter is fine) */ - assert((r->access & ~mask) =3D=3D 0); - } - - /* Check that the register definition has enough info to handle - * reads and writes if they are permitted. - */ - if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { - if (r->access & PL3_R) { - assert((r->fieldoffset || - (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || - r->readfn); - } - if (r->access & PL3_W) { - assert((r->fieldoffset || - (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || - r->writefn); - } - } - /* Bad type field probably means missing sentinel at end of reg list */ - assert(cptype_valid(r->type)); - for (crm =3D crmmin; crm <=3D crmmax; crm++) { - for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { - for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { - for (state =3D ARM_CP_STATE_AA32; - state <=3D ARM_CP_STATE_AA64; state++) { - if (r->state !=3D state && r->state !=3D ARM_CP_STATE_= BOTH) { - continue; - } - if (state =3D=3D ARM_CP_STATE_AA32) { - /* Under AArch32 CP registers can be common - * (same for secure and non-secure world) or banke= d. - */ - switch (r->secure) { - case ARM_CP_SECSTATE_S: - case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, opaque, state, - r->secure, crm, opc1, o= pc2); - break; - default: - add_cpreg_to_hashtable(cpu, r, opaque, state, - ARM_CP_SECSTATE_S, - crm, opc1, opc2); - add_cpreg_to_hashtable(cpu, r, opaque, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2); - break; - } - } else { - /* AArch64 registers get mapped to non-secure inst= ance - * of AArch32 */ - add_cpreg_to_hashtable(cpu, r, opaque, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2); - } - } - } - } - } -} - -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque) -{ - /* Define a whole list of registers */ - const ARMCPRegInfo *r; - for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { - define_one_arm_cp_reg_with_opaque(cpu, r, opaque); - } -} - -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Helper coprocessor write function for write-ignore registers */ -} - -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* Helper coprocessor write function for read-as-zero registers */ - return 0; -} - -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) -{ - /* Helper coprocessor reset function for do-nothing-on-reset registers= */ -} - -static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) -{ - /* Return true if it is not valid for us to switch to - * this CPU mode (ie all the UNPREDICTABLE cases in - * the ARM ARM CPSRWriteByInstr pseudocode). - */ - - /* Changes to or from Hyp via MSR and CPS are illegal. */ - if (write_type =3D=3D CPSRWriteByInstr && - ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_HYP || - mode =3D=3D ARM_CPU_MODE_HYP)) { - return 1; - } - - switch (mode) { - case ARM_CPU_MODE_USR: - return 0; - case ARM_CPU_MODE_SYS: - case ARM_CPU_MODE_SVC: - case ARM_CPU_MODE_ABT: - case ARM_CPU_MODE_UND: - case ARM_CPU_MODE_IRQ: - case ARM_CPU_MODE_FIQ: - /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 - * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) - */ - /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR - * and CPS are treated as illegal mode changes. - */ - if (write_type =3D=3D CPSRWriteByInstr && - (env->cp15.hcr_el2 & HCR_TGE) && - (env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON && - !arm_is_secure_below_el3(env)) { - return 1; - } - return 0; - case ARM_CPU_MODE_HYP: - return !arm_feature(env, ARM_FEATURE_EL2) - || arm_current_el(env) < 2 || arm_is_secure(env); - case ARM_CPU_MODE_MON: - return arm_current_el(env) < 3; - default: - return 1; - } -} - -uint32_t cpsr_read(CPUARMState *env) -{ - int ZF; - ZF =3D (env->ZF =3D=3D 0); - return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | - (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) - | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) - | ((env->condexec_bits & 0xfc) << 8) - | (env->GE << 16) | (env->daif & CPSR_AIF); -} - -void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, - CPSRWriteType write_type) -{ - uint32_t changed_daif; - - if (mask & CPSR_NZCV) { - env->ZF =3D (~val) & CPSR_Z; - env->NF =3D val; - env->CF =3D (val >> 29) & 1; - env->VF =3D (val << 3) & 0x80000000; - } - if (mask & CPSR_Q) - env->QF =3D ((val & CPSR_Q) !=3D 0); - if (mask & CPSR_T) - env->thumb =3D ((val & CPSR_T) !=3D 0); - if (mask & CPSR_IT_0_1) { - env->condexec_bits &=3D ~3; - env->condexec_bits |=3D (val >> 25) & 3; - } - if (mask & CPSR_IT_2_7) { - env->condexec_bits &=3D 3; - env->condexec_bits |=3D (val >> 8) & 0xfc; - } - if (mask & CPSR_GE) { - env->GE =3D (val >> 16) & 0xf; - } - - /* In a V7 implementation that includes the security extensions but do= es - * not include Virtualization Extensions the SCR.FW and SCR.AW bits co= ntrol - * whether non-secure software is allowed to change the CPSR_F and CPS= R_A - * bits respectively. - * - * In a V8 implementation, it is permitted for privileged software to - * change the CPSR A/F bits regardless of the SCR.AW/FW bits. - */ - if (write_type !=3D CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) = && - arm_feature(env, ARM_FEATURE_EL3) && - !arm_feature(env, ARM_FEATURE_EL2) && - !arm_is_secure(env)) { - - changed_daif =3D (env->daif ^ val) & mask; - - if (changed_daif & CPSR_A) { - /* Check to see if we are allowed to change the masking of asy= nc - * abort exceptions from a non-secure state. - */ - if (!(env->cp15.scr_el3 & SCR_AW)) { - qemu_log_mask(LOG_GUEST_ERROR, - "Ignoring attempt to switch CPSR_A flag from= " - "non-secure world with SCR.AW bit clear\n"); - mask &=3D ~CPSR_A; - } - } - - if (changed_daif & CPSR_F) { - /* Check to see if we are allowed to change the masking of FIQ - * exceptions from a non-secure state. - */ - if (!(env->cp15.scr_el3 & SCR_FW)) { - qemu_log_mask(LOG_GUEST_ERROR, - "Ignoring attempt to switch CPSR_F flag from= " - "non-secure world with SCR.FW bit clear\n"); - mask &=3D ~CPSR_F; - } - - /* Check whether non-maskable FIQ (NMFI) support is enabled. - * If this bit is set software is not allowed to mask - * FIQs, but is allowed to set CPSR_F to 0. - */ - if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && - (val & CPSR_F)) { - qemu_log_mask(LOG_GUEST_ERROR, - "Ignoring attempt to enable CPSR_F flag " - "(non-maskable FIQ [NMFI] support enabled)\n= "); - mask &=3D ~CPSR_F; - } - } - } - - env->daif &=3D ~(CPSR_AIF & mask); - env->daif |=3D val & CPSR_AIF & mask; - - if (write_type !=3D CPSRWriteRaw && - ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { - if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_USR) { - /* Note that we can only get here in USR mode if this is a - * gdb stub write; for this case we follow the architectural - * behaviour for guest writes in USR mode of ignoring an attem= pt - * to switch mode. (Those are caught by translate.c for writes - * triggered by guest instructions.) - */ - mask &=3D ~CPSR_M; - } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { - /* Attempt to switch to an invalid mode: this is UNPREDICTABLE= in - * v7, and has defined behaviour in v8: - * + leave CPSR.M untouched - * + allow changes to the other CPSR fields - * + set PSTATE.IL - * For user changes via the GDB stub, we don't set PSTATE.IL, - * as this would be unnecessarily harsh for a user error. - */ - mask &=3D ~CPSR_M; - if (write_type !=3D CPSRWriteByGDBStub && - arm_feature(env, ARM_FEATURE_V8)) { - mask |=3D CPSR_IL; - val |=3D CPSR_IL; - } - } else { - switch_mode(env, val & CPSR_M); - } - } - mask &=3D ~CACHED_CPSR_BITS; - env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); -} =20 /* Sign/zero extend */ uint32_t HELPER(sxtb16)(uint32_t x) @@ -8162,11 +2429,11 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, * @page_size: set to the size of the page containing phys_ptr * @fsr: set to the DFSR/IFSR value on failure */ -static bool get_phys_addr(CPUARMState *env, target_ulong address, - int access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr, - ARMMMUFaultInfo *fi) +bool get_phys_addr(CPUARMState *env, target_ulong address, + int access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, uint32_t *fsr, + ARMMMUFaultInfo *fi) { if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { /* Call ourselves recursively to do the stage 1 and then stage 2 @@ -8757,82 +3024,9 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) return vfp_get_fpscr(env); } =20 -/* Convert vfp exception flags to target form. */ -static inline int vfp_exceptbits_to_host(int target_bits) -{ - int host_bits =3D 0; - - if (target_bits & 1) - host_bits |=3D float_flag_invalid; - if (target_bits & 2) - host_bits |=3D float_flag_divbyzero; - if (target_bits & 4) - host_bits |=3D float_flag_overflow; - if (target_bits & 8) - host_bits |=3D float_flag_underflow; - if (target_bits & 0x10) - host_bits |=3D float_flag_inexact; - if (target_bits & 0x80) - host_bits |=3D float_flag_input_denormal; - return host_bits; -} - -void vfp_set_fpsr(CPUARMState *env, uint32_t val) -{ - uint32_t new_fpscr =3D (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR= _MASK); - vfp_set_fpscr(env, new_fpscr); -} - -void vfp_set_fpcr(CPUARMState *env, uint32_t val) -{ - uint32_t new_fpscr =3D (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR= _MASK); - vfp_set_fpscr(env, new_fpscr); -} - void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { - int i; - uint32_t changed; - - changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; - env->vfp.xregs[ARM_VFP_FPSCR] =3D (val & 0xffc8ffff); - env->vfp.vec_len =3D (val >> 16) & 7; - env->vfp.vec_stride =3D (val >> 20) & 3; - - changed ^=3D val; - if (changed & (3 << 22)) { - i =3D (val >> 22) & 3; - switch (i) { - case FPROUNDING_TIEEVEN: - i =3D float_round_nearest_even; - break; - case FPROUNDING_POSINF: - i =3D float_round_up; - break; - case FPROUNDING_NEGINF: - i =3D float_round_down; - break; - case FPROUNDING_ZERO: - i =3D float_round_to_zero; - break; - } - set_float_rounding_mode(i, &env->vfp.fp_status); - } - if (changed & (1 << 24)) { - set_flush_to_zero((val & (1 << 24)) !=3D 0, &env->vfp.fp_status); - set_flush_inputs_to_zero((val & (1 << 24)) !=3D 0, &env->vfp.fp_st= atus); - } - if (changed & (1 << 25)) - set_default_nan_mode((val & (1 << 25)) !=3D 0, &env->vfp.fp_status= ); - - i =3D vfp_exceptbits_to_host(val); - set_float_exception_flags(i, &env->vfp.fp_status); - set_float_exception_flags(0, &env->vfp.standard_fp_status); -} - -void vfp_set_fpscr(CPUARMState *env, uint32_t val) -{ - HELPER(vfp_set_fpscr)(env, val); + vfp_set_fpscr(env, val); } =20 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) diff --git a/target/arm/internals.h b/target/arm/internals.h index f742a419ff..4f3f04030c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -498,4 +498,12 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } =20 +#ifndef CONFIG_USER_ONLY +bool get_phys_addr(CPUARMState *env, target_ulong address, + int access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, uint32_t *fsr, + ARMMMUFaultInfo *fi); +#endif + #endif --=20 2.11.1 From nobody Mon May 6 09:32:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488302961195297.75632580410183; Tue, 28 Feb 2017 09:29:21 -0800 (PST) Received: from localhost ([::1]:35836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilaP-000425-Jd for importer@patchew.org; Tue, 28 Feb 2017 12:29:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43820) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilPm-0003J9-04 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cilPj-0003hy-GO for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:17 -0500 Received: from clearmind.me ([178.32.49.9]:39637) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cilPj-0003go-6z for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=clearmind.me; s=dkim; h=Sender:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=O7NpNnCZr/Xf+uY+1Rdkb4PLxt0KSb9/MWRdbvU+/pM=; b=PF/W+jVX9TMWRAJmMNpcoFlId zNyFGUuNSCYXF1hlUy/MBzWxeVOmiY3dSE//qx2LfDGCJ4hviG71AferVtDjQXQy0f13Sly4yLTLL 4YiRkFzZ0riYOqik57sadpaeaxD+SIOLjx4nZhjp0f1n4znVGSk6rkDpj6J/bMJWvyab0=; From: Alessandro Di Federico To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 18:19:20 +0100 Message-Id: <20170228171921.21602-7-ale+qemu@clearmind.me> In-Reply-To: <20170228171921.21602-1-ale+qemu@clearmind.me> References: <20170228171921.21602-1-ale+qemu@clearmind.me> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.49.9 Subject: [Qemu-devel] [PATCH 6/7] Factor out tcg/tcg.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch factors out all the necessary data structures contained in tcg.h into include/tcg-common.h so that they can be made available to users of the library version of the TCG, libtcg. The data structures have been modified in a way that allows them to be easily prefixed in different ways depending on the situation. For internal use, the prefix will typically be TCG_ for constants and TCG for data structures, while it will be LIBTCG_/LibTCG for external use. In addition to this, certain data types (namely TCGReg, TCGRegSet and tcg_temp) have been forced to be the same over all the targets, so that the data structures are architecture-independent, a vital requirement to provide a uniform interface to libtcg users. Finally tcg/tcg-opc.h has been moved to include/. --- include/qemu-common.h | 3 + include/tcg-common.h | 233 +++++++++++++++++++++++++++++++++++++++++= ++++ {tcg =3D> include}/tcg-opc.h | 0 tcg/aarch64/tcg-target.h | 4 +- tcg/arm/tcg-target.h | 4 +- tcg/i386/tcg-target.h | 4 +- tcg/ia64/tcg-target.h | 4 +- tcg/mips/tcg-target.h | 4 +- tcg/ppc/tcg-target.h | 4 +- tcg/s390/tcg-target.h | 4 +- tcg/sparc/tcg-target.h | 4 +- tcg/tcg.c | 7 -- tcg/tcg.h | 212 ++--------------------------------------- tcg/tci/tcg-target.h | 4 +- 14 files changed, 264 insertions(+), 227 deletions(-) create mode 100644 include/tcg-common.h rename {tcg =3D> include}/tcg-opc.h (100%) diff --git a/include/qemu-common.h b/include/qemu-common.h index 1430390eb6..c81828ef55 100644 --- a/include/qemu-common.h +++ b/include/qemu-common.h @@ -12,6 +12,7 @@ #ifndef QEMU_COMMON_H #define QEMU_COMMON_H =20 +#include #include "qemu/fprintf-fn.h" =20 #define TFR(expr) do { if ((expr) !=3D -1) break; } while (errno =3D=3D EI= NTR) @@ -79,6 +80,8 @@ int qemu_openpty_raw(int *aslave, char *pty_name); void tcg_exec_init(unsigned long tb_size); bool tcg_enabled(void); =20 +typedef uint32_t TCGReg; + void cpu_exec_init_all(void); void cpu_exec_step_atomic(CPUState *cpu); =20 diff --git a/include/tcg-common.h b/include/tcg-common.h new file mode 100644 index 0000000000..856c4974a0 --- /dev/null +++ b/include/tcg-common.h @@ -0,0 +1,233 @@ +/* This is file has no include guards because it's OK to include it multip= le + * times */ + +/* Includers should define the following macros: + * + * PREFIX: prefix for data types and structures. + * PREFIX2: prefix for enum data types. + * PREFIX3: prefix for other enum data types which, internally, do not nee= d a + * prefix, since they already have one. + */ +#if !defined(PREFIX) || !defined(PREFIX2) || !defined(PREFIX3) +# error You need to define PREFIX, PREFIX2 and PREFIX3 to include this file +#endif + +#include + +/* Includers outside the QEMU environment might need this. */ +#ifndef TCG_TARGET_REG_BITS +# if __SIZEOF_POINTER__ =3D=3D 8 +# define TCG_TARGET_REG_BITS 64 +# define TCG_TARGET_REG_BITS 64 +# else +# define TCG_TARGET_REG_BITS 32 +# endif +#endif + +typedef uint64_t PREFIX(RegSet); +typedef uint64_t tcg_temp; +typedef uint64_t PREFIX(Arg); + +typedef struct PREFIX(ArgConstraint) { + uint16_t ct; + uint8_t alias_index; + union { + PREFIX(RegSet) regs; + } u; +} PREFIX(ArgConstraint); + +typedef enum PREFIX(Opcode) { +#define DEF(name, oargs, iargs, cargs, flags) PREFIX3(INDEX_op_ ## name), +#include "tcg-opc.h" +#undef DEF + PREFIX3(NB_OPS), +} PREFIX(Opcode); + +typedef enum PREFIX(TempVal) { + PREFIX3(TEMP_VAL_DEAD), + PREFIX3(TEMP_VAL_REG), + PREFIX3(TEMP_VAL_MEM), + PREFIX3(TEMP_VAL_CONST), +} PREFIX(TempVal); + +typedef enum PREFIX(Type) { + PREFIX2(TYPE_I32), + PREFIX2(TYPE_I64), + PREFIX2(TYPE_COUNT), /* number of different types */ + +#ifndef LIBTCG_INTERFACE + /* An alias for the size of the host register. */ +#if TCG_TARGET_REG_BITS =3D=3D 32 + PREFIX2(TYPE_REG) =3D PREFIX2(TYPE_I32), +#else + PREFIX2(TYPE_REG) =3D PREFIX2(TYPE_I64), +#endif + + /* An alias for the size of the native pointer. */ +#if UINTPTR_MAX =3D=3D UINT32_MAX + PREFIX2(TYPE_PTR) =3D PREFIX2(TYPE_I32), +#else + PREFIX2(TYPE_PTR) =3D PREFIX2(TYPE_I64), +#endif + + /* An alias for the size of the target "long", aka register. */ +#if TARGET_LONG_BITS =3D=3D 64 + PREFIX2(TYPE_TL) =3D PREFIX2(TYPE_I64), +#else + PREFIX2(TYPE_TL) =3D PREFIX2(TYPE_I32), +#endif +#endif +} PREFIX(Type); + +typedef struct PREFIX(Temp) { + PREFIX(Reg) reg:8; + PREFIX(TempVal) val_type:8; + PREFIX(Type) base_type:8; + PREFIX(Type) type:8; + unsigned int fixed_reg:1; + unsigned int indirect_reg:1; + unsigned int indirect_base:1; + unsigned int mem_coherent:1; + unsigned int mem_allocated:1; + unsigned int temp_local:1; /* If true, the temp is saved across + basic blocks. Otherwise, it is not + preserved across basic blocks. */ + unsigned int temp_allocated:1; /* never used for code gen */ + + tcg_temp val; + struct PREFIX(Temp) *mem_base; + intptr_t mem_offset; + const char *name; +} PREFIX(Temp); + +typedef struct PREFIX(OpDef) { + const char *name; + uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; + uint8_t flags; + PREFIX(ArgConstraint) *args_ct; + int *sorted_args; +#if defined(CONFIG_DEBUG_TCG) + int used; +#endif +} PREFIX(OpDef); + +/* Conditions. Note that these are laid out for easy manipulation by + the functions below: + bit 0 is used for inverting; + bit 1 is signed, + bit 2 is unsigned, + bit 3 is used with bit 0 for swapping signed/unsigned. */ +typedef enum { + /* non-signed */ + PREFIX2(COND_NEVER) =3D 0 | 0 | 0 | 0, + PREFIX2(COND_ALWAYS) =3D 0 | 0 | 0 | 1, + PREFIX2(COND_EQ) =3D 8 | 0 | 0 | 0, + PREFIX2(COND_NE) =3D 8 | 0 | 0 | 1, + /* signed */ + PREFIX2(COND_LT) =3D 0 | 0 | 2 | 0, + PREFIX2(COND_GE) =3D 0 | 0 | 2 | 1, + PREFIX2(COND_LE) =3D 8 | 0 | 2 | 0, + PREFIX2(COND_GT) =3D 8 | 0 | 2 | 1, + /* unsigned */ + PREFIX2(COND_LTU) =3D 0 | 4 | 0 | 0, + PREFIX2(COND_GEU) =3D 0 | 4 | 0 | 1, + PREFIX2(COND_LEU) =3D 8 | 4 | 0 | 0, + PREFIX2(COND_GTU) =3D 8 | 4 | 0 | 1, +} PREFIX(Cond); + +/* Constants for qemu_ld and qemu_st for the Memory Operation field. */ +typedef enum PREFIX(MemOp) { + PREFIX3(MO_8) =3D 0, + PREFIX3(MO_16) =3D 1, + PREFIX3(MO_32) =3D 2, + PREFIX3(MO_64) =3D 3, + PREFIX3(MO_SIZE) =3D 3, /* Mask for the above. */ + + PREFIX3(MO_SIGN) =3D 4, /* Sign-extended, otherwise zero-extended. = */ + + PREFIX3(MO_BSWAP) =3D 8, /* Host reverse endian. */ +#ifndef LIBTCG_INTERFACE +#ifdef HOST_WORDS_BIGENDIAN + PREFIX3(MO_LE) =3D PREFIX3(MO_BSWAP), + PREFIX3(MO_BE) =3D 0, +#else + PREFIX3(MO_LE) =3D 0, + PREFIX3(MO_BE) =3D PREFIX3(MO_BSWAP), +#endif +#ifdef TARGET_WORDS_BIGENDIAN + PREFIX3(MO_TE) =3D PREFIX3(MO_BE), +#else + PREFIX3(MO_TE) =3D PREFIX3(MO_LE), +#endif + + /* MO_UNALN accesses are never checked for alignment. + * MO_ALIGN accesses will result in a call to the CPU's + * do_unaligned_access hook if the guest address is not aligned. + * The default depends on whether the target CPU defines ALIGNED_ONLY. + * + * Some architectures (e.g. ARMv8) need the address which is aligned + * to a size more than the size of the memory access. + * Some architectures (e.g. SPARCv9) need an address which is aligned, + * but less strictly than the natural alignment. + * + * MO_ALIGN supposes the alignment size is the size of a memory access. + * + * There are three options: + * - unaligned access permitted (MO_UNALN). + * - an alignment to the size of an access (MO_ALIGN); + * - an alignment to a specified size, which may be more or less than + * the access size (MO_ALIGN_x where 'x' is a size in bytes); + */ + PREFIX3(MO_ASHIFT) =3D 4, + PREFIX3(MO_AMASK) =3D 7 << PREFIX3(MO_ASHIFT), +#ifdef ALIGNED_ONLY + PREFIX3(MO_ALIGN) =3D 0, + PREFIX3(MO_UNALN) =3D PREFIX3(MO_AMASK), +#else + PREFIX3(MO_ALIGN) =3D PREFIX3(MO_AMASK), + PREFIX3(MO_UNALN) =3D 0, +#endif + PREFIX3(MO_ALIGN_2) =3D 1 << PREFIX3(MO_ASHIFT), + PREFIX3(MO_ALIGN_4) =3D 2 << PREFIX3(MO_ASHIFT), + PREFIX3(MO_ALIGN_8) =3D 3 << PREFIX3(MO_ASHIFT), + PREFIX3(MO_ALIGN_16) =3D 4 << PREFIX3(MO_ASHIFT), + PREFIX3(MO_ALIGN_32) =3D 5 << PREFIX3(MO_ASHIFT), + PREFIX3(MO_ALIGN_64) =3D 6 << PREFIX3(MO_ASHIFT), + + /* Combinations of the above, for ease of use. */ + PREFIX3(MO_UB) =3D PREFIX3(MO_8), + PREFIX3(MO_UW) =3D PREFIX3(MO_16), + PREFIX3(MO_UL) =3D PREFIX3(MO_32), + PREFIX3(MO_SB) =3D PREFIX3(MO_SIGN) | PREFIX3(MO_8), + PREFIX3(MO_SW) =3D PREFIX3(MO_SIGN) | PREFIX3(MO_16), + PREFIX3(MO_SL) =3D PREFIX3(MO_SIGN) | PREFIX3(MO_32), + PREFIX3(MO_Q) =3D PREFIX3(MO_64), + + PREFIX3(MO_LEUW) =3D PREFIX3(MO_LE) | PREFIX3(MO_UW), + PREFIX3(MO_LEUL) =3D PREFIX3(MO_LE) | PREFIX3(MO_UL), + PREFIX3(MO_LESW) =3D PREFIX3(MO_LE) | PREFIX3(MO_SW), + PREFIX3(MO_LESL) =3D PREFIX3(MO_LE) | PREFIX3(MO_SL), + PREFIX3(MO_LEQ) =3D PREFIX3(MO_LE) | PREFIX3(MO_Q), + + PREFIX3(MO_BEUW) =3D PREFIX3(MO_BE) | PREFIX3(MO_UW), + PREFIX3(MO_BEUL) =3D PREFIX3(MO_BE) | PREFIX3(MO_UL), + PREFIX3(MO_BESW) =3D PREFIX3(MO_BE) | PREFIX3(MO_SW), + PREFIX3(MO_BESL) =3D PREFIX3(MO_BE) | PREFIX3(MO_SL), + PREFIX3(MO_BEQ) =3D PREFIX3(MO_BE) | PREFIX3(MO_Q), + + PREFIX3(MO_TEUW) =3D PREFIX3(MO_TE) | PREFIX3(MO_UW), + PREFIX3(MO_TEUL) =3D PREFIX3(MO_TE) | PREFIX3(MO_UL), + PREFIX3(MO_TESW) =3D PREFIX3(MO_TE) | PREFIX3(MO_SW), + PREFIX3(MO_TESL) =3D PREFIX3(MO_TE) | PREFIX3(MO_SL), + PREFIX3(MO_TEQ) =3D PREFIX3(MO_TE) | PREFIX3(MO_Q), + + PREFIX3(MO_SSIZE) =3D PREFIX3(MO_SIZE) | PREFIX3(MO_SIGN), +#endif +} PREFIX(MemOp); + +typedef struct PREFIX(HelperInfo) { + void *func; + const char *name; + unsigned flags; + unsigned sizemask; +} PREFIX(HelperInfo); diff --git a/tcg/tcg-opc.h b/include/tcg-opc.h similarity index 100% rename from tcg/tcg-opc.h rename to include/tcg-opc.h diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 1a5ea23844..3a23a4c025 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -17,7 +17,7 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 #undef TCG_TARGET_STACK_GROWSUP =20 -typedef enum { +enum { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11, @@ -35,7 +35,7 @@ typedef enum { TCG_REG_FP =3D TCG_REG_X29, TCG_REG_LR =3D TCG_REG_X30, TCG_AREG0 =3D TCG_REG_X19, -} TCGReg; +}; =20 #define TCG_TARGET_NB_REGS 32 =20 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 09a19c6f35..7e9e5dc372 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -61,7 +61,7 @@ extern int arm_arch; #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 =20 -typedef enum { +enum { TCG_REG_R0 =3D 0, TCG_REG_R1, TCG_REG_R2, @@ -78,7 +78,7 @@ typedef enum { TCG_REG_R13, TCG_REG_R14, TCG_REG_PC, -} TCGReg; +}; =20 #define TCG_TARGET_NB_REGS 16 =20 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 21d96ec35c..89d0771e90 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -36,7 +36,7 @@ # define TCG_TARGET_NB_REGS 8 #endif =20 -typedef enum { +enum { TCG_REG_EAX =3D 0, TCG_REG_ECX, TCG_REG_EDX, @@ -64,7 +64,7 @@ typedef enum { TCG_REG_RBP =3D TCG_REG_EBP, TCG_REG_RSI =3D TCG_REG_ESI, TCG_REG_RDI =3D TCG_REG_EDI, -} TCGReg; +}; =20 /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_ESP=20 diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h index 42aea03a8b..230f1de1c8 100644 --- a/tcg/ia64/tcg-target.h +++ b/tcg/ia64/tcg-target.h @@ -36,7 +36,7 @@ typedef struct { =20 /* We only map the first 64 registers */ #define TCG_TARGET_NB_REGS 64 -typedef enum { +enum { TCG_REG_R0 =3D 0, TCG_REG_R1, TCG_REG_R2, @@ -103,7 +103,7 @@ typedef enum { TCG_REG_R63, =20 TCG_AREG0 =3D TCG_REG_R32, -} TCGReg; +}; =20 #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S22 0x200 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index f46d64a3a7..acd1aea71b 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -39,7 +39,7 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 =20 -typedef enum { +enum { TCG_REG_ZERO =3D 0, TCG_REG_AT, TCG_REG_V0, @@ -75,7 +75,7 @@ typedef enum { =20 TCG_REG_CALL_STACK =3D TCG_REG_SP, TCG_AREG0 =3D TCG_REG_S0, -} TCGReg; +}; =20 /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 16 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index abd8b3d6cd..e08ac7dc91 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -35,7 +35,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 =20 -typedef enum { +enum { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, @@ -47,7 +47,7 @@ typedef enum { =20 TCG_REG_CALL_STACK =3D TCG_REG_R1, TCG_AREG0 =3D TCG_REG_R27 -} TCGReg; +}; =20 extern bool have_isa_2_06; extern bool have_isa_3_00; diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index cbdd2a6275..2345946c54 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -28,7 +28,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 2 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 =20 -typedef enum TCGReg { +enum TCGReg { TCG_REG_R0 =3D 0, TCG_REG_R1, TCG_REG_R2, @@ -45,7 +45,7 @@ typedef enum TCGReg { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15 -} TCGReg; +}; =20 #define TCG_TARGET_NB_REGS 16 =20 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index b8b74f96ff..6652c776ec 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -31,7 +31,7 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 #define TCG_TARGET_NB_REGS 32 =20 -typedef enum { +enum { TCG_REG_G0 =3D 0, TCG_REG_G1, TCG_REG_G2, @@ -64,7 +64,7 @@ typedef enum { TCG_REG_I5, TCG_REG_I6, TCG_REG_I7, -} TCGReg; +}; =20 #define TCG_CT_CONST_S11 0x100 #define TCG_CT_CONST_S13 0x200 diff --git a/tcg/tcg.c b/tcg/tcg.c index cb898f1636..652131e5e9 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -307,13 +307,6 @@ void tcg_pool_reset(TCGContext *s) s->pool_current =3D NULL; } =20 -typedef struct TCGHelperInfo { - void *func; - const char *name; - unsigned flags; - unsigned sizemask; -} TCGHelperInfo; - #include "exec/helper-proto.h" =20 static const TCGHelperInfo all_helpers[] =3D { diff --git a/tcg/tcg.h b/tcg/tcg.h index 631c6f69b1..09e452ca46 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -79,13 +79,16 @@ typedef uint64_t tcg_target_ulong; #error unsupported #endif =20 -#if TCG_TARGET_NB_REGS <=3D 32 -typedef uint32_t TCGRegSet; -#elif TCG_TARGET_NB_REGS <=3D 64 -typedef uint64_t TCGRegSet; -#else -#error unsupported -#endif +#define PREFIX(x) TCG ## x +#define PREFIX2(x) TCG_ ## x +/* No prefix if not libtcg */ +#define PREFIX3(x) x + +#include "tcg-common.h" + +#undef PREFIX +#undef PREFIX2 +#undef PREFIX3 =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Turn some undef macros into false macros. */ @@ -169,13 +172,6 @@ typedef uint64_t TCGRegSet; # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) #endif =20 -typedef enum TCGOpcode { -#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, -#include "tcg-opc.h" -#undef DEF - NB_OPS, -} TCGOpcode; - #define tcg_regset_clear(d) (d) =3D 0 #define tcg_regset_set(d, s) (d) =3D (s) #define tcg_regset_set32(d, reg, val32) (d) |=3D (val32) << (reg) @@ -243,121 +239,6 @@ typedef struct TCGPool { this value, they are statically allocated in the TB stack frame */ #define TCG_STATIC_CALL_ARGS_SIZE 128 =20 -typedef enum TCGType { - TCG_TYPE_I32, - TCG_TYPE_I64, - TCG_TYPE_COUNT, /* number of different types */ - - /* An alias for the size of the host register. */ -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_TYPE_REG =3D TCG_TYPE_I32, -#else - TCG_TYPE_REG =3D TCG_TYPE_I64, -#endif - - /* An alias for the size of the native pointer. */ -#if UINTPTR_MAX =3D=3D UINT32_MAX - TCG_TYPE_PTR =3D TCG_TYPE_I32, -#else - TCG_TYPE_PTR =3D TCG_TYPE_I64, -#endif - - /* An alias for the size of the target "long", aka register. */ -#if TARGET_LONG_BITS =3D=3D 64 - TCG_TYPE_TL =3D TCG_TYPE_I64, -#else - TCG_TYPE_TL =3D TCG_TYPE_I32, -#endif -} TCGType; - -/* Constants for qemu_ld and qemu_st for the Memory Operation field. */ -typedef enum TCGMemOp { - MO_8 =3D 0, - MO_16 =3D 1, - MO_32 =3D 2, - MO_64 =3D 3, - MO_SIZE =3D 3, /* Mask for the above. */ - - MO_SIGN =3D 4, /* Sign-extended, otherwise zero-extended. */ - - MO_BSWAP =3D 8, /* Host reverse endian. */ -#ifdef HOST_WORDS_BIGENDIAN - MO_LE =3D MO_BSWAP, - MO_BE =3D 0, -#else - MO_LE =3D 0, - MO_BE =3D MO_BSWAP, -#endif -#ifdef TARGET_WORDS_BIGENDIAN - MO_TE =3D MO_BE, -#else - MO_TE =3D MO_LE, -#endif - - /* MO_UNALN accesses are never checked for alignment. - * MO_ALIGN accesses will result in a call to the CPU's - * do_unaligned_access hook if the guest address is not aligned. - * The default depends on whether the target CPU defines ALIGNED_ONLY. - * - * Some architectures (e.g. ARMv8) need the address which is aligned - * to a size more than the size of the memory access. - * Some architectures (e.g. SPARCv9) need an address which is aligned, - * but less strictly than the natural alignment. - * - * MO_ALIGN supposes the alignment size is the size of a memory access. - * - * There are three options: - * - unaligned access permitted (MO_UNALN). - * - an alignment to the size of an access (MO_ALIGN); - * - an alignment to a specified size, which may be more or less than - * the access size (MO_ALIGN_x where 'x' is a size in bytes); - */ - MO_ASHIFT =3D 4, - MO_AMASK =3D 7 << MO_ASHIFT, -#ifdef ALIGNED_ONLY - MO_ALIGN =3D 0, - MO_UNALN =3D MO_AMASK, -#else - MO_ALIGN =3D MO_AMASK, - MO_UNALN =3D 0, -#endif - MO_ALIGN_2 =3D 1 << MO_ASHIFT, - MO_ALIGN_4 =3D 2 << MO_ASHIFT, - MO_ALIGN_8 =3D 3 << MO_ASHIFT, - MO_ALIGN_16 =3D 4 << MO_ASHIFT, - MO_ALIGN_32 =3D 5 << MO_ASHIFT, - MO_ALIGN_64 =3D 6 << MO_ASHIFT, - - /* Combinations of the above, for ease of use. */ - MO_UB =3D MO_8, - MO_UW =3D MO_16, - MO_UL =3D MO_32, - MO_SB =3D MO_SIGN | MO_8, - MO_SW =3D MO_SIGN | MO_16, - MO_SL =3D MO_SIGN | MO_32, - MO_Q =3D MO_64, - - MO_LEUW =3D MO_LE | MO_UW, - MO_LEUL =3D MO_LE | MO_UL, - MO_LESW =3D MO_LE | MO_SW, - MO_LESL =3D MO_LE | MO_SL, - MO_LEQ =3D MO_LE | MO_Q, - - MO_BEUW =3D MO_BE | MO_UW, - MO_BEUL =3D MO_BE | MO_UL, - MO_BESW =3D MO_BE | MO_SW, - MO_BESL =3D MO_BE | MO_SL, - MO_BEQ =3D MO_BE | MO_Q, - - MO_TEUW =3D MO_TE | MO_UW, - MO_TEUL =3D MO_TE | MO_UL, - MO_TESW =3D MO_TE | MO_SW, - MO_TESL =3D MO_TE | MO_SL, - MO_TEQ =3D MO_TE | MO_Q, - - MO_SSIZE =3D MO_SIZE | MO_SIGN, -} TCGMemOp; - /** * get_alignment_bits * @memop: TCGMemOp value @@ -385,8 +266,6 @@ static inline unsigned get_alignment_bits(TCGMemOp memo= p) return a; } =20 -typedef tcg_target_ulong TCGArg; - /* Define type and accessor macros for TCG variables. =20 TCG variables are the inputs and outputs of TCG ops, as described @@ -515,30 +394,6 @@ typedef enum { TCG_BAR_SC =3D 0x30, /* No ops cross barrier; OR of the above */ } TCGBar; =20 -/* Conditions. Note that these are laid out for easy manipulation by - the functions below: - bit 0 is used for inverting; - bit 1 is signed, - bit 2 is unsigned, - bit 3 is used with bit 0 for swapping signed/unsigned. */ -typedef enum { - /* non-signed */ - TCG_COND_NEVER =3D 0 | 0 | 0 | 0, - TCG_COND_ALWAYS =3D 0 | 0 | 0 | 1, - TCG_COND_EQ =3D 8 | 0 | 0 | 0, - TCG_COND_NE =3D 8 | 0 | 0 | 1, - /* signed */ - TCG_COND_LT =3D 0 | 0 | 2 | 0, - TCG_COND_GE =3D 0 | 0 | 2 | 1, - TCG_COND_LE =3D 8 | 0 | 2 | 0, - TCG_COND_GT =3D 8 | 0 | 2 | 1, - /* unsigned */ - TCG_COND_LTU =3D 0 | 4 | 0 | 0, - TCG_COND_GEU =3D 0 | 4 | 0 | 1, - TCG_COND_LEU =3D 8 | 4 | 0 | 0, - TCG_COND_GTU =3D 8 | 4 | 0 | 1, -} TCGCond; - /* Invert the sense of the comparison. */ static inline TCGCond tcg_invert_cond(TCGCond c) { @@ -578,34 +433,6 @@ static inline TCGCond tcg_high_cond(TCGCond c) } } =20 -typedef enum TCGTempVal { - TEMP_VAL_DEAD, - TEMP_VAL_REG, - TEMP_VAL_MEM, - TEMP_VAL_CONST, -} TCGTempVal; - -typedef struct TCGTemp { - TCGReg reg:8; - TCGTempVal val_type:8; - TCGType base_type:8; - TCGType type:8; - unsigned int fixed_reg:1; - unsigned int indirect_reg:1; - unsigned int indirect_base:1; - unsigned int mem_coherent:1; - unsigned int mem_allocated:1; - unsigned int temp_local:1; /* If true, the temp is saved across - basic blocks. Otherwise, it is not - preserved across basic blocks. */ - unsigned int temp_allocated:1; /* never used for code gen */ - - tcg_target_long val; - struct TCGTemp *mem_base; - intptr_t mem_offset; - const char *name; -} TCGTemp; - typedef struct TCGContext TCGContext; =20 typedef struct TCGTempSet { @@ -858,14 +685,6 @@ void tcg_dump_op_count(FILE *f, fprintf_function cpu_f= printf); #define TCG_CT_REG 0x01 #define TCG_CT_CONST 0x02 /* any constant of register size */ =20 -typedef struct TCGArgConstraint { - uint16_t ct; - uint8_t alias_index; - union { - TCGRegSet regs; - } u; -} TCGArgConstraint; - #define TCG_MAX_OP_ARGS 16 =20 /* Bits for TCGOpDef->flags, 8 bits available. */ @@ -884,17 +703,6 @@ enum { TCG_OPF_NOT_PRESENT =3D 0x10, }; =20 -typedef struct TCGOpDef { - const char *name; - uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; - uint8_t flags; - TCGArgConstraint *args_ct; - int *sorted_args; -#if defined(CONFIG_DEBUG_TCG) - int used; -#endif -} TCGOpDef; - extern TCGOpDef tcg_op_defs[]; extern const size_t tcg_op_defs_max; =20 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 838bf3a858..321b5465c4 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -135,7 +135,7 @@ /* #define TCG_TARGET_NB_REGS 32 */ =20 /* List of registers which are used by TCG. */ -typedef enum { +enum { TCG_REG_R0 =3D 0, TCG_REG_R1, TCG_REG_R2, @@ -174,7 +174,7 @@ typedef enum { #endif /* Special value UINT8_MAX is used by TCI to encode constant values. */ TCG_CONST =3D UINT8_MAX -} TCGReg; +}; =20 #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2) =20 --=20 2.11.1 From nobody Mon May 6 09:32:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488303515518836.5116578624351; Tue, 28 Feb 2017 09:38:35 -0800 (PST) Received: from localhost ([::1]:35902 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciljN-00031Q-UO for importer@patchew.org; Tue, 28 Feb 2017 12:38:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilPt-0003P9-9Y for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cilPk-0003iN-AG for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:25 -0500 Received: from clearmind.me ([178.32.49.9]:43007) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cilPj-0003gs-Li for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:18:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=clearmind.me; s=dkim; h=Sender:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=DJxrzM5pmq0EjlvU2W0RImd5QtKBh8luphg6osCuOBk=; b=QMeH/YCifgQQoVy1G8FMkvoWQ am3+uJT724AuicBi16Tt33goFDCO3S2VYYkGwO2XIIQaoSU15Waw6GLq8tlLJoSqJkCLnSyHckVNn l9K1GLFS0zELkadrI7GtHklbx44Dp7OvR7qG+7tT/1QuUMcCDDcEPup57294/x78pEO4c=; From: Alessandro Di Federico To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 18:19:21 +0100 Message-Id: <20170228171921.21602-8-ale+qemu@clearmind.me> In-Reply-To: <20170228171921.21602-1-ale+qemu@clearmind.me> References: <20170228171921.21602-1-ale+qemu@clearmind.me> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.49.9 Subject: [Qemu-devel] [PATCH 7/7] Introduce libtcg infrastructure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" * Extend the build system to build libtcg-$arch.so dynamic libraries. * Introduce --enable-libtcg and --disable-libtcg the *-libtcg target, similar to *-linux-user and *-bsd-user, since it enables CONFIG_USER_ONLY, but uses only the TCG frontends (in particular the various target/$arch/translate.c files). * If there's at least a *-libtcg target, compile everything as position independent code and with -fvisibility=3Dhidden. * In case we're building libtcg, install the output binary in the $PREFIX/lib directory instead of $PREFIX/bin. * Reduce the number of object files linked into libtcg-$arch.so to the minimum. To achieve this, we break some dependency edges among translation units, for instance by replacing references to helper functions with NULL pointers (see the HELPER_REF macro). We also disable some portions of the code uninteresting to libtcg users (e.g., the various cpu_*_dump functions). * Introduce and install the libtcg.h header to use libtcg. Note that the only function exported by the libtcg library is libtcg_init, all the others have to be accessed through an interface data structure. * Introduce tests to load all the compiled versions of the libtcg library and try to translate the code for some architectures. * Make the tb_alloc function available outside translate-all.c. --- Makefile | 9 ++ Makefile.target | 45 +++++- configure | 20 +++ crypto/Makefile.objs | 2 +- default-configs/aarch64-libtcg.mak | 0 default-configs/alpha-libtcg.mak | 0 default-configs/arm-libtcg.mak | 0 default-configs/armeb-libtcg.mak | 0 default-configs/cris-libtcg.mak | 0 default-configs/hppa-libtcg.mak | 0 default-configs/i386-libtcg.mak | 0 default-configs/m68k-libtcg.mak | 0 default-configs/microblaze-libtcg.mak | 0 default-configs/microblazeel-libtcg.mak | 0 default-configs/mips-libtcg.mak | 0 default-configs/mips64-libtcg.mak | 0 default-configs/mips64el-libtcg.mak | 0 default-configs/mipsel-libtcg.mak | 0 default-configs/mipsn32-libtcg.mak | 0 default-configs/mipsn32el-libtcg.mak | 0 default-configs/nios2-libtcg.mak | 0 default-configs/or1k-libtcg.mak | 0 default-configs/or32-libtcg.mak | 0 default-configs/ppc-libtcg.mak | 1 + default-configs/ppc64-libtcg.mak | 1 + default-configs/ppc64abi32-libtcg.mak | 1 + default-configs/ppc64le-libtcg.mak | 1 + default-configs/s390x-libtcg.mak | 0 default-configs/sh4-libtcg.mak | 0 default-configs/sh4eb-libtcg.mak | 0 default-configs/sparc-libtcg.mak | 0 default-configs/sparc32plus-libtcg.mak | 0 default-configs/sparc64-libtcg.mak | 0 default-configs/tilegx-libtcg.mak | 0 default-configs/unicore32-libtcg.mak | 0 default-configs/x86_64-libtcg.mak | 0 hw/core/Makefile.objs | 5 +- include/exec/helper-gen.h | 12 +- include/exec/helper-head.h | 8 ++ include/exec/helper-tcg.h | 12 +- include/libtcg.h | 109 +++++++++++++++ include/tcg-common.h | 3 + libtcg/Makefile.objs | 1 + libtcg/libtcg.c | 226 ++++++++++++++++++++++++++++= ++ libtcg/qemu.h | 7 + qom/cpu.c | 4 +- target/alpha/Makefile.objs | 8 +- target/alpha/cpu.c | 6 +- target/alpha/translate.c | 2 + target/arm/Makefile.objs | 21 ++- target/arm/coprocessors.c | 12 ++ target/arm/cpu.c | 20 ++- target/arm/cpu64.c | 2 + target/arm/translate.c | 2 + target/cris/Makefile.objs | 9 +- target/cris/cpu.c | 28 +++- target/cris/translate.c | 2 + target/hppa/Makefile.objs | 6 +- target/hppa/cpu.c | 10 +- target/hppa/translate.c | 2 + target/i386/Makefile.objs | 15 +- target/i386/cpu.c | 24 +++- target/i386/translate.c | 2 + target/lm32/Makefile.objs | 11 +- target/lm32/translate.c | 2 + target/m68k/Makefile.objs | 6 +- target/m68k/cpu.c | 12 +- target/m68k/translate.c | 2 + target/microblaze/Makefile.objs | 9 +- target/microblaze/cpu.c | 6 +- target/microblaze/translate.c | 2 + target/mips/Makefile.objs | 10 +- target/mips/cpu.c | 8 +- target/mips/translate.c | 2 + target/moxie/Makefile.objs | 8 +- target/moxie/translate.c | 2 + target/nios2/Makefile.objs | 6 +- target/nios2/cpu.c | 17 ++- target/nios2/translate.c | 2 + target/openrisc/Makefile.objs | 11 +- target/openrisc/cpu.c | 7 +- target/openrisc/translate.c | 2 + target/ppc/Makefile.objs | 19 +-- target/ppc/translate.c | 2 + target/ppc/translate_init.c | 16 ++- target/s390x/Makefile.objs | 16 ++- target/s390x/cpu.c | 8 +- target/s390x/translate.c | 2 + target/sh4/Makefile.objs | 7 +- target/sh4/cpu.c | 10 +- target/sh4/translate.c | 2 + target/sparc/Makefile.objs | 13 +- target/sparc/cpu.c | 12 +- target/sparc/translate.c | 2 + target/tilegx/Makefile.objs | 6 +- target/tilegx/cpu.c | 12 +- target/tilegx/translate.c | 12 +- target/tricore/Makefile.objs | 6 +- target/tricore/translate.c | 2 + target/unicore32/Makefile.objs | 7 +- target/unicore32/cpu.c | 6 +- target/unicore32/translate.c | 2 + target/xtensa/Makefile.objs | 13 +- target/xtensa/translate.c | 2 + tcg/tcg.c | 8 +- tcg/tcg.h | 1 + tests/Makefile.include | 7 +- tests/test-libtcg.c | 238 ++++++++++++++++++++++++++++= ++++ trace/Makefile.objs | 2 +- translate-all.c | 2 +- 110 files changed, 1068 insertions(+), 130 deletions(-) create mode 100644 default-configs/aarch64-libtcg.mak create mode 100644 default-configs/alpha-libtcg.mak create mode 100644 default-configs/arm-libtcg.mak create mode 100644 default-configs/armeb-libtcg.mak create mode 100644 default-configs/cris-libtcg.mak create mode 100644 default-configs/hppa-libtcg.mak create mode 100644 default-configs/i386-libtcg.mak create mode 100644 default-configs/m68k-libtcg.mak create mode 100644 default-configs/microblaze-libtcg.mak create mode 100644 default-configs/microblazeel-libtcg.mak create mode 100644 default-configs/mips-libtcg.mak create mode 100644 default-configs/mips64-libtcg.mak create mode 100644 default-configs/mips64el-libtcg.mak create mode 100644 default-configs/mipsel-libtcg.mak create mode 100644 default-configs/mipsn32-libtcg.mak create mode 100644 default-configs/mipsn32el-libtcg.mak create mode 100644 default-configs/nios2-libtcg.mak create mode 100644 default-configs/or1k-libtcg.mak create mode 100644 default-configs/or32-libtcg.mak create mode 100644 default-configs/ppc-libtcg.mak create mode 100644 default-configs/ppc64-libtcg.mak create mode 100644 default-configs/ppc64abi32-libtcg.mak create mode 100644 default-configs/ppc64le-libtcg.mak create mode 100644 default-configs/s390x-libtcg.mak create mode 100644 default-configs/sh4-libtcg.mak create mode 100644 default-configs/sh4eb-libtcg.mak create mode 100644 default-configs/sparc-libtcg.mak create mode 100644 default-configs/sparc32plus-libtcg.mak create mode 100644 default-configs/sparc64-libtcg.mak create mode 100644 default-configs/tilegx-libtcg.mak create mode 100644 default-configs/unicore32-libtcg.mak create mode 100644 default-configs/x86_64-libtcg.mak create mode 100644 include/libtcg.h create mode 100644 libtcg/Makefile.objs create mode 100644 libtcg/libtcg.c create mode 100644 libtcg/qemu.h create mode 100644 tests/test-libtcg.c diff --git a/Makefile b/Makefile index 1c4c04f6f2..5c5ac8ae80 100644 --- a/Makefile +++ b/Makefile @@ -26,7 +26,16 @@ endif =20 CONFIG_SOFTMMU :=3D $(if $(filter %-softmmu,$(TARGET_DIRS)),y) CONFIG_USER_ONLY :=3D $(if $(filter %-user,$(TARGET_DIRS)),y) +CONFIG_LIBTCG :=3D $(if $(filter %-libtcg,$(TARGET_DIRS)),y) CONFIG_ALL=3Dy + +# If there's at least a *-libtcg target we need to build everything with -= fPIC +# and with default visibility hidden, so that we don't export symbols that= are +# not needed +ifeq ($(CONFIG_LIBTCG),y) +QEMU_CFLAGS +=3D -fPIC -fvisibility=3Dhidden +endif + -include config-all-devices.mak -include config-all-disas.mak =20 diff --git a/Makefile.target b/Makefile.target index cf8adc3ced..c02cb679cd 100644 --- a/Makefile.target +++ b/Makefile.target @@ -15,10 +15,24 @@ QEMU_CFLAGS +=3D -I.. -I$(SRC_PATH)/target/$(TARGET_BAS= E_ARCH) -DNEED_CPU_H =20 QEMU_CFLAGS+=3D-I$(SRC_PATH)/include =20 +# By default install in bindir +PROGS_INSTALL_DIR :=3D $(bindir) + ifdef CONFIG_USER_ONLY +ifdef CONFIG_LIBTCG +# libtcg +QEMU_PROG=3Dlibtcg-$(TARGET_NAME)$(DSOSUF).$(VERSION) +QEMU_PROG_BUILD =3D $(QEMU_PROG) +QEMU_CFLAGS +=3D -fPIC -fvisibility=3Dhidden +LIBTCG_SONAME=3Dlibtcg-$(TARGET_NAME)$(DSOSUF).0 + +# Change the install directory +PROGS_INSTALL_DIR :=3D $(libdir) +else # user emulator name QEMU_PROG=3Dqemu-$(TARGET_NAME) QEMU_PROG_BUILD =3D $(QEMU_PROG) +endif else # system emulator name QEMU_PROG=3Dqemu-system-$(TARGET_NAME)$(EXESUF) @@ -88,18 +102,22 @@ all: $(PROGS) stap =20 ######################################################### # cpu emulator library -obj-y =3D exec.o translate-all.o cpu-exec.o +obj-y =3D exec.o translate-all.o obj-$(call land,$(CONFIG_USER_ONLY),$(call lnot,$(CONFIG_BSD_USER))) +=3D = mmap.o +ifndef CONFIG_LIBTCG +obj-y +=3D cpu-exec.o +obj-y +=3D tcg-runtime.o +obj-y +=3D fpu/softfloat.o +obj-y +=3D tcg/optimize.o +endif obj-y +=3D translate-common.o obj-y +=3D cpu-exec-common.o -obj-y +=3D tcg/tcg.o tcg/tcg-op.o tcg/optimize.o +obj-y +=3D tcg/tcg.o tcg/tcg-op.o obj-$(CONFIG_TCG_INTERPRETER) +=3D tci.o obj-y +=3D tcg/tcg-common.o obj-$(CONFIG_TCG_INTERPRETER) +=3D disas/tci.o -obj-y +=3D fpu/softfloat.o obj-y +=3D target/$(TARGET_BASE_ARCH)/ obj-y +=3D disas.o -obj-y +=3D tcg-runtime.o obj-$(call notempty,$(TARGET_XML_FILES)) +=3D gdbstub-xml.o obj-$(call lnot,$(CONFIG_HAX)) +=3D hax-stub.o obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o @@ -138,6 +156,19 @@ obj-y +=3D gdbstub.o user-exec.o user-exec-stub.o endif #CONFIG_BSD_USER =20 ######################################################### +# libtcg target + +ifdef CONFIG_LIBTCG + +QEMU_CFLAGS+=3D-I$(SRC_PATH)/libtcg + +obj-y +=3D libtcg/ + +LDFLAGS+=3D$(LDFLAGS_SHARED) -Wl,-soname,$(LIBTCG_SONAME) + +endif #CONFIG_LIBTCG + +######################################################### # System emulator target ifdef CONFIG_SOFTMMU obj-y +=3D arch_init.o cpus.o monitor.o gdbstub.o balloon.o ioport.o numa.o @@ -230,8 +261,12 @@ ifdef CONFIG_TRACE_SYSTEMTAP endif =20 install: all +ifdef CONFIG_LIBTCG + mkdir -p "$(DESTDIR)$(includedir)" + $(INSTALL_DATA) $(SRC_PATH)/include/tcg-opc.h $(SRC_PATH)/include/libtcg.= h $(SRC_PATH)/include/tcg-common.h "$(DESTDIR)$(includedir)" +endif ifneq ($(PROGS),) - $(call install-prog,$(PROGS),$(DESTDIR)$(bindir)) + $(call install-prog,$(PROGS),$(DESTDIR)$(PROGS_INSTALL_DIR)) endif ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset" diff --git a/configure b/configure index 4b68861992..d848a4f0be 100755 --- a/configure +++ b/configure @@ -265,6 +265,7 @@ cocoa=3D"no" softmmu=3D"yes" linux_user=3D"no" bsd_user=3D"no" +libtcg=3D"no" aix=3D"no" blobs=3D"yes" pkgversion=3D"" @@ -678,6 +679,7 @@ Haiku) audio_possible_drivers=3D"oss alsa sdl pa" linux=3D"yes" linux_user=3D"yes" + libtcg=3D"yes" kvm=3D"yes" vhost_net=3D"yes" vhost_scsi=3D"yes" @@ -971,6 +973,10 @@ for opt do ;; --enable-bsd-user) bsd_user=3D"yes" ;; + --disable-libtcg) libtcg=3D"no" + ;; + --enable-libtcg) libtcg=3D"yes" + ;; --enable-pie) pie=3D"yes" ;; --disable-pie) pie=3D"no" @@ -1247,6 +1253,7 @@ EXTRA_CFLAGS=3D"$CPU_CFLAGS $EXTRA_CFLAGS" if [ "$ARCH" =3D "unknown" ]; then bsd_user=3D"no" linux_user=3D"no" + libtcg=3D"no" fi =20 default_target_list=3D"" @@ -1262,6 +1269,9 @@ fi if [ "$bsd_user" =3D "yes" ]; then mak_wilds=3D"${mak_wilds} $source_path/default-configs/*-bsd-user.mak" fi +if [ "$libtcg" =3D "yes" ]; then + mak_wilds=3D"${mak_wilds} $source_path/default-configs/*-libtcg.mak" +fi =20 for config in $mak_wilds; do default_target_list=3D"${default_target_list} $(basename "$config" .ma= k)" @@ -1403,6 +1413,7 @@ disabled with --disable-FEATURE, default is enabled i= f available: tcmalloc tcmalloc support jemalloc jemalloc support replication replication support + libtcg standalone TCG library =20 NOTE: The object files are built at the place where configure is launched EOF @@ -5114,6 +5125,7 @@ echo "tcmalloc support $tcmalloc" echo "jemalloc support $jemalloc" echo "avx2 optimization $avx2_opt" echo "replication support $replication" +echo "libtcg enabled $libtcg" =20 if test "$sdl_too_old" =3D "yes"; then echo "-> Your SDL version is too old - please upgrade to have SDL support" @@ -5851,6 +5863,7 @@ target_softmmu=3D"no" target_user_only=3D"no" target_linux_user=3D"no" target_bsd_user=3D"no" +target_libtcg=3D"no" case "$target" in ${target_name}-softmmu) target_softmmu=3D"yes" @@ -5869,6 +5882,10 @@ case "$target" in target_user_only=3D"yes" target_bsd_user=3D"yes" ;; + ${target_name}-libtcg) + target_user_only=3D"yes" + target_libtcg=3D"yes" + ;; *) error_exit "Target '$target' not recognised" exit 1 @@ -6074,6 +6091,9 @@ fi if test "$target_linux_user" =3D "yes" ; then echo "CONFIG_LINUX_USER=3Dy" >> $config_target_mak fi +if test "$target_libtcg" =3D "yes" ; then + echo "CONFIG_LIBTCG=3Dy" >> $config_target_mak +fi list=3D"" if test ! -z "$gdb_xml_files" ; then for x in $gdb_xml_files; do diff --git a/crypto/Makefile.objs b/crypto/Makefile.objs index 1f749f2087..2f654db9af 100644 --- a/crypto/Makefile.objs +++ b/crypto/Makefile.objs @@ -7,7 +7,7 @@ crypto-obj-y +=3D hmac.o crypto-obj-$(CONFIG_NETTLE) +=3D hmac-nettle.o crypto-obj-$(CONFIG_GCRYPT_HMAC) +=3D hmac-gcrypt.o crypto-obj-$(if $(CONFIG_NETTLE),n,$(if $(CONFIG_GCRYPT_HMAC),n,y)) +=3D h= mac-glib.o -crypto-obj-y +=3D aes.o +crypto-obj-$(call lnot,$(CONFIG_LIBTCG)) +=3D aes.o crypto-obj-y +=3D desrfb.o crypto-obj-y +=3D cipher.o crypto-obj-y +=3D tlscreds.o diff --git a/default-configs/aarch64-libtcg.mak b/default-configs/aarch64-l= ibtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/alpha-libtcg.mak b/default-configs/alpha-libtc= g.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/arm-libtcg.mak b/default-configs/arm-libtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/armeb-libtcg.mak b/default-configs/armeb-libtc= g.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/cris-libtcg.mak b/default-configs/cris-libtcg.= mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/hppa-libtcg.mak b/default-configs/hppa-libtcg.= mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/i386-libtcg.mak b/default-configs/i386-libtcg.= mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/m68k-libtcg.mak b/default-configs/m68k-libtcg.= mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/microblaze-libtcg.mak b/default-configs/microb= laze-libtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/microblazeel-libtcg.mak b/default-configs/micr= oblazeel-libtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/mips-libtcg.mak b/default-configs/mips-libtcg.= mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/mips64-libtcg.mak b/default-configs/mips64-lib= tcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/mips64el-libtcg.mak b/default-configs/mips64el= -libtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/mipsel-libtcg.mak b/default-configs/mipsel-lib= tcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/mipsn32-libtcg.mak b/default-configs/mipsn32-l= ibtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/mipsn32el-libtcg.mak b/default-configs/mipsn32= el-libtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/nios2-libtcg.mak b/default-configs/nios2-libtc= g.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/or1k-libtcg.mak b/default-configs/or1k-libtcg.= mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/or32-libtcg.mak b/default-configs/or32-libtcg.= mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/ppc-libtcg.mak b/default-configs/ppc-libtcg.mak new file mode 100644 index 0000000000..7235c56d55 --- /dev/null +++ b/default-configs/ppc-libtcg.mak @@ -0,0 +1 @@ +CONFIG_LIBDECNUMBER=3Dy diff --git a/default-configs/ppc64-libtcg.mak b/default-configs/ppc64-libtc= g.mak new file mode 100644 index 0000000000..7235c56d55 --- /dev/null +++ b/default-configs/ppc64-libtcg.mak @@ -0,0 +1 @@ +CONFIG_LIBDECNUMBER=3Dy diff --git a/default-configs/ppc64abi32-libtcg.mak b/default-configs/ppc64a= bi32-libtcg.mak new file mode 100644 index 0000000000..7235c56d55 --- /dev/null +++ b/default-configs/ppc64abi32-libtcg.mak @@ -0,0 +1 @@ +CONFIG_LIBDECNUMBER=3Dy diff --git a/default-configs/ppc64le-libtcg.mak b/default-configs/ppc64le-l= ibtcg.mak new file mode 100644 index 0000000000..7235c56d55 --- /dev/null +++ b/default-configs/ppc64le-libtcg.mak @@ -0,0 +1 @@ +CONFIG_LIBDECNUMBER=3Dy diff --git a/default-configs/s390x-libtcg.mak b/default-configs/s390x-libtc= g.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/sh4-libtcg.mak b/default-configs/sh4-libtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/sh4eb-libtcg.mak b/default-configs/sh4eb-libtc= g.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/sparc-libtcg.mak b/default-configs/sparc-libtc= g.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/sparc32plus-libtcg.mak b/default-configs/sparc= 32plus-libtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/sparc64-libtcg.mak b/default-configs/sparc64-l= ibtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/tilegx-libtcg.mak b/default-configs/tilegx-lib= tcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/unicore32-libtcg.mak b/default-configs/unicore= 32-libtcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/default-configs/x86_64-libtcg.mak b/default-configs/x86_64-lib= tcg.mak new file mode 100644 index 0000000000..e69de29bb2 diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 91450b2eab..71d5f65ccb 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -1,11 +1,14 @@ # core qdev-related obj files, also used by *-user: -common-obj-y +=3D qdev.o qdev-properties.o +common-obj-y +=3D qdev-properties.o +#ifndef CONFIG_LIBTCG common-obj-y +=3D bus.o reset.o +common-obj-y +=3D qdev.o common-obj-y +=3D fw-path-provider.o # irq.o needed for qdev GPIO handling: common-obj-y +=3D irq.o common-obj-y +=3D hotplug.o obj-y +=3D nmi.o +#endif =20 common-obj-$(CONFIG_EMPTY_SLOT) +=3D empty_slot.o common-obj-$(CONFIG_XILINX_AXI) +=3D stream.o diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 8239ffc77c..ac290180b3 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -9,7 +9,7 @@ #define DEF_HELPER_FLAGS_0(name, flags, ret) \ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ { \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 0, NULL); \ + tcg_gen_callN(&tcg_ctx, HELPER_REF(name), dh_retvar(ret), 0, NULL); \ } =20 #define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ @@ -17,7 +17,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1)) \ { \ TCGArg args[1] =3D { dh_arg(t1, 1) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 1, args); \ + tcg_gen_callN(&tcg_ctx, HELPER_REF(name), dh_retvar(ret), 1, args); \ } =20 #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ @@ -25,7 +25,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ { \ TCGArg args[2] =3D { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 2, args); \ + tcg_gen_callN(&tcg_ctx, HELPER_REF(name), dh_retvar(ret), 2, args); \ } =20 #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ @@ -33,7 +33,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ { \ TCGArg args[3] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 3, args); \ + tcg_gen_callN(&tcg_ctx, HELPER_REF(name), dh_retvar(ret), 3, args); \ } =20 #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ @@ -43,7 +43,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ { \ TCGArg args[4] =3D { dh_arg(t1, 1), dh_arg(t2, 2), \ dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 4, args); \ + tcg_gen_callN(&tcg_ctx, HELPER_REF(name), dh_retvar(ret), 4, args); \ } =20 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ @@ -53,7 +53,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ { \ TCGArg args[5] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 5, args); \ + tcg_gen_callN(&tcg_ctx, HELPER_REF(name), dh_retvar(ret), 5, args); \ } =20 #include "helper.h" diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 1cfc43b9ff..26bd3a47b1 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -20,6 +20,14 @@ =20 #define HELPER(name) glue(helper_, name) =20 +/* In libtcg we don't want helpers, therefore we leave these fields empty = so + * that we don't needlessly introduce a dependency towards the helper. */ +#ifdef CONFIG_LIBTCG +# define HELPER_REF(helper) (NULL) +#else +# define HELPER_REF(helper) (HELPER(helper)) +#endif + #define GET_TCGV_i32 GET_TCGV_I32 #define GET_TCGV_i64 GET_TCGV_I64 #define GET_TCGV_ptr GET_TCGV_PTR diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index bb9287727c..ebc7b45d1a 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -7,30 +7,30 @@ #include "exec/helper-head.h" =20 #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func =3D HELPER(NAME), .name =3D #NAME, .flags =3D FLAGS, \ + { .func =3D HELPER_REF(NAME), .name =3D #NAME, .flags =3D FLAGS, \ .sizemask =3D dh_sizemask(ret, 0) }, =20 #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func =3D HELPER(NAME), .name =3D #NAME, .flags =3D FLAGS, \ + { .func =3D HELPER_REF(NAME), .name =3D #NAME, .flags =3D FLAGS, \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, =20 #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func =3D HELPER(NAME), .name =3D #NAME, .flags =3D FLAGS, \ + { .func =3D HELPER_REF(NAME), .name =3D #NAME, .flags =3D FLAGS, \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) }, =20 #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func =3D HELPER(NAME), .name =3D #NAME, .flags =3D FLAGS, \ + { .func =3D HELPER_REF(NAME), .name =3D #NAME, .flags =3D FLAGS, \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, =20 #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func =3D HELPER(NAME), .name =3D #NAME, .flags =3D FLAGS, \ + { .func =3D HELPER_REF(NAME), .name =3D #NAME, .flags =3D FLAGS, \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, =20 #define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func =3D HELPER(NAME), .name =3D #NAME, .flags =3D FLAGS, \ + { .func =3D HELPER_REF(NAME), .name =3D #NAME, .flags =3D FLAGS, \ .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, diff --git a/include/libtcg.h b/include/libtcg.h new file mode 100644 index 0000000000..8996742cbd --- /dev/null +++ b/include/libtcg.h @@ -0,0 +1,109 @@ +#ifndef LIBTCG_H +#define LIBTCG_H + +#include +#include + +#define PREFIX(x) LibTCG ## x +#define PREFIX2(x) LIBTCG_ ## x +#define PREFIX3(x) LIBTCG_ ## x + +typedef uint8_t PREFIX(Reg); + +#include "tcg-common.h" + +#undef PREFIX +#undef PREFIX2 +#undef PREFIX3 + +/** + * This is a reduced version of TCGOp + */ +typedef struct LibTCGOp { + LibTCGOpcode opc:8; + + /* The number of out and in parameter for a call. */ + unsigned calli:4; + unsigned callo:2; + + LibTCGArg *args; +} LibTCGOp; + +/** + * Data structure holding a list of instructions, along with their argumen= ts, + * global and local variables + */ +typedef struct { + LibTCGOp *instructions; + unsigned instruction_count; + + /* Additional data, do not access this directly */ + LibTCGArg *arguments; + LibTCGTemp *temps; + unsigned global_temps; + unsigned total_temps; +} LibTCGInstructions; + +/** + * Pair of an address in the emulated address space, and the corresponding + * address in the host address space + */ +typedef struct { + uint64_t virtual_address; + void *pointer; +} address_pair; + +/** + * Maps a page in the emulated address space, if possible at @start. See m= map(2) + * for further documentation. + * + * @return an address pair, i.e., the start of the mmap'd region in terms = of the + * host and emulated address space. + */ +typedef address_pair (*libtcg_mmap_func)(uint64_t start, uint64_t len, int= prot, + int flags, int fd, off_t offset); + +/** + * Translates the basic block starting at @virtual_address into tiny code + * instructions. + * + * @param virtual_address: the starting address of the basic block, in ter= ms of + * the emulated address space. + * + * @return an instance of LibTCGInstructions containing the list generated= of + * tiny code instructions. The caller is responsible to call + * free_instructions on this object when it's no longer needed. + */ +typedef LibTCGInstructions (*libtcg_translate_func)(uint64_t virtual_addre= ss); + +/** + * Releases the memory hold by @instructions. + */ +typedef void (*libtcg_free_instructions_func)(LibTCGInstructions *instruct= ions); + +typedef struct { + libtcg_mmap_func mmap; + libtcg_translate_func translate; + libtcg_free_instructions_func free_instructions; +} LibTCGInterface; + +/** + * Initializes libtcg to generate code for @cpu_name. + * + * This is the only function exported by libtcg. Users are supposed to obt= ain + * its address through dlsym(3), in this way multiple versions of libtcg c= an be + * used at the same time by initializing them and using the appropriate + * LibTCGInterface object. + * + * @param cpu_name: the name of the CPU to emulate. For a complete list in= voke + * the qemu-user binary (e.g., qemu-arm) with the -cpu help option. + * @param start_address: starting point for the guest address space, if in + * doubt, 0xb0000000 is usually a good value. + * + * @return an pointer to LibTCGInterface, which the caller can use to call= the + * other functions exposed by libtcg. + */ +typedef const LibTCGInterface *(*libtcg_init_func)(const char *cpu_name, + intptr_t start_address); + +#endif /* LIBTCG_H */ diff --git a/include/tcg-common.h b/include/tcg-common.h index 856c4974a0..86face7f8a 100644 --- a/include/tcg-common.h +++ b/include/tcg-common.h @@ -71,12 +71,15 @@ typedef enum PREFIX(Type) { #endif =20 /* An alias for the size of the target "long", aka register. */ +#ifdef TARGET_LONG_BITS #if TARGET_LONG_BITS =3D=3D 64 PREFIX2(TYPE_TL) =3D PREFIX2(TYPE_I64), #else PREFIX2(TYPE_TL) =3D PREFIX2(TYPE_I32), #endif #endif + +#endif } PREFIX(Type); =20 typedef struct PREFIX(Temp) { diff --git a/libtcg/Makefile.objs b/libtcg/Makefile.objs new file mode 100644 index 0000000000..b08a87d936 --- /dev/null +++ b/libtcg/Makefile.objs @@ -0,0 +1 @@ +obj-y +=3D libtcg.o diff --git a/libtcg/libtcg.c b/libtcg/libtcg.c new file mode 100644 index 0000000000..0b451c75ce --- /dev/null +++ b/libtcg/libtcg.c @@ -0,0 +1,226 @@ +#include "qemu/osdep.h" +#include +#include +#include "qemu.h" +#include "exec/exec-all.h" + +#include "libtcg.h" + +#define REINTERPRET(type, value) (*((type *) &(value))) + +/* Functions and global variables we need to provide */ +unsigned long guest_base; +int singlestep; +unsigned long mmap_min_addr; +unsigned long reserved_va; + +void cpu_resume(CPUState *cpu) +{ + abort(); +} + +bool qemu_cpu_is_self(CPUState *cpu) +{ + abort(); +} + +void qemu_cpu_kick(CPUState *cpu) +{ +} + +void qemu_init_vcpu(CPUState *cpu) +{ +} + +static CPUState *cpu; + +/* Interface functions */ +const LibTCGInterface *libtcg_init(const char *cpu_name, + intptr_t start_address); +static address_pair libtcg_mmap(uint64_t start, uint64_t len, int prot, + int flags, int fd, off_t offset); +static LibTCGInstructions libtcg_translate(uint64_t virtual_address); +static void libtcg_free_instructions(LibTCGInstructions *instructions); + +/* The interface object return by libtcg_init */ +static LibTCGInterface interface; + +/* This is the only function exposed by the library */ +__attribute__((visibility("default"))) +const LibTCGInterface *libtcg_init(const char *cpu_name, + intptr_t start_address) +{ + /* TODO: support changing CPU */ + assert(cpu =3D=3D NULL); + + /* Initialize guest_base. Since libtcg only translates buffers of code= , and + * doesn't have the full view over the program being translated as + * {linux,bsd}-user have, we let the user mmap the code. */ + assert(start_address <=3D UINT_MAX); + guest_base =3D (unsigned long) start_address; + + /* Initialize the TCG subsystem using the default translation buffer s= ize */ + tcg_exec_init(0); + + /* Initialize the QOM subsystem */ + module_call_init(MODULE_INIT_QOM); + + /* Initialize the CPU with the given name. This is a call to the + * cpu_*_init function */ + cpu =3D cpu_init(cpu_name); + assert(cpu !=3D NULL); + + /* Initialize the interface object */ + interface.mmap =3D libtcg_mmap; + interface.translate =3D libtcg_translate; + interface.free_instructions =3D libtcg_free_instructions; + + /* Return a reference to the interface object */ + return &interface; +} + +static address_pair libtcg_mmap(uint64_t start, uint64_t len, int prot, + int flags, int fd, off_t offset) +{ + address_pair result; + result.virtual_address =3D target_mmap(start, len, prot, flags, fd, of= fset); + result.pointer =3D g2h(result.virtual_address); + return result; +} + +static TranslationBlock *do_gen_code(TCGContext *context, CPUState *cpu, + target_ulong pc, target_ulong cs_base, + int flags, int cflags) +{ + CPUArchState *env =3D cpu->env_ptr; + + /* We don't care about caching translation blocks, flush out the cache= */ + tb_flush(cpu); + + /* Allocate a new translation block and get a pointer to it */ + TranslationBlock *tb =3D tb_alloc(pc); + + /* Configure translation options */ + tb->cs_base =3D cs_base; + tb->flags =3D flags; + tb->cflags =3D cflags; + + /* Clean the translation context */ + tcg_func_start(context); + + /* Invoke the frontend-specific gen_intermediate_code function to perf= orm + * the actual translation to tiny code instructions */ + gen_intermediate_code(env, tb); + + /* Return the TranslationBlock */ + return tb; +} + +static LibTCGInstructions libtcg_translate(uint64_t virtual_address) +{ + TCGContext *context =3D &tcg_ctx; + + /* Get the flags defining in which context the code was generated */ + target_ulong temp; + uint32_t flags =3D 0; + cpu_get_tb_cpu_state(cpu->env_ptr, &temp, &temp, &flags); + + /* Perform the translation forcing the pc and with cs_base and cflags = set to + * 0 */ + TranslationBlock *tb =3D do_gen_code(context, cpu, + (target_ulong) virtual_address, 0, = flags, + 0); + + LibTCGInstructions result; + unsigned arguments_count =3D 0; + + /* First, count the instructions and the arguments, so we can allocate= an + * appropriate amount of space */ + TCGOp *op =3D NULL; + for (unsigned i =3D context->gen_op_buf[0].next; i !=3D 0; i =3D op->n= ext) { + result.instruction_count++; + + op =3D &context->gen_op_buf[i]; + TCGOpcode c =3D op->opc; + const TCGOpDef *def =3D &tcg_op_defs[c]; + + if (c =3D=3D INDEX_op_insn_start) { + arguments_count +=3D 2; + } else if (c =3D=3D INDEX_op_call) { + arguments_count +=3D op->callo + op->calli + def->nb_cargs; + } else { + arguments_count +=3D def->nb_oargs + def->nb_iargs + def->nb_c= args; + } + } + + /* Allocate space for the instructions and arguments data structures */ + result.instructions =3D (LibTCGOp *) g_new0(LibTCGOp, + result.instruction_count); + result.arguments =3D (LibTCGArg *) g_new0(LibTCGArg, arguments_count); + + /* Copy the temp values */ + result.total_temps =3D context->nb_temps; + result.global_temps =3D context->nb_globals; + result.temps =3D (LibTCGTemp *) g_new0(LibTCGTemp, result.total_temps); + + for (unsigned i =3D 0; i < result.total_temps; i++) { + result.temps[i] =3D REINTERPRET(LibTCGTemp, context->temps[i]); + } + + /* Go through all the instructions again and copy to the output buffer= s */ + result.instruction_count =3D 0; + unsigned total_arguments_count =3D 0; + op =3D NULL; + for (unsigned i =3D context->gen_op_buf[0].next; i !=3D 0; i =3D op->n= ext) { + /* Get the pointer to the output LibTCGOp object */ + LibTCGOp *current_instruction =3D NULL; + current_instruction =3D &result.instructions[result.instruction_co= unt]; + result.instruction_count++; + + op =3D &context->gen_op_buf[i]; + TCGArg *args =3D &context->gen_opparam_buf[op->args]; + + current_instruction->opc =3D (LibTCGOpcode) op->opc; + current_instruction->callo =3D op->callo; + current_instruction->calli =3D op->calli; + current_instruction->args =3D &result.arguments[total_arguments_co= unt]; + + /* Compute the number of arguments for this instruction */ + TCGOpcode opcode =3D current_instruction->opc; + const TCGOpDef *def =3D &tcg_op_defs[opcode]; + unsigned arguments_count =3D 0; + if (opcode =3D=3D INDEX_op_insn_start) { + arguments_count =3D 2; + } else if (opcode =3D=3D INDEX_op_call) { + arguments_count +=3D current_instruction->callo; + arguments_count +=3D current_instruction->calli; + arguments_count +=3D def->nb_cargs; + } else { + arguments_count =3D def->nb_oargs + def->nb_iargs + def->nb_ca= rgs; + } + + /* Copy all the new arguments to the output buffer */ + for (unsigned j =3D 0; j < arguments_count; j++) { + LibTCGArg argument =3D REINTERPRET(LibTCGArg, args[j]); + result.arguments[total_arguments_count + j] =3D argument; + } + + /* Increment the counter of the total number of arguments */ + total_arguments_count +=3D arguments_count; + } + + /* Free the TranslationBlock */ + tb_free(tb); + + return result; +} + +void libtcg_free_instructions(LibTCGInstructions *instructions) +{ + assert(instructions !=3D NULL); + g_free(instructions->instructions); + g_free(instructions->arguments); + g_free(instructions->temps); +} + +#undef REINTERPRET diff --git a/libtcg/qemu.h b/libtcg/qemu.h new file mode 100644 index 0000000000..b32486959a --- /dev/null +++ b/libtcg/qemu.h @@ -0,0 +1,7 @@ +#ifndef QEMU_H +#define QEMU_H + +/* Everything we need is currently provided by qemu-user-common.h */ +#include "qemu-user-common.h" + +#endif /* QEMU_H */ diff --git a/qom/cpu.c b/qom/cpu.c index ed87c50cea..6e97e98b7c 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -386,7 +386,9 @@ static void cpu_common_initfn(Object *obj) QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); =20 - cpu->trace_dstate =3D bitmap_new(trace_get_vcpu_event_count()); + uint32_t event_count =3D trace_get_vcpu_event_count(); + if (event_count > 0) + cpu->trace_dstate =3D bitmap_new(event_count); =20 cpu_exec_initfn(cpu); } diff --git a/target/alpha/Makefile.objs b/target/alpha/Makefile.objs index 63664629f6..476edf1b60 100644 --- a/target/alpha/Makefile.objs +++ b/target/alpha/Makefile.objs @@ -1,4 +1,8 @@ +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D machine.o -obj-y +=3D translate.o helper.o cpu.o -obj-y +=3D int_helper.o fpu_helper.o vax_helper.o sys_helper.o mem_helper.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o int_helper.o fpu_helper.o vax_helper.o sys_helper.o me= m_helper.o obj-y +=3D gdbstub.o +endif diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index a1125fca93..9e57be75e0 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -336,12 +336,14 @@ static void alpha_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->class_by_name =3D alpha_cpu_class_by_name; cc->has_work =3D alpha_cpu_has_work; + cc->set_pc =3D alpha_cpu_set_pc; +#ifndef CONFIG_LIBTCG cc->do_interrupt =3D alpha_cpu_do_interrupt; cc->cpu_exec_interrupt =3D alpha_cpu_exec_interrupt; cc->dump_state =3D alpha_cpu_dump_state; - cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D alpha_cpu_handle_mmu_fault; #else @@ -350,6 +352,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; #endif + +#endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 67; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index df06591997..92c011f597 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3026,6 +3026,7 @@ void restore_state_to_opc(CPUAlphaState *env, Transla= tionBlock *tb, env->pc =3D data[0]; } =20 +#ifndef CONFIG_LIBTCG void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, int flags) { @@ -3059,3 +3060,4 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, } cpu_fprintf(f, "\n"); } +#endif diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 82898a6a68..b7957fc3ce 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -1,12 +1,21 @@ -obj-y +=3D arm-semi.o +obj-y +=3D translate.o cpu.o coprocessors.o +obj-$(TARGET_AARCH64) +=3D translate-a64.o +obj-$(TARGET_AARCH64) +=3D cpu64.o + obj-$(CONFIG_SOFTMMU) +=3D machine.o psci.o arch_dump.o monitor.o +obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o obj-$(CONFIG_KVM) +=3D kvm.o obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) +=3D kvm32.o obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) +=3D kvm64.o + +ifndef CONFIG_LIBTCG + +obj-y +=3D helper.o op_helper.o neon_helper.o iwmmxt_helper.o crypto_helpe= r.o +obj-$(TARGET_AARCH64) +=3D helper-a64.o + +obj-y +=3D arm-semi.o obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o -obj-y +=3D translate.o op_helper.o helper.o coprocessors.o cpu.o -obj-y +=3D neon_helper.o iwmmxt_helper.o + obj-y +=3D gdbstub.o -obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o -obj-y +=3D crypto_helper.o -obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o +obj-$(TARGET_AARCH64) +=3D gdbstub64.o +endif diff --git a/target/arm/coprocessors.c b/target/arm/coprocessors.c index c2819f7ea2..53d99f220f 100644 --- a/target/arm/coprocessors.c +++ b/target/arm/coprocessors.c @@ -16,6 +16,7 @@ #define PMCRE 0x1 #endif =20 +#ifndef CONFIG_LIBTCG static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; @@ -109,6 +110,7 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, ui= nt8_t *buf, int reg) return 0; } } +#endif =20 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -169,6 +171,7 @@ static void write_raw_cp_reg(CPUARMState *env, const AR= MCPRegInfo *ri, } } =20 +#ifndef CONFIG_LIBTCG static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* Return true if the regdef would cause an assertion if you called @@ -189,6 +192,7 @@ static bool raw_accessors_invalid(const ARMCPRegInfo *r= i) } return true; } +#endif =20 bool write_cpustate_to_list(ARMCPU *cpu) { @@ -5225,6 +5229,7 @@ ARMCPU *cpu_arm_init(const char *cpu_model) return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); } =20 +#ifndef CONFIG_LIBTCG void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) { CPUState *cs =3D CPU(cpu); @@ -5245,6 +5250,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) 19, "arm-vfp.xml", 0); } } +#endif =20 /* Sort alphabetically by type name, except for "any". */ static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) @@ -5437,6 +5443,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS; } =20 +#ifndef CONFIG_LIBTCG /* Check that raw accesses are either forbidden or handled. Note that * we can't assert this earlier because the setup of fieldoffset for * banked registers has to be done first. @@ -5444,6 +5451,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, if (!(r2->type & ARM_CP_NO_RAW)) { assert(!raw_accessors_invalid(r2)); } +#endif =20 /* Overriding of an existing definition must be explicitly * requested. @@ -5545,6 +5553,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, assert((r->access & ~mask) =3D=3D 0); } =20 +#ifndef CONFIG_LIBTCG /* Check that the register definition has enough info to handle * reads and writes if they are permitted. */ @@ -5560,6 +5569,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, r->writefn); } } +#endif /* Bad type field probably means missing sentinel at end of reg list */ assert(cptype_valid(r->type)); for (crm =3D crmmin; crm <=3D crmmax; crm++) { @@ -5629,6 +5639,7 @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMC= PRegInfo *opaque) /* Helper coprocessor reset function for do-nothing-on-reset registers= */ } =20 +#ifndef CONFIG_LIBTCG static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) { /* Return true if it is not valid for us to switch to @@ -5800,3 +5811,4 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, mask &=3D ~CACHED_CPSR_BITS; env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); } +#endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4a069f6985..be0a8fd04a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -249,6 +249,15 @@ static void arm_cpu_reset(CPUState *s) hw_watchpoint_update_all(cpu); } =20 +#ifdef CONFIG_LIBTCG + +bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + abort(); +} + +#else + bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -302,6 +311,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) =20 return ret; } +#endif =20 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) static void arm_v7m_unassigned_access(CPUState *cpu, hwaddr addr, @@ -820,7 +830,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) } =20 register_cp_regs_for_features(cpu); +#ifndef CONFIG_LIBTCG arm_cpu_register_gdb_regs_for_features(cpu); +#endif =20 init_cpreg_list(cpu); =20 @@ -1653,10 +1665,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void= *data) cc->class_by_name =3D arm_cpu_class_by_name; cc->has_work =3D arm_cpu_has_work; cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; - cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; - cc->gdb_read_register =3D arm_cpu_gdb_read_register; - cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D arm_cpu_handle_mmu_fault; #else @@ -1673,8 +1682,13 @@ static void arm_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_core_xml_file =3D "arm-core.xml"; cc->gdb_arch_name =3D arm_gdb_arch_name; cc->gdb_stop_before_watchpoint =3D true; +#ifndef CONFIG_LIBTCG + cc->dump_state =3D arm_cpu_dump_state; cc->debug_excp_handler =3D arm_debug_excp_handler; + cc->gdb_read_register =3D arm_cpu_gdb_read_register; + cc->gdb_write_register =3D arm_cpu_gdb_write_register; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; +#endif #if !defined(CONFIG_USER_ONLY) cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6e..fbf018d522 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -313,8 +313,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->set_pc =3D aarch64_cpu_set_pc; +#ifndef CONFIG_LIBTCG cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; +#endif cc->gdb_num_core_regs =3D 34; cc->gdb_core_xml_file =3D "aarch64-core.xml"; cc->gdb_arch_name =3D aarch64_gdb_arch_name; diff --git a/target/arm/translate.c b/target/arm/translate.c index 495f967eb6..990d44b257 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12085,6 +12085,7 @@ done_generating: tb->icount =3D num_insns; } =20 +#ifndef CONFIG_LIBTCG static const char *cpu_mode_names[16] =3D { "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", "???", "???", "hyp", "und", "???", "???", "???", "sys" @@ -12148,6 +12149,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]= ); } } +#endif =20 void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, target_ulong *data) diff --git a/target/cris/Makefile.objs b/target/cris/Makefile.objs index 7779227fc4..ec06586d23 100644 --- a/target/cris/Makefile.objs +++ b/target/cris/Makefile.objs @@ -1,3 +1,8 @@ -obj-y +=3D translate.o op_helper.o helper.o cpu.o -obj-y +=3D gdbstub.o +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D mmu.o machine.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o +obj-y +=3D gdbstub.o +endif diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 5f766f09d6..d3152a0cc9 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -213,52 +213,62 @@ static void cris_cpu_initfn(Object *obj) =20 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) { - CPUClass *cc =3D CPU_CLASS(oc); CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 8; +#ifndef CONFIG_LIBTCG + CPUClass *cc =3D CPU_CLASS(oc); cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; +#endif } =20 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) { - CPUClass *cc =3D CPU_CLASS(oc); CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 9; +#ifndef CONFIG_LIBTCG + CPUClass *cc =3D CPU_CLASS(oc); cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; +#endif } =20 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) { - CPUClass *cc =3D CPU_CLASS(oc); CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 10; +#ifndef CONFIG_LIBTCG + CPUClass *cc =3D CPU_CLASS(oc); cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; +#endif } =20 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) { - CPUClass *cc =3D CPU_CLASS(oc); CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 11; +#ifndef CONFIG_LIBTCG + CPUClass *cc =3D CPU_CLASS(oc); cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; +#endif } =20 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) { - CPUClass *cc =3D CPU_CLASS(oc); CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 17; +#ifndef CONFIG_LIBTCG + CPUClass *cc =3D CPU_CLASS(oc); cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; +#endif } =20 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) @@ -314,12 +324,14 @@ static void cris_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; + cc->set_pc =3D cris_cpu_set_pc; +#ifndef CONFIG_LIBTCG + cc->dump_state =3D cris_cpu_dump_state; cc->do_interrupt =3D cris_cpu_do_interrupt; cc->cpu_exec_interrupt =3D cris_cpu_exec_interrupt; - cc->dump_state =3D cris_cpu_dump_state; - cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D cris_cpu_handle_mmu_fault; #else @@ -327,6 +339,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) dc->vmsd =3D &vmstate_cris_cpu; #endif =20 +#endif + cc->gdb_num_core_regs =3D 49; cc->gdb_stop_before_watchpoint =3D true; =20 diff --git a/target/cris/translate.c b/target/cris/translate.c index 0ee05ca02d..8274fd8186 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3303,6 +3303,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) #endif } =20 +#ifndef CONFIG_LIBTCG void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprin= tf, int flags) { @@ -3359,6 +3360,7 @@ void cris_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, cpu_fprintf(f, "\n\n"); =20 } +#endif =20 void cris_initialize_tcg(void) { diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index 263446fa0b..d06e1b6bba 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1 +1,5 @@ -obj-y +=3D translate.o helper.o cpu.o op_helper.o gdbstub.o +obj-y +=3D translate.o cpu.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o gdbstub.o +endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 1d791d0f80..2e74a15fa9 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -107,7 +107,9 @@ static void hppa_cpu_initfn(Object *obj) CPUHPPAState *env =3D &cpu->env; =20 cs->env_ptr =3D env; +#ifndef CONFIG_LIBTCG cpu_hppa_loaded_fr0(env); +#endif set_snan_bit_is_one(true, &env->fp_status); =20 hppa_translate_init(); @@ -133,14 +135,16 @@ static void hppa_cpu_class_init(ObjectClass *oc, void= *data) acc->parent_realize =3D dc->realize; dc->realize =3D hppa_cpu_realizefn; =20 +#ifndef CONFIG_LIBTCG cc->do_interrupt =3D hppa_cpu_do_interrupt; cc->cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; - cc->set_pc =3D hppa_cpu_set_pc; - cc->synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; + cc->handle_mmu_fault =3D hppa_cpu_handle_mmu_fault; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; - cc->handle_mmu_fault =3D hppa_cpu_handle_mmu_fault; +#endif + cc->set_pc =3D hppa_cpu_set_pc; + cc->synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->disas_set_info =3D hppa_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 128; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5eeb35abc3..7b0c0d88f1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3938,6 +3938,7 @@ void restore_state_to_opc(CPUHPPAState *env, Translat= ionBlock *tb, env->psw_n =3D 0; } =20 +#ifndef CONFIG_LIBTCG void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -3962,3 +3963,4 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, =20 /* ??? FR */ } +#endif diff --git a/target/i386/Makefile.objs b/target/i386/Makefile.objs index 4fcb7f3df0..8201ed5470 100644 --- a/target/i386/Makefile.objs +++ b/target/i386/Makefile.objs @@ -1,10 +1,15 @@ -obj-y +=3D translate.o helper.o cpu.o bpt_helper.o -obj-y +=3D excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o -obj-y +=3D smm_helper.o misc_helper.o mem_helper.o seg_helper.o mpx_helper= .o -obj-y +=3D gdbstub.o +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D machine.o arch_memory_mapping.o arch_dump.o mon= itor.o obj-$(CONFIG_KVM) +=3D kvm.o hyperv.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o bpt_helper.o int_helper.o misc_helper.o mem_helper.o \ + excp_helper.o fpu_helper.o cc_helper.o svm_helper.o smm_helper.o \ + seg_helper.o mpx_helper.o obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o +obj-y +=3D gdbstub.o + # HAX support ifdef CONFIG_WIN32 obj-$(CONFIG_HAX) +=3D hax-all.o hax-mem.o hax-windows.o @@ -12,3 +17,5 @@ endif ifdef CONFIG_DARWIN obj-$(CONFIG_HAX) +=3D hax-all.o hax-mem.o hax-darwin.o endif + +endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fd7add2521..88b2fa05f8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2807,7 +2807,9 @@ static void x86_cpu_reset(CPUState *s) =20 env->hflags2 |=3D HF2_GIF_MASK; =20 +#ifndef CONFIG_LIBTCG cpu_x86_update_cr0(env, 0x60000010); +#endif env->a20_mask =3D ~0x0; env->smbase =3D 0x30000; =20 @@ -2846,7 +2848,9 @@ static void x86_cpu_reset(CPUState *s) for (i =3D 0; i < 8; i++) { env->fptags[i] =3D 1; } +#ifndef CONFIG_LIBTCG cpu_set_fpuc(env, 0x37f); +#endif =20 env->mxcsr =3D 0x1f80; /* All units are in INIT state. */ @@ -2885,7 +2889,9 @@ static void x86_cpu_reset(CPUState *s) #endif =20 env->xcr0 =3D xcr0; +#ifndef CONFIG_LIBTCG cpu_x86_update_cr4(env, cr4); +#endif =20 /* * SDM 11.11.5 requires: @@ -3731,16 +3737,20 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; - cc->do_interrupt =3D x86_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; - cc->dump_state =3D x86_cpu_dump_state; cc->get_crash_info =3D x86_cpu_get_crash_info; cc->set_pc =3D x86_cpu_set_pc; cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; - cc->gdb_read_register =3D x86_cpu_gdb_read_register; - cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; +#ifndef CONFIG_LIBTCG + cc->dump_state =3D x86_cpu_dump_state; + cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; + cc->gdb_read_register =3D x86_cpu_gdb_read_register; + cc->gdb_write_register =3D x86_cpu_gdb_write_register; + cc->cpu_exec_enter =3D x86_cpu_exec_enter; + cc->cpu_exec_exit =3D x86_cpu_exec_exit; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D x86_cpu_handle_mmu_fault; #else @@ -3752,6 +3762,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->vmsd =3D &vmstate_x86_cpu; #endif + +#endif /* CPU_NB_REGS * 2 =3D general regs + xmm regs * 25 =3D eip, eflags, 6 seg regs, st[0-7], fctrl,...,fop, mxcsr. */ @@ -3759,8 +3771,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) #ifndef CONFIG_USER_ONLY cc->debug_excp_handler =3D breakpoint_handler; #endif - cc->cpu_exec_enter =3D x86_cpu_exec_enter; - cc->cpu_exec_exit =3D x86_cpu_exec_exit; =20 dc->cannot_instantiate_with_device_add_yet =3D false; } diff --git a/target/i386/translate.c b/target/i386/translate.c index 5623ee65a6..7111242c78 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8527,6 +8527,7 @@ void restore_state_to_opc(CPUX86State *env, Translati= onBlock *tb, } } =20 +#ifndef CONFIG_LIBTCG /***********************************************************/ /* x86 debug */ =20 @@ -8849,3 +8850,4 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, cpu_fprintf(f, "\n"); } } +#endif diff --git a/target/lm32/Makefile.objs b/target/lm32/Makefile.objs index c3e1bd6bd6..2d00071430 100644 --- a/target/lm32/Makefile.objs +++ b/target/lm32/Makefile.objs @@ -1,4 +1,9 @@ -obj-y +=3D translate.o op_helper.o helper.o cpu.o -obj-y +=3D gdbstub.o -obj-y +=3D lm32-semi.o +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D machine.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o +obj-y +=3D lm32-semi.o +obj-y +=3D gdbstub.o +endif diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 692882f447..2cfed2f893 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1158,6 +1158,7 @@ void gen_intermediate_code(CPULM32State *env, struct = TranslationBlock *tb) #endif } =20 +#ifndef CONFIG_LIBTCG void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprin= tf, int flags) { @@ -1191,6 +1192,7 @@ void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, } cpu_fprintf(f, "\n\n"); } +#endif =20 void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, target_ulong *data) diff --git a/target/m68k/Makefile.objs b/target/m68k/Makefile.objs index 02cf616a78..9d8ca84220 100644 --- a/target/m68k/Makefile.objs +++ b/target/m68k/Makefile.objs @@ -1,3 +1,7 @@ +obj-y +=3D translate.o cpu.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o obj-y +=3D m68k-semi.o -obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-y +=3D gdbstub.o +endif diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 3b00d00461..7434eb097d 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -258,7 +258,6 @@ static const M68kCPUInfo m68k_cpus[] =3D { static void m68k_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); - M68kCPU *cpu =3D M68K_CPU(dev); M68kCPUClass *mcc =3D M68K_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 @@ -268,7 +267,10 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error= **errp) return; } =20 +#ifndef CONFIG_LIBTCG + M68kCPU *cpu =3D M68K_CPU(dev); m68k_cpu_init_gdb(cpu); +#endif =20 cpu_reset(cs); qemu_init_vcpu(cs); @@ -330,17 +332,21 @@ static void m68k_cpu_class_init(ObjectClass *c, void = *data) =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; + cc->set_pc =3D m68k_cpu_set_pc; +#ifndef CONFIG_LIBTCG + cc->dump_state =3D m68k_cpu_dump_state; cc->do_interrupt =3D m68k_cpu_do_interrupt; cc->cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; - cc->dump_state =3D m68k_cpu_dump_state; - cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D m68k_cpu_handle_mmu_fault; #else cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; #endif + +#endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 18; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 9f60fbc0db..c1b5bc7a27 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5136,6 +5136,7 @@ void gen_intermediate_code(CPUM68KState *env, Transla= tionBlock *tb) tb->icount =3D num_insns; } =20 +#ifndef CONFIG_LIBTCG void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprin= tf, int flags) { @@ -5158,6 +5159,7 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); cpu_fprintf (f, "FPRESULT =3D %12g\n", *(double *)&env->fp_result); } +#endif =20 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, target_ulong *data) diff --git a/target/microblaze/Makefile.objs b/target/microblaze/Makefile.o= bjs index f3d7b44c89..ba4efbe606 100644 --- a/target/microblaze/Makefile.objs +++ b/target/microblaze/Makefile.objs @@ -1,3 +1,8 @@ -obj-y +=3D translate.o op_helper.o helper.o cpu.o -obj-y +=3D gdbstub.o +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D mmu.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o +obj-y +=3D gdbstub.o +endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 3d58869716..5719fe4ee9 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -255,18 +255,22 @@ static void mb_cpu_class_init(ObjectClass *oc, void *= data) cc->reset =3D mb_cpu_reset; =20 cc->has_work =3D mb_cpu_has_work; +#ifndef CONFIG_LIBTCG cc->do_interrupt =3D mb_cpu_do_interrupt; cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; - cc->set_pc =3D mb_cpu_set_pc; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D mb_cpu_handle_mmu_fault; #else cc->do_unassigned_access =3D mb_cpu_unassigned_access; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; #endif + +#endif + cc->set_pc =3D mb_cpu_set_pc; dc->vmsd =3D &vmstate_mb_cpu; dc->props =3D mb_properties; cc->gdb_num_core_regs =3D 32 + 5; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0bb609513c..4837d64d53 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1784,6 +1784,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) assert(!dc->abort_at_next_insn); } =20 +#ifndef CONFIG_LIBTCG void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -1813,6 +1814,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf= _function cpu_fprintf, } cpu_fprintf(f, "\n\n"); } +#endif =20 MicroBlazeCPU *cpu_mb_init(const char *cpu_model) { diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs index bc5ed8511f..1c0ae09d4e 100644 --- a/target/mips/Makefile.objs +++ b/target/mips/Makefile.objs @@ -1,4 +1,10 @@ -obj-y +=3D translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o -obj-y +=3D gdbstub.o msa_helper.o mips-semi.o +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D machine.o obj-$(CONFIG_KVM) +=3D kvm.o + +ifndef CONFIG_LIBTCG +obj-y +=3D dsp_helper.o op_helper.o lmi_helper.o helper.o msa_helper.o +obj-y +=3D mips-semi.o +obj-y +=3D gdbstub.o +endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1bb66b7a5a..e0fcb60eb1 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -163,11 +163,12 @@ static void mips_cpu_class_init(ObjectClass *c, void = *data) cc->reset =3D mips_cpu_reset; =20 cc->has_work =3D mips_cpu_has_work; - cc->do_interrupt =3D mips_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; - cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->synchronize_from_tb =3D mips_cpu_synchronize_from_tb; +#ifndef CONFIG_LIBTCG + cc->dump_state =3D mips_cpu_dump_state; + cc->do_interrupt =3D mips_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifdef CONFIG_USER_ONLY @@ -178,6 +179,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; #endif +#endif cc->disas_set_info =3D mips_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 73; diff --git a/target/mips/translate.c b/target/mips/translate.c index 5077099a78..9cc609a03f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20071,6 +20071,7 @@ done_generating: #endif } =20 +#ifndef CONFIG_LIBTCG static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fp= u_fprintf, int flags) { @@ -20143,6 +20144,7 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fpr= intf_function cpu_fprintf, if (env->hflags & MIPS_HFLAG_FPU) fpu_dump_state(env, f, cpu_fprintf, flags); } +#endif =20 void mips_tcg_init(void) { diff --git a/target/moxie/Makefile.objs b/target/moxie/Makefile.objs index 6381d4d636..095992c742 100644 --- a/target/moxie/Makefile.objs +++ b/target/moxie/Makefile.objs @@ -1,2 +1,8 @@ -obj-y +=3D translate.o helper.o machine.o cpu.o machine.o +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D mmu.o + +ifndef CONFIG_LIBTCG +obj-y +=3D machine.o +obj-y +=3D helper.o +endif diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 0660b44c08..28930c4d5e 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -70,6 +70,7 @@ static int extract_branch_offset(int opcode) return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1; } =20 +#ifndef CONFIG_LIBTCG void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, int flags) { @@ -90,6 +91,7 @@ void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_= function cpu_fprintf, i, env->sregs[i + 2], i+1, env->sregs[i + 3]); } } +#endif =20 void moxie_translate_init(void) { diff --git a/target/nios2/Makefile.objs b/target/nios2/Makefile.objs index 2a11c5ce08..d50466788d 100644 --- a/target/nios2/Makefile.objs +++ b/target/nios2/Makefile.objs @@ -1,4 +1,8 @@ -obj-y +=3D translate.o op_helper.o helper.o cpu.o mmu.o +obj-y +=3D translate.o cpu.o obj-$(CONFIG_SOFTMMU) +=3D monitor.o =20 +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o +obj-y +=3D mmu.o $(obj)/op_helper.o: QEMU_CFLAGS +=3D $(HELPER_CFLAGS) +endif \ No newline at end of file diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index d56bb7245a..03e1809c05 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -110,6 +110,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error= **errp) ncc->parent_realize(dev, errp); } =20 +#ifndef CONFIG_LIBTCG static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { Nios2CPU *cpu =3D NIOS2_CPU(cs); @@ -123,6 +124,7 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) } return false; } +#endif =20 =20 static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) @@ -136,6 +138,7 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, dis= assemble_info *info) #endif } =20 +#ifndef CONFIG_LIBTCG static int nios2_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int= n) { Nios2CPU *cpu =3D NIOS2_CPU(cs); @@ -178,6 +181,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, u= int8_t *mem_buf, int n) =20 return 4; } +#endif =20 static Property nios2_properties[] =3D { DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true), @@ -204,19 +208,22 @@ static void nios2_cpu_class_init(ObjectClass *oc, voi= d *data) cc->reset =3D nios2_cpu_reset; =20 cc->has_work =3D nios2_cpu_has_work; - cc->do_interrupt =3D nios2_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; - cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; +#ifndef CONFIG_LIBTCG + cc->do_interrupt =3D nios2_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; + cc->gdb_read_register =3D nios2_cpu_gdb_read_register; + cc->gdb_write_register =3D nios2_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D nios2_cpu_handle_mmu_fault; #else cc->do_unaligned_access =3D nios2_cpu_do_unaligned_access; cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; #endif - cc->gdb_read_register =3D nios2_cpu_gdb_read_register; - cc->gdb_write_register =3D nios2_cpu_gdb_write_register; + +#endif cc->gdb_num_core_regs =3D 49; } =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2d738391ad..c0fd3df689 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -909,6 +909,7 @@ void gen_intermediate_code(CPUNios2State *env, Translat= ionBlock *tb) #endif } =20 +#ifndef CONFIG_LIBTCG void nios2_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, int flags) { @@ -937,6 +938,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, #endif cpu_fprintf(f, "\n\n"); } +#endif =20 void nios2_tcg_init(void) { diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index 918b1c6e9c..2b1656dccb 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -1,5 +1,10 @@ +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D machine.o -obj-y +=3D cpu.o exception.o interrupt.o mmu.o translate.o -obj-y +=3D exception_helper.o fpu_helper.o \ - interrupt_helper.o mmu_helper.o sys_helper.o + +ifndef CONFIG_LIBTCG +obj-y +=3D exception.o interrupt.o mmu.o +obj-y +=3D exception_helper.o fpu_helper.o interrupt_helper.o \ + mmu_helper.o sys_helper.o obj-y +=3D gdbstub.o +endif diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a216..ba96f1cf8c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -167,18 +167,23 @@ static void openrisc_cpu_class_init(ObjectClass *oc, = void *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; + cc->set_pc =3D openrisc_cpu_set_pc; +#ifndef CONFIG_LIBTCG cc->do_interrupt =3D openrisc_cpu_do_interrupt; cc->cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; - cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D openrisc_cpu_handle_mmu_fault; #else cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; #endif + +#endif + cc->gdb_num_core_regs =3D 32 + 3; } =20 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c4cbf205f..b4b1913afd 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1652,6 +1652,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) } } =20 +#ifndef CONFIG_LIBTCG void openrisc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) @@ -1666,6 +1667,7 @@ void openrisc_cpu_dump_state(CPUState *cs, FILE *f, (i % 4) =3D=3D 3 ? '\n' : ' '); } } +#endif =20 void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb, target_ulong *data) diff --git a/target/ppc/Makefile.objs b/target/ppc/Makefile.objs index a8c7a30cde..54b6e4b2a7 100644 --- a/target/ppc/Makefile.objs +++ b/target/ppc/Makefile.objs @@ -1,17 +1,18 @@ -obj-y +=3D cpu-models.o obj-y +=3D translate.o +obj-y +=3D cpu-models.o + ifeq ($(CONFIG_SOFTMMU),y) -obj-y +=3D machine.o mmu_helper.o mmu-hash32.o monitor.o +obj-y +=3D machine.o mmu-hash32.o monitor.o +obj-y +=3D mmu_helper.o obj-$(TARGET_PPC64) +=3D mmu-hash64.o arch_dump.o compat.o endif + obj-$(CONFIG_KVM) +=3D kvm.o obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o -obj-y +=3D dfp_helper.o -obj-y +=3D excp_helper.o -obj-y +=3D fpu_helper.o -obj-y +=3D int_helper.o -obj-y +=3D timebase_helper.o -obj-y +=3D misc_helper.o -obj-y +=3D mem_helper.o + +ifndef CONFIG_LIBTCG +obj-y +=3D int_helper.o dfp_helper.o timebase_helper.o mem_helper.o \ + misc_helper.o fpu_helper.o excp_helper.o obj-$(CONFIG_USER_ONLY) +=3D user_only_helper.o obj-y +=3D gdbstub.o +endif diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3ba2616b8a..2393031069 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6863,6 +6863,7 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F= , 0x03FFF800, \ #include "helper_regs.h" #include "translate_init.c" =20 +#ifndef CONFIG_LIBTCG /*************************************************************************= ****/ /* Misc PowerPC helpers */ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprint= f, @@ -7032,6 +7033,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, #undef RGPL #undef RFPL } +#endif =20 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, fprintf_function cpu_fprintf, int flags) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 12ef379d50..fede933461 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -9449,6 +9449,7 @@ static void dump_ppc_insns (CPUPPCState *env) } #endif =20 +#ifndef CONFIG_LIBTCG static bool avr_need_swap(CPUPPCState *env) { #ifdef HOST_WORDS_BIGENDIAN @@ -9634,6 +9635,7 @@ static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t = *mem_buf, int n) } return 0; } +#endif =20 static int ppc_fixup_cpu(PowerPCCPU *cpu) { @@ -9736,6 +9738,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error= **errp) } init_ppc_proc(cpu); =20 +#ifndef CONFIG_LIBTCG if (pcc->insns_flags & PPC_FLOAT) { gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, 33, "power-fpu.xml", 0); @@ -9752,6 +9755,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error= **errp) gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, 32, "power-vsx.xml", 0); } +#endif =20 qemu_init_vcpu(cs); =20 @@ -10497,11 +10501,12 @@ static void ppc_cpu_class_init(ObjectClass *oc, v= oid *data) =20 cc->class_by_name =3D ppc_cpu_class_by_name; cc->has_work =3D ppc_cpu_has_work; + cc->dump_statistics =3D ppc_cpu_dump_statistics; + cc->set_pc =3D ppc_cpu_set_pc; +#ifndef CONFIG_LIBTCG cc->do_interrupt =3D ppc_cpu_do_interrupt; cc->cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; cc->dump_state =3D ppc_cpu_dump_state; - cc->dump_statistics =3D ppc_cpu_dump_statistics; - cc->set_pc =3D ppc_cpu_set_pc; cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifdef CONFIG_USER_ONLY @@ -10511,8 +10516,11 @@ static void ppc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->vmsd =3D &vmstate_ppc_cpu; #if defined(TARGET_PPC64) cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; -#endif -#endif +#endif /* TARGET_PPC64 */ +#endif /* CONFIG_USER_ONLY */ + +#endif /* CONFIG_LIBTCG */ + cc->cpu_exec_enter =3D ppc_cpu_exec_enter; =20 cc->gdb_num_core_regs =3D 71; diff --git a/target/s390x/Makefile.objs b/target/s390x/Makefile.objs index c573633bd1..b0aa2d563f 100644 --- a/target/s390x/Makefile.objs +++ b/target/s390x/Makefile.objs @@ -1,9 +1,17 @@ -obj-y +=3D translate.o helper.o cpu.o interrupt.o -obj-y +=3D int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o -obj-y +=3D gdbstub.o cpu_models.o cpu_features.o -obj-$(CONFIG_SOFTMMU) +=3D machine.o ioinst.o arch_dump.o mmu_helper.o +obj-y +=3D translate.o cpu.o +obj-y +=3D cpu_models.o cpu_features.o + +obj-$(CONFIG_SOFTMMU) +=3D machine.o ioinst.o arch_dump.o +obj-$(CONFIG_SOFTMMU) +=3D mmu_helper.o obj-$(CONFIG_KVM) +=3D kvm.o =20 +ifndef CONFIG_LIBTCG +obj-y +=3D interrupt.o +obj-y +=3D helper.o int_helper.o fpu_helper.o cc_helper.o mem_helper.o \ + misc_helper.o +obj-y +=3D gdbstub.o +endif + # build and run feature list generator feat-src =3D $(SRC_PATH)/target/$(TARGET_BASE_ARCH)/ feat-dst =3D $(BUILD_DIR)/$(TARGET_DIR) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 2101d1dbf1..e402504cd4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -214,7 +214,9 @@ static void s390_cpu_realizefn(DeviceState *dev, Error = **errp) qemu_register_reset(s390_cpu_machine_reset_cb, cpu); #endif env->cpu_num =3D cpu->id; +#ifndef CONFIG_LIBTCG s390_cpu_gdb_init(cs); +#endif qemu_init_vcpu(cs); #if !defined(CONFIG_USER_ONLY) run_on_cpu(cs, s390_do_cpu_full_reset, RUN_ON_CPU_NULL); @@ -417,11 +419,13 @@ static void s390_cpu_class_init(ObjectClass *oc, void= *data) cc->reset =3D s390_cpu_full_reset; cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; + cc->set_pc =3D s390_cpu_set_pc; +#ifndef CONFIG_LIBTCG cc->do_interrupt =3D s390_cpu_do_interrupt; cc->dump_state =3D s390_cpu_dump_state; - cc->set_pc =3D s390_cpu_set_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D s390_cpu_handle_mmu_fault; #else @@ -431,6 +435,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->cpu_exec_interrupt =3D s390_cpu_exec_interrupt; cc->debug_excp_handler =3D s390x_cpu_debug_excp_handler; #endif + +#endif cc->disas_set_info =3D s390_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 01c62176bf..08b5e2db23 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -91,6 +91,7 @@ static uint64_t pc_to_link_info(DisasContext *s, uint64_t= pc) return pc; } =20 +#ifndef CONFIG_LIBTCG void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprin= tf, int flags) { @@ -150,6 +151,7 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf= _function cpu_fprintf, =20 cpu_fprintf(f, "\n"); } +#endif =20 static TCGv_i64 psw_addr; static TCGv_i64 psw_mask; diff --git a/target/sh4/Makefile.objs b/target/sh4/Makefile.objs index 2c25d96e65..381e4ed899 100644 --- a/target/sh4/Makefile.objs +++ b/target/sh4/Makefile.objs @@ -1,3 +1,8 @@ -obj-y +=3D translate.o op_helper.o helper.o cpu.o +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D monitor.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o obj-y +=3D gdbstub.o +endif diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 9a481c35dc..e3849eae17 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -291,18 +291,22 @@ static void superh_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; - cc->do_interrupt =3D superh_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D superh_cpu_exec_interrupt; - cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; cc->synchronize_from_tb =3D superh_cpu_synchronize_from_tb; +#ifndef CONFIG_LIBTCG + cc->dump_state =3D superh_cpu_dump_state; + cc->do_interrupt =3D superh_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D superh_cpu_handle_mmu_fault; #else cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif + +#endif cc->disas_set_info =3D superh_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 59; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index c89a14733f..0d4cbbda12 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -157,6 +157,7 @@ void sh4_translate_init(void) done_init =3D 1; } =20 +#ifndef CONFIG_LIBTCG void superh_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -182,6 +183,7 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, env->delayed_pc); } } +#endif =20 static void gen_read_sr(TCGv dst) { diff --git a/target/sparc/Makefile.objs b/target/sparc/Makefile.objs index ec905698c5..dbf04188f3 100644 --- a/target/sparc/Makefile.objs +++ b/target/sparc/Makefile.objs @@ -1,7 +1,12 @@ +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D machine.o monitor.o -obj-y +=3D translate.o helper.o cpu.o -obj-y +=3D fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o fop_helper.o cc_helper.o win_helper.o mmu_helper.o \ + ldst_helper.o obj-$(TARGET_SPARC) +=3D int32_helper.o -obj-$(TARGET_SPARC64) +=3D int64_helper.o -obj-$(TARGET_SPARC64) +=3D vis_helper.o +obj-$(TARGET_SPARC64) +=3D int64_helper.o vis_helper.o + obj-y +=3D gdbstub.o +endif diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 652cbef425..bbd2aa6c77 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -76,6 +76,7 @@ static void sparc_cpu_reset(CPUState *s) env->cache_control =3D 0; } =20 +#ifndef CONFIG_LIBTCG static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { @@ -95,6 +96,7 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int in= terrupt_request) } return false; } +#endif =20 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) { @@ -770,16 +772,18 @@ static void sparc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->reset =3D sparc_cpu_reset; =20 cc->has_work =3D sparc_cpu_has_work; - cc->do_interrupt =3D sparc_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; - cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; #endif cc->set_pc =3D sparc_cpu_set_pc; cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; +#ifndef CONFIG_LIBTCG + cc->dump_state =3D sparc_cpu_dump_state; + cc->do_interrupt =3D sparc_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D sparc_cpu_handle_mmu_fault; #else @@ -788,6 +792,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; #endif + +#endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 248ff9018d..10f05bef1a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5965,6 +5965,7 @@ void restore_state_to_opc(CPUSPARCState *env, Transla= tionBlock *tb, } } =20 +#ifndef CONFIG_LIBTCG static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf, uint32_t cc) { @@ -6049,3 +6050,4 @@ void sparc_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, #endif cpu_fprintf(f, "\n"); } +#endif diff --git a/target/tilegx/Makefile.objs b/target/tilegx/Makefile.objs index 0db778f407..b3c0e1ec1c 100644 --- a/target/tilegx/Makefile.objs +++ b/target/tilegx/Makefile.objs @@ -1 +1,5 @@ -obj-y +=3D cpu.o translate.o helper.o simd_helper.o +obj-y +=3D translate.o cpu.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o simd_helper.o +endif diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index b79868e1e4..1925de4271 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -24,7 +24,11 @@ #include "qemu-common.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" -#include "linux-user/syscall_defs.h" +#ifdef CONFIG_LIBTCG +# define TARGET_SIGSEGV 0 +#else +# include "linux-user/syscall_defs.h" +#endif #include "exec/exec-all.h" =20 TileGXCPU *cpu_tilegx_init(const char *cpu_model) @@ -94,6 +98,7 @@ static void tilegx_cpu_initfn(Object *obj) } } =20 +#ifndef CONFIG_LIBTCG static void tilegx_cpu_do_interrupt(CPUState *cs) { cs->exception_index =3D -1; @@ -121,6 +126,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int= interrupt_request) } return false; } +#endif =20 static void tilegx_cpu_class_init(ObjectClass *oc, void *data) { @@ -135,11 +141,13 @@ static void tilegx_cpu_class_init(ObjectClass *oc, vo= id *data) cc->reset =3D tilegx_cpu_reset; =20 cc->has_work =3D tilegx_cpu_has_work; +#ifndef CONFIG_LIBTCG cc->do_interrupt =3D tilegx_cpu_do_interrupt; cc->cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; - cc->set_pc =3D tilegx_cpu_set_pc; cc->handle_mmu_fault =3D tilegx_cpu_handle_mmu_fault; +#endif + cc->set_pc =3D tilegx_cpu_set_pc; cc->gdb_num_core_regs =3D 0; } =20 diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index a170b744f4..843e25bc80 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -26,7 +26,15 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" -#include "linux-user/syscall_defs.h" + +#ifdef CONFIG_LIBTCG +# define TARGET_SIGTRAP 0 +# define TARGET_TRAP_BRKPT 0 +# define TARGET_SIGILL 0 +# define TARGET_ILL_ILLOPC 0 +#else +# include "linux-user/syscall_defs.h" +#endif =20 #include "opcode_tilegx.h" #include "spr_def_64.h" @@ -2456,6 +2464,7 @@ void tilegx_tcg_init(void) } } =20 +#ifndef CONFIG_LIBTCG void tilegx_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpr= intf, int flags) { @@ -2481,3 +2490,4 @@ void tilegx_cpu_dump_state(CPUState *cs, FILE *f, fpr= intf_function cpu_fprintf, cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n", env->pc, env->spregs[TILEGX_SPR_CMPEXCH]); } +#endif diff --git a/target/tricore/Makefile.objs b/target/tricore/Makefile.objs index 7a05670718..e68f251d62 100644 --- a/target/tricore/Makefile.objs +++ b/target/tricore/Makefile.objs @@ -1 +1,5 @@ -obj-y +=3D translate.o helper.o cpu.o op_helper.o fpu_helper.o +obj-y +=3D translate.o cpu.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o fpu_helper.o +endif diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ddd2dd07dd..245cd6d17d 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -90,6 +90,7 @@ enum { MODE_UU =3D 3, }; =20 +#ifndef CONFIG_LIBTCG void tricore_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -121,6 +122,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, } cpu_fprintf(f, "\n"); } +#endif =20 /* * Functions to generate micro-ops diff --git a/target/unicore32/Makefile.objs b/target/unicore32/Makefile.objs index 6b41b1e9ef..6013189869 100644 --- a/target/unicore32/Makefile.objs +++ b/target/unicore32/Makefile.objs @@ -1,4 +1,7 @@ -obj-y +=3D translate.o op_helper.o helper.o cpu.o -obj-y +=3D ucf64_helper.o +obj-y +=3D translate.o cpu.o =20 obj-$(CONFIG_SOFTMMU) +=3D softmmu.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o ucf64_helper.o +endif diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index bab718af7b..f1ac24cf89 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -162,15 +162,19 @@ static void uc32_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D uc32_cpu_class_by_name; cc->has_work =3D uc32_cpu_has_work; + cc->set_pc =3D uc32_cpu_set_pc; +#ifndef CONFIG_LIBTCG cc->do_interrupt =3D uc32_cpu_do_interrupt; cc->cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; - cc->set_pc =3D uc32_cpu_set_pc; + #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D uc32_cpu_handle_mmu_fault; #else cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; #endif + +#endif dc->vmsd =3D &vmstate_uc32_cpu; } =20 diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 666a2016a8..456338123b 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -2036,6 +2036,7 @@ done_generating: tb->icount =3D num_insns; } =20 +#ifndef CONFIG_LIBTCG static const char *cpu_mode_names[16] =3D { "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP", "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR" @@ -2103,6 +2104,7 @@ void uc32_cpu_dump_state(CPUState *cs, FILE *f, =20 cpu_dump_state_ucf64(env, f, cpu_fprintf, flags); } +#endif =20 void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, target_ulong *data) diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index 481de91973..51516b4a2a 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -1,7 +1,10 @@ -obj-y +=3D xtensa-semi.o -obj-y +=3D core-dc232b.o -obj-y +=3D core-dc233c.o -obj-y +=3D core-fsf.o +obj-y +=3D translate.o cpu.o + obj-$(CONFIG_SOFTMMU) +=3D monitor.o -obj-y +=3D translate.o op_helper.o helper.o cpu.o + +ifndef CONFIG_LIBTCG +obj-y +=3D helper.o op_helper.o +obj-y +=3D xtensa-semi.o +obj-y +=3D core-dc232b.o core-dc233c.o core-fsf.o obj-y +=3D gdbstub.o +endif diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 263002486c..617e9ad897 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -3256,6 +3256,7 @@ done: tb->icount =3D insn_count; } =20 +#ifndef CONFIG_LIBTCG void xtensa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -3306,6 +3307,7 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f, } } } +#endif =20 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, target_ulong *data) diff --git a/tcg/tcg.c b/tcg/tcg.c index 652131e5e9..d834a536b9 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -22,11 +22,13 @@ * THE SOFTWARE. */ =20 -/* define it to use liveness analysis (better code) */ -#define USE_TCG_OPTIMIZATIONS - #include "qemu/osdep.h" =20 +/* define it to use liveness analysis (better code) */ +#ifndef CONFIG_LIBTCG +# define USE_TCG_OPTIMIZATIONS +#endif + /* Define to jump the ELF file used to communicate with GDB. */ #undef DEBUG_JIT =20 diff --git a/tcg/tcg.h b/tcg/tcg.h index 09e452ca46..884ff9f20f 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -593,6 +593,7 @@ void tcg_pool_reset(TCGContext *s); void tb_lock(void); void tb_unlock(void); void tb_lock_reset(void); +TranslationBlock *tb_alloc(target_ulong pc); =20 /* Called with tb_lock held. */ static inline void *tcg_malloc(int size) diff --git a/tests/Makefile.include b/tests/Makefile.include index e60bb6ce58..21030600c2 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -8,6 +8,8 @@ SYSEMU_TARGET_LIST :=3D $(subst -softmmu.mak,,$(notdir \ =20 check-unit-y =3D tests/check-qdict$(EXESUF) gcov-files-check-qdict-y =3D qobject/qdict.c +check-unit-y +=3D tests/test-libtcg$(EXESUF) +gcov-files-test-libtcg-y =3D libtcg/tcg.c check-unit-y +=3D tests/test-char$(EXESUF) gcov-files-check-qdict-y =3D chardev/char.c check-unit-y +=3D tests/check-qfloat$(EXESUF) @@ -495,7 +497,9 @@ test-obj-y =3D tests/check-qint.o tests/check-qstring.o= tests/check-qdict.o \ tests/rcutorture.o tests/test-rcu-list.o \ tests/test-qdist.o tests/test-shift128.o \ tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \ - tests/atomic_add-bench.o + tests/atomic_add-bench.o tests/test-libtcg.o + +tests/test-libtcg: QEMU_CFLAGS +=3D -ldl =20 $(test-obj-y): QEMU_INCLUDES +=3D -Itests QEMU_CFLAGS +=3D -I$(SRC_PATH)/tests @@ -514,6 +518,7 @@ test-block-obj-y =3D $(block-obj-y) $(test-io-obj-y) te= sts/iothread.o tests/check-qint$(EXESUF): tests/check-qint.o $(test-util-obj-y) tests/check-qstring$(EXESUF): tests/check-qstring.o $(test-util-obj-y) tests/check-qdict$(EXESUF): tests/check-qdict.o $(test-util-obj-y) +tests/check-libtcg$(EXESUF): tests/check-libtcg.o $(test-util-obj-y) tests/check-qlist$(EXESUF): tests/check-qlist.o $(test-util-obj-y) tests/check-qfloat$(EXESUF): tests/check-qfloat.o $(test-util-obj-y) tests/check-qnull$(EXESUF): tests/check-qnull.o $(test-util-obj-y) diff --git a/tests/test-libtcg.c b/tests/test-libtcg.c new file mode 100644 index 0000000000..4b5e142aec --- /dev/null +++ b/tests/test-libtcg.c @@ -0,0 +1,238 @@ +/* + * libtcg unit-tests. + * + * Copyright (C) 2017 Alessandro Di Federico + * + * Authors: + * Alessandro Di Federico + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or l= ater. + * See the COPYING.LIB file in the top-level directory. + */ + +#include +#include +#include +#include +#include +#include + +#include "libtcg.h" + +static const char *get_default_cpu(const char *architecture) +{ + if (strcmp(architecture, "arm") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "armeb") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "cris") =3D=3D 0) { + return "crisv17"; + } else if (strcmp(architecture, "aarch64") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "or1k") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "hppa") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "microblaze") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "microblazeel") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "nios2") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "m68k") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "tilegx") =3D=3D 0) { + return "any"; + } else if (strcmp(architecture, "alpha") =3D=3D 0) { + return "ev4-alpha-cpu"; + } else if (strcmp(architecture, "mips") =3D=3D 0) { + return "mips32r6-generic"; + } else if (strcmp(architecture, "mips64el") =3D=3D 0) { + return "mips32r6-generic"; + } else if (strcmp(architecture, "mips64") =3D=3D 0) { + return "mips32r6-generic"; + } else if (strcmp(architecture, "mipsel") =3D=3D 0) { + return "mips32r6-generic"; + } else if (strcmp(architecture, "mipsn32el") =3D=3D 0) { + return "mips32r6-generic"; + } else if (strcmp(architecture, "mipsn32") =3D=3D 0) { + return "mips32r6-generic"; + } else if (strcmp(architecture, "x86_64") =3D=3D 0) { + return "qemu64"; + } else if (strcmp(architecture, "i386") =3D=3D 0) { + return "qemu64"; + } else if (strcmp(architecture, "ppc64abi32") =3D=3D 0) { + return "default"; + } else if (strcmp(architecture, "ppc64le") =3D=3D 0) { + return "default"; + } else if (strcmp(architecture, "ppc64") =3D=3D 0) { + return "default"; + } else if (strcmp(architecture, "ppc") =3D=3D 0) { + return "default"; + } else if (strcmp(architecture, "s390x") =3D=3D 0) { + return "qemu"; + } else if (strcmp(architecture, "sh4") =3D=3D 0) { + return "SH7785"; + } else if (strcmp(architecture, "sh4eb") =3D=3D 0) { + return "SH7785"; + } else if (strcmp(architecture, "sparc") =3D=3D 0) { + return "TI MicroSparc II"; + } else if (strcmp(architecture, "sparc64") =3D=3D 0) { + return "Fujitsu Sparc64 V"; + } else if (strcmp(architecture, "sparc32plus") =3D=3D 0) { + return "Sun UltraSparc IV"; + } + + g_assert(false); +} + +static const char *get_architecture(char *path) +{ + size_t length =3D strlen(path); + path +=3D length; + + while (*path !=3D '-') { + path--; + } + + char *start =3D path + 1; + + while (*path !=3D '.') { + path++; + } + + *path =3D '\0'; + return start; +} + +typedef struct { + char *path; + char *name; + const char *cpu; +} Architecture; + +static void test_libtcg(gconstpointer argument) +{ + const Architecture *architecture =3D (const Architecture *) argument; + + /* Load the library */ + void *handle =3D dlopen(architecture->path, RTLD_LAZY); + if (handle =3D=3D NULL) { + fprintf(stderr, "Couldn't load %s: %s\n", + architecture->path, dlerror()); + } + g_assert(handle !=3D NULL); + + /* Obtain a reference to the libtcg_init entry point */ + libtcg_init_func libtcg_init =3D dlsym(handle, "libtcg_init"); + g_assert(libtcg_init !=3D NULL); + + /* For some architectures, actually test the translation */ + bool translate =3D true; + uint32_t buffer[8] =3D { 0 }; + unsigned expected_instruction_count =3D 0; + if (strcmp(architecture->name, "arm") =3D=3D 0) { + buffer[0] =3D 0xe3a0b000; + buffer[1] =3D 0xe3a0e000; + buffer[2] =3D 0xe12fff1e; + expected_instruction_count =3D 3; + } else if (strcmp(architecture->name, "mips") =3D=3D 0) { + buffer[0] =3D 0x8fbf001c; + buffer[1] =3D 0x03e00008; + buffer[2] =3D 0x27bd0020; + expected_instruction_count =3D 3; + } else if (strcmp(architecture->name, "x86_64") =3D=3D 0) { + buffer[0] =3D 0x9090c3; + expected_instruction_count =3D 1; + } else if (strcmp(architecture->name, "s390x") =3D=3D 0) { + /* s390x is currently broken, disable it */ + return; + } else { + translate =3D false; + } + + /* Initialize libtcg */ + const LibTCGInterface *libtcg =3D libtcg_init(architecture->cpu, 0xb00= 00000); + g_assert(libtcg !=3D NULL); + + + if (translate) { + /* mmap a page */ + address_pair mmapd_address =3D { 0 }; + mmapd_address =3D libtcg->mmap(0, 4096, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + g_assert(mmapd_address.pointer !=3D NULL + && mmapd_address.virtual_address !=3D 0); + + /* Copy the code to the mmap'd page */ + memcpy(mmapd_address.pointer, + buffer, + 8 * sizeof(uint32_t)); + + /* Perform the translation */ + LibTCGInstructions instructions; + instructions =3D libtcg->translate(mmapd_address.virtual_address); + + /* Count the instructions (in terms of the input architectures, no= t tiny + * code instructions) */ + unsigned tci_count =3D instructions.instruction_count; + unsigned instruction_count =3D 0; + for (unsigned i =3D 0; i < tci_count; i++) { + LibTCGOpcode opcode =3D instructions.instructions[i].opc; + if (opcode =3D=3D LIBTCG_INDEX_op_insn_start) { + instruction_count++; + } + } + + /* Check the expected amount of instructions have been met */ + g_assert(instruction_count =3D=3D expected_instruction_count); + + /* Cleanup */ + libtcg->free_instructions(&instructions); + } +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + /* Enumerate all the versions of libtcg that have been compiled */ + glob_t results; + int result =3D glob("*-libtcg/libtcg-*.so*", 0, NULL, &results); + if (result =3D=3D GLOB_NOMATCH) { + return 0; + } + g_assert(result =3D=3D 0); + + /* Collect path to the library, name of the architecture and default C= PU + * for the architecture in a data structure */ + unsigned architectures_count =3D results.gl_pathc; + Architecture *architectures =3D g_malloc0_n(sizeof(Architecture), + architectures_count); + + for (unsigned i =3D 0; i < architectures_count; i++) { + char *path =3D results.gl_pathv[i]; + architectures[i].path =3D g_strdup(path); + architectures[i].name =3D g_strdup(get_architecture(path)); + architectures[i].cpu =3D get_default_cpu(architectures[i].name); + + /* Create a test for each architecture */ + gchar *name =3D g_strdup_printf("/libtcg/%s", architectures[i].nam= e); + g_test_add_data_func(name, &architectures[i], test_libtcg); + g_free(name); + } + + globfree(&results); + + /* Run the tests */ + result =3D g_test_run(); + + /* Perform cleanup operations */ + for (unsigned i =3D 0; i < architectures_count; i++) { + g_free(architectures[i].path); + g_free(architectures[i].name); + } + g_free(architectures); + + return result; +} diff --git a/trace/Makefile.objs b/trace/Makefile.objs index 7de840ad7e..297edd515a 100644 --- a/trace/Makefile.objs +++ b/trace/Makefile.objs @@ -44,7 +44,7 @@ $(obj)/generated-helpers.c-timestamp: $(trace-events-file= s) $(BUILD_DIR)/config- =20 $(obj)/generated-helpers.o: $(obj)/generated-helpers.c =20 -target-obj-y +=3D generated-helpers.o +target-obj-$(call lnot,$(CONFIG_LIBTCG)) +=3D generated-helpers.o =20 =20 $(obj)/generated-tcg-tracers.h: $(obj)/generated-tcg-tracers.h-timestamp diff --git a/translate-all.c b/translate-all.c index 5f44ec844e..38e10a34eb 100644 --- a/translate-all.c +++ b/translate-all.c @@ -843,7 +843,7 @@ bool tcg_enabled(void) * * Called with tb_lock held. */ -static TranslationBlock *tb_alloc(target_ulong pc) +TranslationBlock *tb_alloc(target_ulong pc) { TranslationBlock *tb; =20 --=20 2.11.1