From nobody Thu Nov 6 19:45:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488214613694957.3355983779348; Mon, 27 Feb 2017 08:56:53 -0800 (PST) Received: from localhost ([::1]:54299 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciObT-0001J9-A6 for importer@patchew.org; Mon, 27 Feb 2017 11:56:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43786) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciO75-00086H-3Q for qemu-devel@nongnu.org; Mon, 27 Feb 2017 11:25:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ciO71-0005Gv-UZ for qemu-devel@nongnu.org; Mon, 27 Feb 2017 11:25:27 -0500 Received: from mx1.redhat.com ([209.132.183.28]:51898) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ciO71-0005GS-Le for qemu-devel@nongnu.org; Mon, 27 Feb 2017 11:25:23 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D0DC87E9D8; Mon, 27 Feb 2017 16:25:23 +0000 (UTC) Received: from localhost (ovpn-116-24.gru2.redhat.com [10.97.116.24]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1RGPMne022272; Mon, 27 Feb 2017 11:25:23 -0500 From: Eduardo Habkost To: Peter Maydell Date: Mon, 27 Feb 2017 13:24:59 -0300 Message-Id: <20170227162501.29280-10-ehabkost@redhat.com> In-Reply-To: <20170227162501.29280-1-ehabkost@redhat.com> References: <20170227162501.29280-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Mon, 27 Feb 2017 16:25:23 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 09/11] i386: Define static "base" CPU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-devel@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The query-cpu-model-expand QMP command needs at least one static model, to allow the "static" expansion mode to be implemented. Instead of defining static versions of every CPU model, define a "base" CPU model that has absolutely no feature flag enabled. Despite having no CPUID data set at all, "-cpu base" is even a functional CPU: * It can boot a Slackware Linux 1.01 image with a Linux 0.99.12 kernel[1]. * It is even possible to boot[2] a modern Fedora x86_64 guest by manually enabling the following CPU features: -cpu base,+lm,+msr,+pae,+fpu,+cx8,+cmov,+sse,+sse2,+fxsr [1] http://www.qemu-advent-calendar.org/2014/#day-1 [2] This is what can be seen in the guest: [root@localhost ~]# cat /proc/cpuinfo processor : 0 vendor_id : unknown cpu family : 0 model : 0 model name : 00/00 stepping : 0 physical id : 0 siblings : 1 core id : 0 cpu cores : 1 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu msr pae cx8 cmov fxsr sse sse2 lm nopl bugs : bogomips : 5832.70 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: [root@localhost ~]# x86info -v -a x86info v1.30. Dave Jones 2001-2011 Feedback to . No TSC, MHz calculation cannot be performed. Unknown vendor (0) MP Table: Family: 0 Model: 0 Stepping: 0 CPU Model (x86info's best guess): eax in: 0x00000000, eax =3D 00000001 ebx =3D 00000000 ecx =3D 00000000 = edx =3D 00000000 eax in: 0x00000001, eax =3D 00000000 ebx =3D 00000800 ecx =3D 00000000 = edx =3D 07008161 eax in: 0x80000000, eax =3D 80000001 ebx =3D 00000000 ecx =3D 00000000 = edx =3D 00000000 eax in: 0x80000001, eax =3D 00000000 ebx =3D 00000000 ecx =3D 00000000 = edx =3D 20000000 Feature flags: fpu Onboard FPU msr Model-Specific Registers pae Physical Address Extensions cx8 CMPXCHG8 instruction cmov CMOV instruction fxsr FXSAVE and FXRSTOR instructions sse SSE support sse2 SSE2 support Long NOPs supported: yes Address sizes : 0 bits physical, 0 bits virtual 0MHz processor (estimate). running at an estimated 0MHz [root@localhost ~]# Message-Id: <20170222190029.17243-2-ehabkost@redhat.com> Reviewed-by: David Hildenbrand Tested-by: Jiri Denemark Signed-off-by: Eduardo Habkost --- target/i386/cpu-qom.h | 2 ++ target/i386/cpu.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index f6c704c3a9..c2205e6077 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -50,6 +50,7 @@ typedef struct X86CPUDefinition X86CPUDefinition; * @kvm_required: Whether CPU model requires KVM to be enabled. * @ordering: Ordering on the "-cpu help" CPU model list. * @migration_safe: See CpuDefinitionInfo::migration_safe + * @static_model: See CpuDefinitionInfo::static * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * @@ -68,6 +69,7 @@ typedef struct X86CPUClass { bool kvm_required; int ordering; bool migration_safe; + bool static_model; =20 /* Optional description of CPU model. * If unavailable, cpu_def->model_id is used */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 366253cd4c..0a71594445 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2229,6 +2229,7 @@ static void x86_cpu_definition_entry(gpointer data, g= pointer user_data) info->q_typename =3D g_strdup(object_class_get_name(oc)); info->migration_safe =3D cc->migration_safe; info->has_migration_safe =3D true; + info->q_static =3D cc->static_model; =20 entry =3D g_malloc0(sizeof(*entry)); entry->value =3D info; @@ -3835,6 +3836,24 @@ static const TypeInfo x86_cpu_type_info =3D { .class_init =3D x86_cpu_common_class_init, }; =20 + +/* "base" CPU model, used by query-cpu-model-expansion */ +static void x86_cpu_base_class_init(ObjectClass *oc, void *data) +{ + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); + + xcc->static_model =3D true; + xcc->migration_safe =3D true; + xcc->model_description =3D "base CPU model type with no features enabl= ed"; + xcc->ordering =3D 8; +} + +static const TypeInfo x86_base_cpu_type_info =3D { + .name =3D X86_CPU_TYPE_NAME("base"), + .parent =3D TYPE_X86_CPU, + .class_init =3D x86_cpu_base_class_init, +}; + static void x86_cpu_register_types(void) { int i; @@ -3844,6 +3863,7 @@ static void x86_cpu_register_types(void) x86_register_cpudef_type(&builtin_x86_defs[i]); } type_register_static(&max_x86_cpu_type_info); + type_register_static(&x86_base_cpu_type_info); #ifdef CONFIG_KVM type_register_static(&host_x86_cpu_type_info); #endif --=20 2.11.0.259.g40922b1