From nobody Thu May 2 17:02:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488128098180836.6550852096484; Sun, 26 Feb 2017 08:54:58 -0800 (PST) Received: from localhost ([::1]:47503 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ci264-0004KP-Ii for importer@patchew.org; Sun, 26 Feb 2017 11:54:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ci250-0003ou-OC for qemu-devel@nongnu.org; Sun, 26 Feb 2017 11:53:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ci24x-0007mj-HN for qemu-devel@nongnu.org; Sun, 26 Feb 2017 11:53:50 -0500 Received: from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34913) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ci24x-0007mY-An for qemu-devel@nongnu.org; Sun, 26 Feb 2017 11:53:47 -0500 Received: by mail-yw0-x242.google.com with SMTP id l16so4429862ywb.2 for ; Sun, 26 Feb 2017 08:53:47 -0800 (PST) Received: from localhost.localdomain (c-73-207-178-95.hsd1.ga.comcast.net. [73.207.178.95]) by smtp.gmail.com with ESMTPSA id j16sm5786459ywg.35.2017.02.26.08.53.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Feb 2017 08:53:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=rwmTYTtv9wUuFaOE1BehgqqJK7Rq1oneMdze21miNDQ=; b=B2qR/mgeYoMIFzg6bxXRUdPEHw3B/NyOmtFksEPHwuiThPavjPB2TxLNgpP+Onm95q AhWj5v5VXcJAdS/+kdbh0bB+Badqin0qOsxmzxYz50kwuMjN/LfxUor+PHCQuHxqIkep TuNZ81D/454jpcEhh1UWaWiDUVEpLHo7AkPZkfvyZMvNAn1tPY0n8x3g70AqbBlNrnQq b7fViWbA0+XOhKrbxVC6g8Grn7/KEcnq6qbTtN+I6gj7ysVvFw5o9bQuZE+6qnoqwyZu CRESYHNbCzffGXcnbZHw0C/f7tl7/2po++DFFVor/s92eIYWzxZ9zs3+5VYRvZzL1PJq mK0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=rwmTYTtv9wUuFaOE1BehgqqJK7Rq1oneMdze21miNDQ=; b=twxK+oCDqi21HJ7xbVSd8yuXGYouilvaaglCgf1PUeF69hr321NWvJI/jDg3gVkUim 7W6LnUxASZAbXjRBPeTarFm26rpqO3204ZnKPDi/NIeJHpZwWjq70PSfpK0k+Fcbfthr x50V7AgJi1jr0xwYxb1YxK7ERM7sO5XMnrAWFemvFcPGdUk0gGnoA3rMZq3uhXSl6oOd Wbnj1cPoWnkDc5oUO095BfC28qauu5MMYz7ajHwgRIp4OPUV2FD5p199NpVC7FyvGqzU U8kSvqEOPIkzbAHb7uPZh2cFiiern/m/1f4L4KIa1XPOMkD0f4zumkmV7qF+vZ1tiFGR ro/g== X-Gm-Message-State: AMke39lI31BHhO9B02D23/1+bAxZCrpJ0P/WebRG+JoyVycsdV8AssZUZcRtTz462GJdlQ== X-Received: by 10.129.175.16 with SMTP id n16mr1268770ywh.26.1488128026325; Sun, 26 Feb 2017 08:53:46 -0800 (PST) From: Pranith Kumar To: Riku Voipio , Paolo Bonzini , Richard Henderson , Eduardo Habkost , qemu-devel@nongnu.org (open list:All patches CC here) Date: Sun, 26 Feb 2017 11:53:44 -0500 Message-Id: <20170226165345.8757-1-bobby.prani@gmail.com> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:4002:c05::242 Subject: [Qemu-devel] [PATCH v3] linux-user: Add signal handling support for x86_64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: awirth@akamai.com, Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note that x86_64 has only _rt signal handlers. This implementation attempts to share code with the x86_32 implementation. CC: Laurent Vivier Signed-off-by: Allan Wirth Reviewed-by: Peter Maydell Signed-off-by: Pranith Kumar Reviewed-by: Laurent Vivier --- linux-user/signal.c | 278 ++++++++++++++++++++++++++++++++++++++-----= ---- target/i386/cpu.h | 2 + target/i386/fpu_helper.c | 12 ++ 3 files changed, 241 insertions(+), 51 deletions(-) diff --git a/linux-user/signal.c b/linux-user/signal.c index 8209539555..5dae87e3f4 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -254,7 +254,7 @@ int do_sigprocmask(int how, const sigset_t *set, sigset= _t *oldset) } =20 #if !defined(TARGET_OPENRISC) && !defined(TARGET_UNICORE32) && \ - !defined(TARGET_X86_64) && !defined(TARGET_NIOS2) + !defined(TARGET_NIOS2) /* Just set the guest's signal mask to the specified value; the * caller is assumed to have called block_signals() already. */ @@ -512,7 +512,7 @@ void signal_init(void) } } =20 -#if !(defined(TARGET_X86_64) || defined(TARGET_UNICORE32)) +#ifndef TARGET_UNICORE32 /* Force a synchronously taken signal. The kernel force_sig() function * also forces the signal to "not blocked, not ignored", but for QEMU * that work is done in process_pending_signals(). @@ -819,9 +819,8 @@ int do_sigaction(int sig, const struct target_sigaction= *act, return ret; } =20 -#if defined(TARGET_I386) && TARGET_ABI_BITS =3D=3D 32 - -/* from the Linux kernel */ +#if defined(TARGET_I386) +/* from the Linux kernel - /arch/x86/include/uapi/asm/sigcontext.h */ =20 struct target_fpreg { uint16_t significand[4]; @@ -835,58 +834,120 @@ struct target_fpxreg { }; =20 struct target_xmmreg { - abi_ulong element[4]; + uint32_t element[4]; }; =20 -struct target_fpstate { +struct target_fpstate_32 { /* Regular FPU environment */ - abi_ulong cw; - abi_ulong sw; - abi_ulong tag; - abi_ulong ipoff; - abi_ulong cssel; - abi_ulong dataoff; - abi_ulong datasel; - struct target_fpreg _st[8]; + uint32_t cw; + uint32_t sw; + uint32_t tag; + uint32_t ipoff; + uint32_t cssel; + uint32_t dataoff; + uint32_t datasel; + struct target_fpreg st[8]; uint16_t status; uint16_t magic; /* 0xffff =3D regular FPU data only */ =20 /* FXSR FPU environment */ - abi_ulong _fxsr_env[6]; /* FXSR FPU env is ignored */ - abi_ulong mxcsr; - abi_ulong reserved; - struct target_fpxreg _fxsr_st[8]; /* FXSR FPU reg data is ignored */ - struct target_xmmreg _xmm[8]; - abi_ulong padding[56]; + uint32_t _fxsr_env[6]; /* FXSR FPU env is ignored */ + uint32_t mxcsr; + uint32_t reserved; + struct target_fpxreg fxsr_st[8]; /* FXSR FPU reg data is ignored */ + struct target_xmmreg xmm[8]; + uint32_t padding[56]; }; =20 -#define X86_FXSR_MAGIC 0x0000 +struct target_fpstate_64 { + /* FXSAVE format */ + uint16_t cw; + uint16_t sw; + uint16_t twd; + uint16_t fop; + uint64_t rip; + uint64_t rdp; + uint32_t mxcsr; + uint32_t mxcsr_mask; + uint32_t st_space[32]; + uint32_t xmm_space[64]; + uint32_t reserved[24]; +}; =20 -struct target_sigcontext { +#ifndef TARGET_X86_64 +# define target_fpstate target_fpstate_32 +#else +# define target_fpstate target_fpstate_64 +#endif + +struct target_sigcontext_32 { uint16_t gs, __gsh; uint16_t fs, __fsh; uint16_t es, __esh; uint16_t ds, __dsh; - abi_ulong edi; - abi_ulong esi; - abi_ulong ebp; - abi_ulong esp; - abi_ulong ebx; - abi_ulong edx; - abi_ulong ecx; - abi_ulong eax; - abi_ulong trapno; - abi_ulong err; - abi_ulong eip; + uint32_t edi; + uint32_t esi; + uint32_t ebp; + uint32_t esp; + uint32_t ebx; + uint32_t edx; + uint32_t ecx; + uint32_t eax; + uint32_t trapno; + uint32_t err; + uint32_t eip; uint16_t cs, __csh; - abi_ulong eflags; - abi_ulong esp_at_signal; + uint32_t eflags; + uint32_t esp_at_signal; uint16_t ss, __ssh; - abi_ulong fpstate; /* pointer */ - abi_ulong oldmask; - abi_ulong cr2; + uint32_t fpstate; /* pointer */ + uint32_t oldmask; + uint32_t cr2; }; =20 +struct target_sigcontext_64 { + uint64_t r8; + uint64_t r9; + uint64_t r10; + uint64_t r11; + uint64_t r12; + uint64_t r13; + uint64_t r14; + uint64_t r15; + + uint64_t rdi; + uint64_t rsi; + uint64_t rbp; + uint64_t rbx; + uint64_t rdx; + uint64_t rax; + uint64_t rcx; + uint64_t rsp; + uint64_t rip; + + uint64_t eflags; + + uint16_t cs; + uint16_t gs; + uint16_t fs; + uint16_t ss; + + uint64_t err; + uint64_t trapno; + uint64_t oldmask; + uint64_t cr2; + + uint64_t fpstate; /* pointer */ + uint64_t padding[8]; +}; + +#ifndef TARGET_X86_64 +# define target_sigcontext target_sigcontext_32 +#else +# define target_sigcontext target_sigcontext_64 +#endif + +/* see Linux/include/uapi/asm-generic/ucontext.h */ struct target_ucontext { abi_ulong tuc_flags; abi_ulong tuc_link; @@ -895,8 +956,8 @@ struct target_ucontext { target_sigset_t tuc_sigmask; /* mask last for extensibility */ }; =20 -struct sigframe -{ +#ifndef TARGET_X86_64 +struct sigframe { abi_ulong pretcode; int sig; struct target_sigcontext sc; @@ -905,8 +966,7 @@ struct sigframe char retcode[8]; }; =20 -struct rt_sigframe -{ +struct rt_sigframe { abi_ulong pretcode; int sig; abi_ulong pinfo; @@ -917,6 +977,17 @@ struct rt_sigframe char retcode[8]; }; =20 +#else + +struct rt_sigframe { + abi_ulong pretcode; + struct target_ucontext uc; + struct target_siginfo info; + struct target_fpstate fpstate; +}; + +#endif + /* * Set up a signal frame. */ @@ -927,6 +998,7 @@ static void setup_sigcontext(struct target_sigcontext *= sc, abi_ulong fpstate_addr) { CPUState *cs =3D CPU(x86_env_get_cpu(env)); +#ifndef TARGET_X86_64 uint16_t magic; =20 /* already locked in setup_frame() */ @@ -959,6 +1031,44 @@ static void setup_sigcontext(struct target_sigcontext= *sc, /* non-iBCS2 extensions.. */ __put_user(mask, &sc->oldmask); __put_user(env->cr[2], &sc->cr2); +#else + __put_user(env->regs[R_EDI], &sc->rdi); + __put_user(env->regs[R_ESI], &sc->rsi); + __put_user(env->regs[R_EBP], &sc->rbp); + __put_user(env->regs[R_ESP], &sc->rsp); + __put_user(env->regs[R_EBX], &sc->rbx); + __put_user(env->regs[R_EDX], &sc->rdx); + __put_user(env->regs[R_ECX], &sc->rcx); + __put_user(env->regs[R_EAX], &sc->rax); + + __put_user(env->regs[8], &sc->r8); + __put_user(env->regs[9], &sc->r9); + __put_user(env->regs[10], &sc->r10); + __put_user(env->regs[11], &sc->r11); + __put_user(env->regs[12], &sc->r12); + __put_user(env->regs[13], &sc->r13); + __put_user(env->regs[14], &sc->r14); + __put_user(env->regs[15], &sc->r15); + + __put_user(cs->exception_index, &sc->trapno); + __put_user(env->error_code, &sc->err); + __put_user(env->eip, &sc->rip); + + __put_user(env->eflags, &sc->eflags); + __put_user(env->segs[R_CS].selector, &sc->cs); + __put_user((uint16_t)0, &sc->gs); + __put_user((uint16_t)0, &sc->fs); + __put_user(env->segs[R_SS].selector, &sc->ss); + + __put_user(mask, &sc->oldmask); + __put_user(env->cr[2], &sc->cr2); + + /* fpstate_addr must be 16 byte aligned for fxsave */ + assert(!(fpstate_addr & 0xf)); + + cpu_x86_fxsave(env, fpstate_addr); + __put_user(fpstate_addr, &sc->fpstate); +#endif } =20 /* @@ -972,23 +1082,34 @@ get_sigframe(struct target_sigaction *ka, CPUX86Stat= e *env, size_t frame_size) =20 /* Default to using normal stack */ esp =3D env->regs[R_ESP]; +#ifdef TARGET_X86_64 + esp -=3D 128; /* this is the redzone */ +#endif + /* This is the X/Open sanctioned signal stack switching. */ if (ka->sa_flags & TARGET_SA_ONSTACK) { if (sas_ss_flags(esp) =3D=3D 0) { esp =3D target_sigaltstack_used.ss_sp + target_sigaltstack_use= d.ss_size; } } else { - +#ifndef TARGET_X86_64 /* This is the legacy signal stack switching. */ if ((env->segs[R_SS].selector & 0xffff) !=3D __USER_DS && !(ka->sa_flags & TARGET_SA_RESTORER) && ka->sa_restorer) { esp =3D (unsigned long) ka->sa_restorer; } +#endif } + +#ifndef TARGET_X86_64 return (esp - frame_size) & -8ul; +#else + return ((esp - frame_size) & (~15ul)) - 8; +#endif } =20 +#ifndef TARGET_X86_64 /* compare linux/arch/i386/kernel/signal.c:setup_frame() */ static void setup_frame(int sig, struct target_sigaction *ka, target_sigset_t *set, CPUX86State *env) @@ -1029,7 +1150,6 @@ static void setup_frame(int sig, struct target_sigact= ion *ka, __put_user(val16, (uint16_t *)(frame->retcode+6)); } =20 - /* Set up registers for signal handler */ env->regs[R_ESP] =3D frame_addr; env->eip =3D ka->_sa_handler; @@ -1047,13 +1167,17 @@ static void setup_frame(int sig, struct target_siga= ction *ka, give_sigsegv: force_sigsegv(sig); } +#endif =20 -/* compare linux/arch/i386/kernel/signal.c:setup_rt_frame() */ +/* compare linux/arch/x86/kernel/signal.c:setup_rt_frame() */ static void setup_rt_frame(int sig, struct target_sigaction *ka, target_siginfo_t *info, target_sigset_t *set, CPUX86State *env) { - abi_ulong frame_addr, addr; + abi_ulong frame_addr; +#ifndef TARGET_X86_64 + abi_ulong addr; +#endif struct rt_sigframe *frame; int i; =20 @@ -1063,12 +1187,17 @@ static void setup_rt_frame(int sig, struct target_s= igaction *ka, if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) goto give_sigsegv; =20 + /* These fields are only in rt_sigframe on 32 bit */ +#ifndef TARGET_X86_64 __put_user(sig, &frame->sig); addr =3D frame_addr + offsetof(struct rt_sigframe, info); __put_user(addr, &frame->pinfo); addr =3D frame_addr + offsetof(struct rt_sigframe, uc); __put_user(addr, &frame->puc); - tswap_siginfo(&frame->info, info); +#endif + if (ka->sa_flags & TARGET_SA_SIGINFO) { + tswap_siginfo(&frame->info, info); + } =20 /* Create the ucontext. */ __put_user(0, &frame->uc.tuc_flags); @@ -1087,6 +1216,7 @@ static void setup_rt_frame(int sig, struct target_sig= action *ka, =20 /* Set up to return from userspace. If provided, use a stub already in userspace. */ +#ifndef TARGET_X86_64 if (ka->sa_flags & TARGET_SA_RESTORER) { __put_user(ka->sa_restorer, &frame->pretcode); } else { @@ -1099,15 +1229,31 @@ static void setup_rt_frame(int sig, struct target_s= igaction *ka, val16 =3D 0x80cd; __put_user(val16, (uint16_t *)(frame->retcode+5)); } +#else + /* XXX: Would be slightly better to return -EFAULT here if test fails + assert(ka->sa_flags & TARGET_SA_RESTORER); */ + __put_user(ka->sa_restorer, &frame->pretcode); +#endif =20 /* Set up registers for signal handler */ env->regs[R_ESP] =3D frame_addr; env->eip =3D ka->_sa_handler; =20 +#ifndef TARGET_X86_64 + env->regs[R_EAX] =3D sig; + env->regs[R_EDX] =3D (unsigned long)&frame->info; + env->regs[R_ECX] =3D (unsigned long)&frame->uc; +#else + env->regs[R_EAX] =3D 0; + env->regs[R_EDI] =3D sig; + env->regs[R_ESI] =3D (unsigned long)&frame->info; + env->regs[R_EDX] =3D (unsigned long)&frame->uc; +#endif + cpu_x86_load_seg(env, R_DS, __USER_DS); cpu_x86_load_seg(env, R_ES, __USER_DS); - cpu_x86_load_seg(env, R_SS, __USER_DS); cpu_x86_load_seg(env, R_CS, __USER_CS); + cpu_x86_load_seg(env, R_SS, __USER_DS); env->eflags &=3D ~TF_MASK; =20 unlock_user_struct(frame, frame_addr, 1); @@ -1125,6 +1271,7 @@ restore_sigcontext(CPUX86State *env, struct target_si= gcontext *sc) abi_ulong fpstate_addr; unsigned int tmpflags; =20 +#ifndef TARGET_X86_64 cpu_x86_load_seg(env, R_GS, tswap16(sc->gs)); cpu_x86_load_seg(env, R_FS, tswap16(sc->fs)); cpu_x86_load_seg(env, R_ES, tswap16(sc->es)); @@ -1138,7 +1285,29 @@ restore_sigcontext(CPUX86State *env, struct target_s= igcontext *sc) env->regs[R_EDX] =3D tswapl(sc->edx); env->regs[R_ECX] =3D tswapl(sc->ecx); env->regs[R_EAX] =3D tswapl(sc->eax); + env->eip =3D tswapl(sc->eip); +#else + env->regs[8] =3D tswapl(sc->r8); + env->regs[9] =3D tswapl(sc->r9); + env->regs[10] =3D tswapl(sc->r10); + env->regs[11] =3D tswapl(sc->r11); + env->regs[12] =3D tswapl(sc->r12); + env->regs[13] =3D tswapl(sc->r13); + env->regs[14] =3D tswapl(sc->r14); + env->regs[15] =3D tswapl(sc->r15); + + env->regs[R_EDI] =3D tswapl(sc->rdi); + env->regs[R_ESI] =3D tswapl(sc->rsi); + env->regs[R_EBP] =3D tswapl(sc->rbp); + env->regs[R_EBX] =3D tswapl(sc->rbx); + env->regs[R_EDX] =3D tswapl(sc->rdx); + env->regs[R_EAX] =3D tswapl(sc->rax); + env->regs[R_ECX] =3D tswapl(sc->rcx); + env->regs[R_ESP] =3D tswapl(sc->rsp); + + env->eip =3D tswapl(sc->rip); +#endif =20 cpu_x86_load_seg(env, R_CS, lduw_p(&sc->cs) | 3); cpu_x86_load_seg(env, R_SS, lduw_p(&sc->ss) | 3); @@ -1152,7 +1321,11 @@ restore_sigcontext(CPUX86State *env, struct target_s= igcontext *sc) if (!access_ok(VERIFY_READ, fpstate_addr, sizeof(struct target_fpstate))) goto badframe; +#ifndef TARGET_X86_64 cpu_x86_frstor(env, fpstate_addr, 1); +#else + cpu_x86_fxrstor(env, fpstate_addr); +#endif } =20 return err; @@ -1160,6 +1333,8 @@ badframe: return 1; } =20 +/* Note: there is no sigreturn on x86_64, there is only rt_sigreturn */ +#ifndef TARGET_X86_64 long do_sigreturn(CPUX86State *env) { struct sigframe *frame; @@ -1191,6 +1366,7 @@ badframe: force_sig(TARGET_SIGSEGV); return -TARGET_QEMU_ESIGRETURN; } +#endif =20 long do_rt_sigreturn(CPUX86State *env) { @@ -1198,7 +1374,7 @@ long do_rt_sigreturn(CPUX86State *env) struct rt_sigframe *frame; sigset_t set; =20 - frame_addr =3D env->regs[R_ESP] - 4; + frame_addr =3D env->regs[R_ESP] - sizeof(abi_ulong); trace_user_do_rt_sigreturn(env, frame_addr); if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) goto badframe; @@ -6418,7 +6594,7 @@ static void handle_pending_signal(CPUArchState *cpu_e= nv, int sig, #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) \ || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) \ || defined(TARGET_PPC64) || defined(TARGET_HPPA) \ - || defined(TARGET_NIOS2) + || defined(TARGET_NIOS2) || defined(TARGET_X86_64) /* These targets do not have traditional signals. */ setup_rt_frame(sig, sa, &k->info, &target_old_set, cpu_env); #else diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8df124f332..573f2aa988 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1417,6 +1417,8 @@ floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); +void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); +void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); =20 /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index 66474ad98e..69ea33a5c2 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -1377,6 +1377,18 @@ void helper_fxrstor(CPUX86State *env, target_ulong p= tr) } } =20 +#if defined(CONFIG_USER_ONLY) +void cpu_x86_fxsave(CPUX86State *env, target_ulong ptr) +{ + helper_fxsave(env, ptr); +} + +void cpu_x86_fxrstor(CPUX86State *env, target_ulong ptr) +{ + helper_fxrstor(env, ptr); +} +#endif + void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm) { uintptr_t ra =3D GETPC(); --=20 2.11.0