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[109.151.49.69]) by smtp.gmail.com with ESMTPSA id u184sm7379770wmb.29.2017.02.23.10.36.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Feb 2017 10:36:33 -0800 (PST) Received: from zen.home (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 104593E1795; Thu, 23 Feb 2017 18:29:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w1is/gaQcK5Ex3dZS2V1G5RCeJtmuwWSsJtjZ2iK++w=; b=IIVcY54y8k4M73uS8Mn5+OtFXl7i84CZTVTOwXK/A9/kPhdCertFy12vxWAjZ55SFY eZfqDfEAmtKOvxVZwMhAYPjTdVRvofCypRjQH+1GhXdbS/U3COgqNYMyagzgui0uhh3y IIoJFu2RSZ82fV7tiEfVNVIqAjaz9VctlYYjc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w1is/gaQcK5Ex3dZS2V1G5RCeJtmuwWSsJtjZ2iK++w=; b=lbLDDMjmPm3SciLqV0diRvBdVo13v1Ny+lKZZypEznFw3UnVzbYgE8oVOYYWS4tnQR I34Q+SIwUhYv41wnAeMYMEAkxwgBlnkU7edV2SzahYB3UbefFOQCed9s6rKllJ1pDfxn zxW0/JhAj3yA0hObQenivUvJ7RVKJIUuPCYXnAmaHWT1TzeWUsEkGvuvRtISmoh8Evfe rhxVnlWvl1Va+UhkoxlzhKWw+Ok9McpesHnhL6mi9TOw2hla7B42SRW8O3AE1LxKunEG Q0K6QHpMBk0LuAj/clcUnBT7w7J6MTZ7Y2jRv2SP8TAUhzhy76A1sFku5k1wBAAkQNCX //Ag== X-Gm-Message-State: AMke39k5GtmuyAcsr3zIrkFi4mGztCz+3jMXREuWqQ3CvJ14UkvnIqSG7is/VwtlJKTOuQQP X-Received: by 10.223.143.36 with SMTP id p33mr16697575wrb.2.1487874994973; Thu, 23 Feb 2017 10:36:34 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, peter.maydell@linaro.org Date: Thu, 23 Feb 2017 18:29:26 +0000 Message-Id: <20170223182927.7166-24-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170223182927.7166-1-alex.bennee@linaro.org> References: <20170223182927.7166-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [PATCH v14 23/24] hw/misc/imx6_src: defer clearing of SRC_SCR reset bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, nikunj@linux.vnet.ibm.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, Peter Chubb , "open list:i.MX31" , serge.fdrv@gmail.com, pbonzini@redhat.com, bobby.prani@gmail.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The arm_reset_cpu/set_cpu_on/set_cpu_off() functions do their work asynchronously in the target vCPUs context. As a result we need to ensure the SRC_SCR reset bits correctly report the reset status at the right time. To do this we defer the clearing of the bit with an async job which will run after the work queued by ARM powerctl functions. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- v12 - s/src_scr_reset_info/SRCSCRResetInfo/ - use int for reset_bit; --- hw/misc/imx6_src.c | 58 +++++++++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 49 insertions(+), 9 deletions(-) diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c index 55b817b8d7..edbb756c36 100644 --- a/hw/misc/imx6_src.c +++ b/hw/misc/imx6_src.c @@ -14,6 +14,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "arm-powerctl.h" +#include "qom/cpu.h" =20 #ifndef DEBUG_IMX6_SRC #define DEBUG_IMX6_SRC 0 @@ -113,6 +114,45 @@ static uint64_t imx6_src_read(void *opaque, hwaddr off= set, unsigned size) return value; } =20 + +/* The reset is asynchronous so we need to defer clearing the reset + * bit until the work is completed. + */ + +struct SRCSCRResetInfo { + IMX6SRCState *s; + int reset_bit; +}; + +static void imx6_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) +{ + struct SRCSCRResetInfo *ri =3D data.host_ptr; + IMX6SRCState *s =3D ri->s; + + assert(qemu_mutex_iothread_locked()); + + s->regs[SRC_SCR] =3D deposit32(s->regs[SRC_SCR], ri->reset_bit, 1, 0); + DPRINTF("reg[%s] <=3D 0x%" PRIx32 "\n", + imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]); + + g_free(ri); +} + +static void imx6_defer_clear_reset_bit(int cpuid, + IMX6SRCState *s, + unsigned long reset_shift) +{ + struct SRCSCRResetInfo *ri; + + ri =3D g_malloc(sizeof(struct SRCSCRResetInfo)); + ri->s =3D s; + ri->reset_bit =3D reset_shift; + + async_run_on_cpu(arm_get_cpu_by_id(cpuid), imx6_clear_reset_bit, + RUN_ON_CPU_HOST_PTR(ri)); +} + + static void imx6_src_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -153,7 +193,7 @@ static void imx6_src_write(void *opaque, hwaddr offset,= uint64_t value, arm_set_cpu_off(3); } /* We clear the reset bits as the processor changed state */ - clear_bit(CORE3_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(3, s, CORE3_RST_SHIFT); clear_bit(CORE3_RST_SHIFT, &change_mask); } if (EXTRACT(change_mask, CORE2_ENABLE)) { @@ -162,11 +202,11 @@ static void imx6_src_write(void *opaque, hwaddr offse= t, uint64_t value, arm_set_cpu_on(2, s->regs[SRC_GPR5], s->regs[SRC_GPR6], 3, false); } else { - /* CORE 3 is shut down */ + /* CORE 2 is shut down */ arm_set_cpu_off(2); } /* We clear the reset bits as the processor changed state */ - clear_bit(CORE2_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(2, s, CORE2_RST_SHIFT); clear_bit(CORE2_RST_SHIFT, &change_mask); } if (EXTRACT(change_mask, CORE1_ENABLE)) { @@ -175,28 +215,28 @@ static void imx6_src_write(void *opaque, hwaddr offse= t, uint64_t value, arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], 3, false); } else { - /* CORE 3 is shut down */ + /* CORE 1 is shut down */ arm_set_cpu_off(1); } /* We clear the reset bits as the processor changed state */ - clear_bit(CORE1_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(1, s, CORE1_RST_SHIFT); clear_bit(CORE1_RST_SHIFT, &change_mask); } if (EXTRACT(change_mask, CORE0_RST)) { arm_reset_cpu(0); - clear_bit(CORE0_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(0, s, CORE0_RST_SHIFT); } if (EXTRACT(change_mask, CORE1_RST)) { arm_reset_cpu(1); - clear_bit(CORE1_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(1, s, CORE1_RST_SHIFT); } if (EXTRACT(change_mask, CORE2_RST)) { arm_reset_cpu(2); - clear_bit(CORE2_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(2, s, CORE2_RST_SHIFT); } if (EXTRACT(change_mask, CORE3_RST)) { arm_reset_cpu(3); - clear_bit(CORE3_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(3, s, CORE3_RST_SHIFT); } if (EXTRACT(change_mask, SW_IPU2_RST)) { /* We pretend the IPU2 is reset */ --=20 2.11.0