From nobody Fri Dec 19 20:33:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487784283918781.0019881875475; Wed, 22 Feb 2017 09:24:43 -0800 (PST) Received: from localhost ([::1]:54244 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgaef-0000Ut-0Q for importer@patchew.org; Wed, 22 Feb 2017 12:24:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgaU1-0006t1-CI for qemu-devel@nongnu.org; Wed, 22 Feb 2017 12:13:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cgaTy-0000cP-OK for qemu-devel@nongnu.org; Wed, 22 Feb 2017 12:13:41 -0500 Received: from mail-wr0-x231.google.com ([2a00:1450:400c:c0c::231]:35838) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cgaTy-0000c2-Gg for qemu-devel@nongnu.org; Wed, 22 Feb 2017 12:13:38 -0500 Received: by mail-wr0-x231.google.com with SMTP id s27so6633509wrb.2 for ; Wed, 22 Feb 2017 09:13:38 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g23sm2819517wme.27.2017.02.22.09.13.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Feb 2017 09:13:31 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id C0BB73E1315; Wed, 22 Feb 2017 17:13:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w1is/gaQcK5Ex3dZS2V1G5RCeJtmuwWSsJtjZ2iK++w=; b=L1Dx4PfC35sBftYs+A6/ld6dRW7lrb0CpLGlMQmjgftiSgZyVVHcF8lTXJD6TzNyt0 Lu+tNn3ul0R/JsDoG+hGFeCFsVT1DeP+uVfTEXtfJ+zB9nL9EowsvO8dzjBfzFzjV4wI YPUpxqqbF9TzJ4fIjCL/5+CgMNOSCU20+3tU8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w1is/gaQcK5Ex3dZS2V1G5RCeJtmuwWSsJtjZ2iK++w=; b=nFpZB2UIl2T3qCCId9vX9wzK/UAulDwcqgBoLdNid6Spw3OZRHFlwHT22yiqfrzNOT QSHZ5jNao0IS1HU8MgycYqrLEtCE8iwK5G13REraMtDFCeyKoWVyLNZDqx6VkZ5quKdN 64lfEw7gWz3umQRocgvzPMANLALHpzJ1AmpAr8pCcDbqwryOwXrhFoSeDN5rDWoVEFci 5HqQfzD5nlD0y4edkyPHuiqBVeInB3F4vZxslPir4wzF79OrWzaoqF/V8MDn1q2nOuYW Pzq8/GiMrvMoqiJwSN4OVU+rpTVUcckn5s9Blj7ORSCRdmfhOHHg+ID0OUO+7cLCg50n tE9g== X-Gm-Message-State: AMke39mdovxlASadQzKKG8XTj+wICKQNS1k9WpvH4myVqvc9xNXz7lSlDbJgkhlR3qsCuL4N X-Received: by 10.223.139.213 with SMTP id w21mr26166447wra.108.1487783617446; Wed, 22 Feb 2017 09:13:37 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: rth@twiddle.net, peter.maydell@linaro.org Date: Wed, 22 Feb 2017 17:13:26 +0000 Message-Id: <20170222171327.26624-24-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170222171327.26624-1-alex.bennee@linaro.org> References: <20170222171327.26624-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c0c::231 Subject: [Qemu-devel] [PATCH v13 23/24] hw/misc/imx6_src: defer clearing of SRC_SCR reset bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, nikunj@linux.vnet.ibm.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, Peter Chubb , "open list:i.MX31" , serge.fdrv@gmail.com, pbonzini@redhat.com, bobby.prani@gmail.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The arm_reset_cpu/set_cpu_on/set_cpu_off() functions do their work asynchronously in the target vCPUs context. As a result we need to ensure the SRC_SCR reset bits correctly report the reset status at the right time. To do this we defer the clearing of the bit with an async job which will run after the work queued by ARM powerctl functions. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- v12 - s/src_scr_reset_info/SRCSCRResetInfo/ - use int for reset_bit; --- hw/misc/imx6_src.c | 58 +++++++++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 49 insertions(+), 9 deletions(-) diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c index 55b817b8d7..edbb756c36 100644 --- a/hw/misc/imx6_src.c +++ b/hw/misc/imx6_src.c @@ -14,6 +14,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "arm-powerctl.h" +#include "qom/cpu.h" =20 #ifndef DEBUG_IMX6_SRC #define DEBUG_IMX6_SRC 0 @@ -113,6 +114,45 @@ static uint64_t imx6_src_read(void *opaque, hwaddr off= set, unsigned size) return value; } =20 + +/* The reset is asynchronous so we need to defer clearing the reset + * bit until the work is completed. + */ + +struct SRCSCRResetInfo { + IMX6SRCState *s; + int reset_bit; +}; + +static void imx6_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) +{ + struct SRCSCRResetInfo *ri =3D data.host_ptr; + IMX6SRCState *s =3D ri->s; + + assert(qemu_mutex_iothread_locked()); + + s->regs[SRC_SCR] =3D deposit32(s->regs[SRC_SCR], ri->reset_bit, 1, 0); + DPRINTF("reg[%s] <=3D 0x%" PRIx32 "\n", + imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]); + + g_free(ri); +} + +static void imx6_defer_clear_reset_bit(int cpuid, + IMX6SRCState *s, + unsigned long reset_shift) +{ + struct SRCSCRResetInfo *ri; + + ri =3D g_malloc(sizeof(struct SRCSCRResetInfo)); + ri->s =3D s; + ri->reset_bit =3D reset_shift; + + async_run_on_cpu(arm_get_cpu_by_id(cpuid), imx6_clear_reset_bit, + RUN_ON_CPU_HOST_PTR(ri)); +} + + static void imx6_src_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -153,7 +193,7 @@ static void imx6_src_write(void *opaque, hwaddr offset,= uint64_t value, arm_set_cpu_off(3); } /* We clear the reset bits as the processor changed state */ - clear_bit(CORE3_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(3, s, CORE3_RST_SHIFT); clear_bit(CORE3_RST_SHIFT, &change_mask); } if (EXTRACT(change_mask, CORE2_ENABLE)) { @@ -162,11 +202,11 @@ static void imx6_src_write(void *opaque, hwaddr offse= t, uint64_t value, arm_set_cpu_on(2, s->regs[SRC_GPR5], s->regs[SRC_GPR6], 3, false); } else { - /* CORE 3 is shut down */ + /* CORE 2 is shut down */ arm_set_cpu_off(2); } /* We clear the reset bits as the processor changed state */ - clear_bit(CORE2_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(2, s, CORE2_RST_SHIFT); clear_bit(CORE2_RST_SHIFT, &change_mask); } if (EXTRACT(change_mask, CORE1_ENABLE)) { @@ -175,28 +215,28 @@ static void imx6_src_write(void *opaque, hwaddr offse= t, uint64_t value, arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], 3, false); } else { - /* CORE 3 is shut down */ + /* CORE 1 is shut down */ arm_set_cpu_off(1); } /* We clear the reset bits as the processor changed state */ - clear_bit(CORE1_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(1, s, CORE1_RST_SHIFT); clear_bit(CORE1_RST_SHIFT, &change_mask); } if (EXTRACT(change_mask, CORE0_RST)) { arm_reset_cpu(0); - clear_bit(CORE0_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(0, s, CORE0_RST_SHIFT); } if (EXTRACT(change_mask, CORE1_RST)) { arm_reset_cpu(1); - clear_bit(CORE1_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(1, s, CORE1_RST_SHIFT); } if (EXTRACT(change_mask, CORE2_RST)) { arm_reset_cpu(2); - clear_bit(CORE2_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(2, s, CORE2_RST_SHIFT); } if (EXTRACT(change_mask, CORE3_RST)) { arm_reset_cpu(3); - clear_bit(CORE3_RST_SHIFT, ¤t_value); + imx6_defer_clear_reset_bit(3, s, CORE3_RST_SHIFT); } if (EXTRACT(change_mask, SW_IPU2_RST)) { /* We pretend the IPU2 is reset */ --=20 2.11.0