From nobody Thu Nov 6 20:33:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487747500051753.7145962100113; Tue, 21 Feb 2017 23:11:40 -0800 (PST) Received: from localhost ([::1]:50332 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgR5N-0005kW-Nr for importer@patchew.org; Wed, 22 Feb 2017 02:11:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38056) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgQVB-000396-VU for qemu-devel@nongnu.org; Wed, 22 Feb 2017 01:34:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cgQV9-0008BX-Ag for qemu-devel@nongnu.org; Wed, 22 Feb 2017 01:34:13 -0500 Received: from ozlabs.org ([103.22.144.67]:39417) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cgQV8-000862-Rr; Wed, 22 Feb 2017 01:34:11 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vSndL6KX8z9sN6; Wed, 22 Feb 2017 17:33:56 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1487745238; bh=Wibaa/Pd6hp6FoKVstA1XgwRNaRQgOrD0KHdMymU4g8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g9yYdNDoi76D6fcTPE3dPYlZW6/53g+ETCjj2gfyz4JyAOECCtkvaQ6qICjRNQBaB k42y5SK6CUGXRAkr8l0623CLSmm9HoOSe6uDfSv3KJxxcG/qcwfDu3Kqv9jQ0Rxgo3 arQ4nuBiuH5Nyz5I8umXqhBBVJzDduseUuc+XLtA= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 22 Feb 2017 17:33:34 +1100 Message-Id: <20170222063348.32176-30-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170222063348.32176-1-david@gibson.dropbear.id.au> References: <20170222063348.32176-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 29/43] target/ppc/POWER9: Adapt LPCR handling for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, qemu-ppc@nongnu.org, Suraj Jitindar Singh , imammedo@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Suraj Jitindar Singh The logical partitioning control register controls a threads operation based on the partition it is currently executing. Add new definitions and update the mask used when writing to the LPCR based on the POWER9 spec. Signed-off-by: Suraj Jitindar Singh Signed-off-by: David Gibson --- target/ppc/cpu.h | 18 ++++++++++++++++++ target/ppc/mmu-hash64.c | 8 ++++++++ target/ppc/translate_init.c | 24 ++++++++++++++++++------ 3 files changed, 44 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bb96dd5..425e79d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -384,12 +384,19 @@ struct ppc_slb_t { #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) #define LPCR_VRMASD_SHIFT (63 - 16) #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */ +#define LPCR_PECE_U_SHIFT (63 - 19) +#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) +#define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt Exit Enab= le */ #define LPCR_RMLS_SHIFT (63 - 37) #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) #define LPCR_ILE (1ull << (63 - 38)) #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) +#define LPCR_UPRT (1ull << (63 - 41)) /* Use Process Table */ +#define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced Virtualisation */ #define LPCR_ONL (1ull << (63 - 45)) +#define LPCR_LD (1ull << (63 - 46)) /* Large Decrementer */ #define LPCR_P7_PECE0 (1ull << (63 - 49)) #define LPCR_P7_PECE1 (1ull << (63 - 50)) #define LPCR_P7_PECE2 (1ull << (63 - 51)) @@ -398,11 +405,22 @@ struct ppc_slb_t { #define LPCR_P8_PECE2 (1ull << (63 - 49)) #define LPCR_P8_PECE3 (1ull << (63 - 50)) #define LPCR_P8_PECE4 (1ull << (63 - 51)) +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */ +#define LPCR_PECE_L_SHIFT (63 - 51) +#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT) +#define LPCR_PDEE (1ull << (63 - 47)) /* Privileged Doorbell Exit = EN */ +#define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enab= le */ +#define LPCR_EEE (1ull << (63 - 49)) /* External Exit Enable = */ +#define LPCR_DEE (1ull << (63 - 50)) /* Decrementer Exit Enable = */ +#define LPCR_OEE (1ull << (63 - 51)) /* Other Exit Enable = */ #define LPCR_MER (1ull << (63 - 52)) +#define LPCR_GTSE (1ull << (63 - 53)) /* Guest Translation Shootdo= wn */ #define LPCR_TC (1ull << (63 - 54)) +#define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern Interrupt Contr= ol */ #define LPCR_LPES0 (1ull << (63 - 60)) #define LPCR_LPES1 (1ull << (63 - 61)) #define LPCR_RMI (1ull << (63 - 62)) +#define LPCR_HVICE (1ull << (63 - 62)) /* HV Virtualisation Int Ena= ble */ #define LPCR_HDICE (1ull << (63 - 63)) =20 #define msr_sf ((env->msr >> MSR_SF) & 1) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 2791f29..c09255d 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1062,6 +1062,14 @@ void helper_store_lpcr(CPUPPCState *env, target_ulon= g val) LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); break; + case POWERPC_MMU_3_00: /* P9 */ + lpcr =3D val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL= | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EE= E | + LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_= TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); + break; default: ; } diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 84bf125..be35cbd 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8870,12 +8870,24 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu) lpcr->default_value &=3D ~LPCR_RMLS; lpcr->default_value |=3D 1ull << LPCR_RMLS_SHIFT; =20 - /* P7 and P8 has slightly different PECE bits, mostly because P8 adds - * bit 47 and 48 which are reserved on P7. Here we set them all, which - * will work as expected for both implementations - */ - lpcr->default_value |=3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2= | - LPCR_P8_PECE3 | LPCR_P8_PECE4; + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* By default we choose legacy mode and switch to new hash or radix + * when a register process table hcall is made. So disable process + * tables and guest translation shootdown by default + */ + lpcr->default_value &=3D ~(LPCR_UPRT | LPCR_GTSE); + lpcr->default_value |=3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_D= EE | + LPCR_OEE; + break; + default: + /* P7 and P8 has slightly different PECE bits, mostly because P8 a= dds + * bit 47 and 48 which are reserved on P7. Here we set them all, w= hich + * will work as expected for both implementations + */ + lpcr->default_value |=3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_P= ECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; + } =20 /* We should be followed by a CPU reset but update the active value * just in case... --=20 2.9.3