From nobody Thu Nov 6 20:33:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487746700409559.8852147559578; Tue, 21 Feb 2017 22:58:20 -0800 (PST) Received: from localhost ([::1]:50245 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgQsU-0000j0-WC for importer@patchew.org; Wed, 22 Feb 2017 01:58:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgQV8-000353-Lw for qemu-devel@nongnu.org; Wed, 22 Feb 2017 01:34:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cgQV5-00083a-Ry for qemu-devel@nongnu.org; Wed, 22 Feb 2017 01:34:10 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:54661) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cgQV5-0007yl-AO; Wed, 22 Feb 2017 01:34:07 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vSndK31PGz9sDG; Wed, 22 Feb 2017 17:33:55 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1487745237; bh=UBpIhMpfaIF6IzSafCTYbIwVH0NUp7TaL8xg+DU5084=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=clZeLO9mGoMMPI/kuF7QIXM911RvFqJCAHbHAhT60cjaMpZwIjxkK0w6jWh8FvuKr 1G+dxXPDmA32rFlaPHZ/w678eyBW0dVe21cgZt7VyEHjmo6Q42dhfNYaEGZS9zdnMN Ee+WYpkKe+QPRHiOlO8fsV2RnPyAs6FhBaTxBSw0= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 22 Feb 2017 17:33:27 +1100 Message-Id: <20170222063348.32176-23-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170222063348.32176-1-david@gibson.dropbear.id.au> References: <20170222063348.32176-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 22/43] softfloat: Add round-to-odd rounding mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, qemu-ppc@nongnu.org, Bharata B Rao , imammedo@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bharata B Rao Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target format, the result is Z. Otherwise the result is either Z1 or Z2 whichever is odd. Here Z1 and Z2 are the next larger and smaller numbers representable in the target format respectively. Signed-off-by: Bharata B Rao Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- fpu/softfloat.c | 21 ++++++++++++++++++++- include/fpu/softfloat.h | 2 ++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c295f31..5ccba76 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -623,6 +623,9 @@ static float64 roundAndPackFloat64(flag zSign, int zExp= , uint64_t zSig, case float_round_down: roundIncrement =3D zSign ? 0x3ff : 0; break; + case float_round_to_odd: + roundIncrement =3D (zSig & 0x400) ? 0 : 0x3ff; + break; default: abort(); } @@ -632,8 +635,10 @@ static float64 roundAndPackFloat64(flag zSign, int zEx= p, uint64_t zSig, || ( ( zExp =3D=3D 0x7FD ) && ( (int64_t) ( zSig + roundIncrement ) < 0 ) ) ) { + bool overflow_to_inf =3D roundingMode !=3D float_round_to_odd = && + roundIncrement !=3D 0; float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat64( zSign, 0x7FF, - ( roundIncrement =3D=3D 0 = )); + return packFloat64(zSign, 0x7FF, -(!overflow_to_inf)); } if ( zExp < 0 ) { if (status->flush_to_zero) { @@ -651,6 +656,13 @@ static float64 roundAndPackFloat64(flag zSign, int zEx= p, uint64_t zSig, if (isTiny && roundBits) { float_raise(float_flag_underflow, status); } + if (roundingMode =3D=3D float_round_to_odd) { + /* + * For round-to-odd case, the roundIncrement depends on + * zSig which just changed. + */ + roundIncrement =3D (zSig & 0x400) ? 0 : 0x3ff; + } } } if (roundBits) { @@ -1149,6 +1161,9 @@ static float128 roundAndPackFloat128(flag zSign, int3= 2_t zExp, case float_round_down: increment =3D zSign && zSig2; break; + case float_round_to_odd: + increment =3D !(zSig1 & 0x1) && zSig2; + break; default: abort(); } @@ -1168,6 +1183,7 @@ static float128 roundAndPackFloat128(flag zSign, int3= 2_t zExp, if ( ( roundingMode =3D=3D float_round_to_zero ) || ( zSign && ( roundingMode =3D=3D float_round_up ) ) || ( ! zSign && ( roundingMode =3D=3D float_round_down ) ) + || (roundingMode =3D=3D float_round_to_odd) ) { return packFloat128( @@ -1215,6 +1231,9 @@ static float128 roundAndPackFloat128(flag zSign, int3= 2_t zExp, case float_round_down: increment =3D zSign && zSig2; break; + case float_round_to_odd: + increment =3D !(zSig1 & 0x1) && zSig2; + break; default: abort(); } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 842ec6b..8a39028 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -180,6 +180,8 @@ enum { float_round_up =3D 2, float_round_to_zero =3D 3, float_round_ties_away =3D 4, + /* Not an IEEE rounding mode: round to the closest odd mantissa value = */ + float_round_to_odd =3D 5, }; =20 /*------------------------------------------------------------------------= ---- --=20 2.9.3