From nobody Tue Feb 10 01:15:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487021299437445.34663527517; Mon, 13 Feb 2017 13:28:19 -0800 (PST) Received: from localhost ([::1]:59608 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdOAS-00069O-Sx for importer@patchew.org; Mon, 13 Feb 2017 16:28:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45250) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdO8W-0004ha-8e for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cdO8U-0001Kv-Cp for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:16 -0500 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:34302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cdO8U-0001KZ-7s for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:14 -0500 Received: by mail-qk0-x243.google.com with SMTP id e1so16760847qkh.1 for ; Mon, 13 Feb 2017 13:26:14 -0800 (PST) Received: from bigtime.twiddle.net.com ([1.129.9.91]) by smtp.gmail.com with ESMTPSA id h40sm8311480qtb.6.2017.02.13.13.26.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Feb 2017 13:26:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=LRcS0tsxjo7kYt9AAD/rwJdjjBW3qAybyzvhe+k1U5o=; b=f1wILiHoMXx6hI8ZM4HAHkO0djFpfQYUIh/FdORaOLshKCoMSF5r+CNmhD80p92mtN sg+9ZRVfh5vkfhONU7fPdA7hGIbDd50sb0H2VLiKW1Ltw2W5QL9t6V3z0zyCBwP59BIr ix1eGchR9K9verxRqIMVMvrWUtWwOJGRJdDTZWXRXtDX08RQHFYtWqzbMN+iMPP28tX8 KOU6p2a84eDXNLL7/S/FADQv1l1YDz4m3wL5AQPISe3B32gUDK4qwgAUqdB7lI8J2kuh dN94NoC5mYykmxEw0OizQx23JnvcjvUJ5sEu1gTP7NFV4KfA6fdrr/NRcoO6qjt/qkQn O6yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=LRcS0tsxjo7kYt9AAD/rwJdjjBW3qAybyzvhe+k1U5o=; b=HCfiu3L0SgGlTOKwBa7kfQCgmJyJKE0o6flwBly0JrAOYxMZloFC0Jt/eIeF+o1j/C cv4mj26xk9pdHVUMnkgEPDUeHTeLidEtPAvbp2wo1Ti7qp1r23B/5DhuVEOHOoXXsfJ4 fi6AQ+m5VihIuNmFXuovf8jeNPvKuhExru8x1yBxHliUf01X31eCZ1PhmPVEvEy+53Wn EzPNvjzSL2Rizn56wYeMbHIpHHLhKy2ejcoPSO0cx/qWCasIsRnTw2CwUPcxoEGL3HZ2 QMvMzTYD/xO9GBl9X1lSaS7N1DfTMCXT+VRp5RoO0Iiv3K9uMNpjqfKbjOR51mayXV9J FzBQ== X-Gm-Message-State: AMke39n/7CXRA6h8+4hGr4XGU8ngo5xggsrG6sT6Il+M/44KW2SJ43IWpsKWimqRK2e67w== X-Received: by 10.55.40.27 with SMTP id o27mr2715403qkh.221.1487021173669; Mon, 13 Feb 2017 13:26:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 14 Feb 2017 08:25:20 +1100 Message-Id: <20170213212536.31871-9-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170213212536.31871-1-rth@twiddle.net> References: <20170213212536.31871-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PULL 08/24] target/openrisc: Rationalize immediate extraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The architecture manual is consistent in using "I" for signed fields and "K" for unsigned fields. Mirror that. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 98 ++++++++++++++++++-----------------------= ---- 1 file changed, 40 insertions(+), 58 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ac0c409..d999d2f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -129,23 +129,6 @@ static inline void wb_SR_F(void) gen_set_label(label); } =20 -static inline int zero_extend(unsigned int val, int width) -{ - return val & ((1 << width) - 1); -} - -static inline int sign_extend(unsigned int val, int width) -{ - int sval; - - /* LSL */ - val <<=3D TARGET_LONG_BITS - width; - sval =3D val; - /* ASR. */ - sval >>=3D TARGET_LONG_BITS - width; - return sval; -} - static inline void gen_sync_flags(DisasContext *dc) { /* Sync the tb dependent flag between translate and runtime. */ @@ -221,11 +204,9 @@ static void gen_goto_tb(DisasContext *dc, int n, targe= t_ulong dest) } } =20 -static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_= t op0) +static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t= op0) { - target_ulong tmp_pc; - /* N26, 26bits imm */ - tmp_pc =3D sign_extend((imm<<2), 26) + dc->pc; + target_ulong tmp_pc =3D dc->pc + n26 * 4; =20 switch (op0) { case 0x00: /* l.j */ @@ -760,8 +741,8 @@ static void dec_misc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1; uint32_t ra, rb, rd; - uint32_t L6, K5; - uint32_t I16, I5, I11, N26, tmp; + uint32_t L6, K5, K16, K5_11; + int32_t I16, I5_11, N26; TCGMemOp mop; =20 op0 =3D extract32(insn, 26, 6); @@ -771,11 +752,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn) rd =3D extract32(insn, 21, 5); L6 =3D extract32(insn, 5, 6); K5 =3D extract32(insn, 0, 5); - I16 =3D extract32(insn, 0, 16); - I5 =3D extract32(insn, 21, 5); - I11 =3D extract32(insn, 0, 11); - N26 =3D extract32(insn, 0, 26); - tmp =3D (I5<<11) + I11; + K16 =3D extract32(insn, 0, 16); + I16 =3D (int16_t)K16; + N26 =3D sextract32(insn, 0, 26); + K5_11 =3D (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); + I5_11 =3D (int16_t)K5_11; =20 switch (op0) { case 0x00: /* l.j */ @@ -821,12 +802,12 @@ static void dec_misc(DisasContext *dc, uint32_t insn) break; =20 case 0x13: /* l.maci */ - LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I11); + LOG_DIS("l.maci r%d, %d\n", ra, I16); { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); TCGv_i32 dst =3D tcg_temp_new_i32(); - TCGv ttmp =3D tcg_const_tl(tmp); + TCGv ttmp =3D tcg_const_tl(I16); tcg_gen_mul_tl(dst, cpu_R[ra], ttmp); tcg_gen_ext_i32_i64(t1, dst); tcg_gen_concat_i32_i64(t2, maclo, machi); @@ -936,7 +917,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn) do_load: { TCGv t0 =3D tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); + tcg_gen_addi_tl(t0, cpu_R[ra], I16); tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); tcg_temp_free(t0); } @@ -954,7 +935,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn) TCGv_i32 res =3D tcg_temp_local_new_i32(); TCGv_i32 sr_ove =3D tcg_temp_local_new_i32(); tcg_gen_extu_i32_i64(ta, cpu_R[ra]); - tcg_gen_addi_i64(td, ta, sign_extend(I16, 16)); + tcg_gen_addi_i64(td, ta, I16); tcg_gen_extrl_i64_i32(res, td); tcg_gen_shri_i64(td, td, 32); tcg_gen_andi_i64(td, td, 0x3); @@ -989,7 +970,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn) tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY); tcg_gen_shri_i32(sr_cy, sr_cy, 10); tcg_gen_extu_i32_i64(tcy, sr_cy); - tcg_gen_addi_i64(td, ta, sign_extend(I16, 16)); + tcg_gen_addi_i64(td, ta, I16); tcg_gen_add_i64(td, td, tcy); tcg_gen_extrl_i64_i32(res, td); tcg_gen_shri_i64(td, td, 32); @@ -1013,18 +994,18 @@ static void dec_misc(DisasContext *dc, uint32_t insn) break; =20 case 0x29: /* l.andi */ - LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16); - tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16)); + LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, K16); + tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], K16); break; =20 case 0x2a: /* l.ori */ - LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16); - tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16)); + LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, K16); + tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], K16); break; =20 case 0x2b: /* l.xori */ LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16); - tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16)); + tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], I16); break; =20 case 0x2c: /* l.muli */ @@ -1039,12 +1020,12 @@ static void dec_misc(DisasContext *dc, uint32_t ins= n) break; =20 case 0x2d: /* l.mfspr */ - LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16); + LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, K16); { #if defined(CONFIG_USER_ONLY) return; #else - TCGv_i32 ti =3D tcg_const_i32(I16); + TCGv_i32 ti =3D tcg_const_i32(K16); if (dc->mem_idx =3D=3D MMU_USER_IDX) { gen_illegal_exception(dc); return; @@ -1056,12 +1037,12 @@ static void dec_misc(DisasContext *dc, uint32_t ins= n) break; =20 case 0x30: /* l.mtspr */ - LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11); + LOG_DIS("l.mtspr r%d, r%d, %d\n", ra, rb, K5_11); { #if defined(CONFIG_USER_ONLY) return; #else - TCGv_i32 im =3D tcg_const_i32(tmp); + TCGv_i32 im =3D tcg_const_i32(K5_11); if (dc->mem_idx =3D=3D MMU_USER_IDX) { gen_illegal_exception(dc); return; @@ -1073,38 +1054,38 @@ static void dec_misc(DisasContext *dc, uint32_t ins= n) break; =20 case 0x33: /* l.swa */ - LOG_DIS("l.swa %d, r%d, r%d, %d\n", I5, ra, rb, I11); - gen_swa(dc, cpu_R[rb], cpu_R[ra], sign_extend(tmp, 16)); + LOG_DIS("l.swa r%d, r%d, %d\n", ra, rb, I5_11); + gen_swa(dc, cpu_R[rb], cpu_R[ra], I5_11); break; =20 /* not used yet, open it when we need or64. */ /*#ifdef TARGET_OPENRISC64 case 0x34: l.sd - LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11); + LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); check_ob64s(dc); mop =3D MO_TEQ; goto do_store; #endif*/ =20 case 0x35: /* l.sw */ - LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11); + LOG_DIS("l.sw r%d, r%d, %d\n", ra, rb, I5_11); mop =3D MO_TEUL; goto do_store; =20 case 0x36: /* l.sb */ - LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11); + LOG_DIS("l.sb r%d, r%d, %d\n", ra, rb, I5_11); mop =3D MO_UB; goto do_store; =20 case 0x37: /* l.sh */ - LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11); + LOG_DIS("l.sh r%d, r%d, %d\n", ra, rb, I5_11); mop =3D MO_TEUW; goto do_store; =20 do_store: { TCGv t0 =3D tcg_temp_new(); - tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16)); + tcg_gen_addi_tl(t0, cpu_R[ra], I5_11); tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); tcg_temp_free(t0); } @@ -1172,30 +1153,32 @@ static void dec_mac(DisasContext *dc, uint32_t insn) static void dec_logic(DisasContext *dc, uint32_t insn) { uint32_t op0; - uint32_t rd, ra, L6; + uint32_t rd, ra, L6, S6; op0 =3D extract32(insn, 6, 2); rd =3D extract32(insn, 21, 5); ra =3D extract32(insn, 16, 5); L6 =3D extract32(insn, 0, 6); + S6 =3D L6 & (TARGET_LONG_BITS - 1); =20 switch (op0) { case 0x00: /* l.slli */ LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); + tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6); break; =20 case 0x01: /* l.srli */ LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); + tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6); break; =20 case 0x02: /* l.srai */ LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); break; + tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6); + break; =20 case 0x03: /* l.rori */ LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6); - tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); + tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6); break; =20 default: @@ -1306,15 +1289,14 @@ static void dec_comp(DisasContext *dc, uint32_t ins= n) =20 static void dec_compi(DisasContext *dc, uint32_t insn) { - uint32_t op0; - uint32_t ra, I16; + uint32_t op0, ra; + int32_t I16; =20 op0 =3D extract32(insn, 21, 5); ra =3D extract32(insn, 16, 5); - I16 =3D extract32(insn, 0, 16); + I16 =3D sextract32(insn, 0, 16); =20 tcg_gen_movi_i32(env_btaken, 0x0); - I16 =3D sign_extend(I16, 16); =20 switch (op0) { case 0x0: /* l.sfeqi */ --=20 2.9.3