From nobody Tue Feb 10 04:17:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487021838505995.3188162685018; Mon, 13 Feb 2017 13:37:18 -0800 (PST) Received: from localhost ([::1]:59658 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdOJB-00064b-3q for importer@patchew.org; Mon, 13 Feb 2017 16:37:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45630) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdO90-00059F-LE for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cdO8y-0001eO-KL for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:46 -0500 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:36612) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cdO8y-0001e7-Ew for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:44 -0500 Received: by mail-qk0-x243.google.com with SMTP id p22so8994315qka.3 for ; Mon, 13 Feb 2017 13:26:44 -0800 (PST) Received: from bigtime.twiddle.net.com ([1.129.9.91]) by smtp.gmail.com with ESMTPSA id h40sm8311480qtb.6.2017.02.13.13.26.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Feb 2017 13:26:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=o1E6lbFHLe2WhvoftVcH9awVV+Muzu8WsMx8GfjIiOg=; b=eSkjlGG3u5VYs1EUQ/1uBOpMZ+u97B8S+e6aKi3CfTEo/OEyCMDMuUDgLLujrK+zSX /zv+g8YQuQ3yvUyWDCGGri8gCysqwCDps+tFH+1J8p3g5VeU+64vxnrla1iQP5lS1gJ3 iAFKMwwuRAgDoNSA+Nh+ya/ZZA1mqdD+bzR+/tgAbkRe5hJusYk26ATchPOUQMYyEe51 L3Pl1+IfkUbHKLAghGrwuRz3OyMTm7JjKZgmWcGwOJcrlU6rrVEApvRA4PCD/Bo5zDzP Jhj6rxWOyIpLxifP1Cp1RKESvte8fdiY2D2kdJ8u564QxDEhDawcLlsNP+Liq9GghFV5 VKHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=o1E6lbFHLe2WhvoftVcH9awVV+Muzu8WsMx8GfjIiOg=; b=XpB2zJl21w3Ha5HH4o7xEIzpNqSEnkjfz43hVgj3ZN3SkJ2Kgc1kE8vO8sHEY5IV2A EwwjkLYQbqUNWLcO7ggsBufpp7/D8p6p5tMzLq2mkzJ1Ow7r9lIUm30bA/TdTbdAVthi fMnYJLUr1nZxoe/7c3BnA2OBVCJkfTXc2QTksf4ahHKdbRWYAd4u0Wef3Cvt7kl9Dx5f tGEqYjaWsgDtVzFI1b0Y31OEuS/paO7y201pn/tAf/XlEk2Z7wfpaJcZHTy6kGQOJThz sfvbrmxNS6Aum5xHfUjmIh0C5/Qd9NqEDHLS8YfWM/cqgVFtyGaY9aO+dk6y3IR5VfC6 yzmA== X-Gm-Message-State: AMke39kz8i/m+wUteRE3ttvv2hx8QZGxIq81TW5M6wIRkw+kOTsyrBAvjn13lR3lVhUPiQ== X-Received: by 10.55.215.23 with SMTP id m23mr9859664qki.30.1487021203751; Mon, 13 Feb 2017 13:26:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 14 Feb 2017 08:25:32 +1100 Message-Id: <20170213212536.31871-21-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170213212536.31871-1-rth@twiddle.net> References: <20170213212536.31871-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PULL 20/24] target/openrisc: Fix madd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 3 -- target/openrisc/fpu_helper.c | 68 ++++++++++++++++------------------------= ---- target/openrisc/helper.h | 7 ++--- target/openrisc/translate.c | 13 +++------ 4 files changed, 30 insertions(+), 61 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9528277..0694038 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -279,9 +279,6 @@ typedef struct CPUOpenRISCState { =20 uint64_t mac; /* Multiply registers MACHI:MACLO */ =20 - target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI = */ - target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO = */ - target_ulong epcr; /* Exception PC register */ target_ulong eear; /* Exception EA register */ =20 diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index c54404b..1375cea 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -146,52 +146,32 @@ FLOAT_CALC(div) FLOAT_CALC(rem) #undef FLOAT_CALC =20 -#define FLOAT_TERNOP(name1, name2) \ -uint64_t helper_float_ ## name1 ## name2 ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, \ - uint64_t fdt1) \ -{ \ - uint64_t result, temp, hi, lo; \ - uint32_t val1, val2; \ - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); = \ - hi =3D env->fpmaddhi; = \ - lo =3D env->fpmaddlo; = \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - result =3D float64_ ## name1(fdt0, fdt1, &cpu->env.fp_status); = \ - lo &=3D 0xffffffff; = \ - hi &=3D 0xffffffff; = \ - temp =3D (hi << 32) | lo; = \ - result =3D float64_ ## name2(result, temp, &cpu->env.fp_status); = \ - val1 =3D result >> 32; = \ - val2 =3D (uint32_t) (result & 0xffffffff); = \ - update_fpcsr(cpu); \ - cpu->env.fpmaddlo =3D val2; = \ - cpu->env.fpmaddhi =3D val1; = \ - return 0; \ -} \ - \ -uint32_t helper_float_ ## name1 ## name2 ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ -{ \ - uint64_t result, temp, hi, lo; \ - uint32_t val1, val2; \ - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); = \ - hi =3D cpu->env.fpmaddhi; = \ - lo =3D cpu->env.fpmaddlo; = \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - result =3D float64_ ## name1(fdt0, fdt1, &cpu->env.fp_status); = \ - temp =3D (hi << 32) | lo; = \ - result =3D float64_ ## name2(result, temp, &cpu->env.fp_status); = \ - val1 =3D result >> 32; = \ - val2 =3D (uint32_t) (result & 0xffffffff); = \ - update_fpcsr(cpu); \ - cpu->env.fpmaddlo =3D val2; = \ - cpu->env.fpmaddhi =3D val1; = \ - return 0; \ + +uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, + uint64_t b, uint64_t c) +{ + OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); + uint64_t result; + set_float_exception_flags(0, &cpu->env.fp_status); + /* Note that or1ksim doesn't use merged operation. */ + result =3D float64_mul(b, c, &cpu->env.fp_status); + result =3D float64_add(result, a, &cpu->env.fp_status); + update_fpcsr(cpu); + return result; } =20 -FLOAT_TERNOP(mul, add) -#undef FLOAT_TERNOP +uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, + uint32_t b, uint32_t c) +{ + OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); + uint32_t result; + set_float_exception_flags(0, &cpu->env.fp_status); + /* Note that or1ksim doesn't use merged operation. */ + result =3D float32_mul(b, c, &cpu->env.fp_status); + result =3D float32_add(result, a, &cpu->env.fp_status); + update_fpcsr(cpu); + return result; +} =20 =20 #define FLOAT_CMP(name) \ diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index 78a123d..4fd1a6b 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -29,11 +29,8 @@ DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32) DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32) =20 -#define FOP_MADD(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32)= \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) -FOP_MADD(muladd) -#undef FOP_MADD +DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64) =20 #define FOP_CALC(op) \ DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32)= \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ce9672e..66064e1 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -61,7 +61,6 @@ static TCGv cpu_lock_addr; static TCGv cpu_lock_value; static TCGv_i32 fpcsr; static TCGv_i64 cpu_mac; /* MACHI:MACLO */ -static TCGv fpmaddhi, fpmaddlo; static TCGv_i32 env_flags; #include "exec/gen-icount.h" =20 @@ -108,12 +107,6 @@ void openrisc_translate_init(void) cpu_mac =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUOpenRISCState, mac), "mac"); - fpmaddhi =3D tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, fpmaddhi), - "fpmaddhi"); - fpmaddlo =3D tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, fpmaddlo), - "fpmaddlo"); for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, gpr[i]), @@ -1324,7 +1317,8 @@ static void dec_float(DisasContext *dc, uint32_t insn) =20 case 0x07: /* lf.madd.s */ LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); - gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]= ); + gen_helper_float_madd_s(cpu_R[rd], cpu_env, cpu_R[rd], + cpu_R[ra], cpu_R[rb]); break; =20 case 0x08: /* lf.sfeq.s */ @@ -1409,7 +1403,8 @@ static void dec_float(DisasContext *dc, uint32_t insn) case 0x17: lf.madd.d LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); - gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]= ); + gen_helper_float_madd_d(cpu_R[rd], cpu_env, cpu_R[rd], + cpu_R[ra], cpu_R[rb]); break; =20 case 0x18: lf.sfeq.d --=20 2.9.3