From nobody Mon Feb 9 22:39:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487022228050949.7617481775815; Mon, 13 Feb 2017 13:43:48 -0800 (PST) Received: from localhost ([::1]:59688 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdOPQ-0004NQ-6W for importer@patchew.org; Mon, 13 Feb 2017 16:43:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdO8h-0004rZ-DP for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cdO8e-0001Ro-Qw for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:27 -0500 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:33860) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cdO8e-0001RT-Lo for qemu-devel@nongnu.org; Mon, 13 Feb 2017 16:26:24 -0500 Received: by mail-qt0-x241.google.com with SMTP id w20so14930709qtb.1 for ; Mon, 13 Feb 2017 13:26:24 -0800 (PST) Received: from bigtime.twiddle.net.com ([1.129.9.91]) by smtp.gmail.com with ESMTPSA id h40sm8311480qtb.6.2017.02.13.13.26.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Feb 2017 13:26:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=907k1F4ue88qIue2lcRJ/jNamk0QFbk60njn9TrdETA=; b=sH6Yuz0t/7cWtH91jms1IxY6d8f8Mk59Q0rnWWJdqGi4U7Rv81ofcSM/k2Zf7/P9UB I88eLQekwdkQ3Sh7hz5B3wiad0jz55uSeSuox0xFglYmK6fo4F+WbPtv203VtMkBhR1E Y8OALhl7jFLF3EWtm2rSvWccCOC6ADUZsTupWgjhfjKAORp0Hx2F7Lw0NtCYqMK15I7p 9QPh1FHypyTpaSUHB58VKaZZMZX1eeT5JUZLZWWdFk8aibejPMAG5QP/qO8zzoWMEMs0 L5+CzMyBQ4rUM7ErH+TGavm9bqjKzXh3gHTQBiy1euBWqchHOLxQ6y8Y7/wsxET6/dru z0cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=907k1F4ue88qIue2lcRJ/jNamk0QFbk60njn9TrdETA=; b=kq/LuvJMPq5Ft2Y6PXMkE+LHRzXEAtPFK6ayUvBgp8gitQCe8GQ6mdrAw6bj+xD6Lk cim2cI7knC8V+VUUKzqTafd9a2d3WFJqNRceezvmPXe5FZDpbR0JaY3+xWIcr+zJYCLS 11m/ciP0ajywTU/Lt1IOlyKxFkY3pLub3nwgjWh7oOjqPJf9DB1P3SbhanDTGWm0G0Qh tx9WYbuCKLcFbnTf8aRDcn748mqLkrJLa6N3NUF8Aa6dGzua97D/EkcVkz/VP/XLLhfe i69LJEvhwEajisFKqA19GWqDOv3nOwyaoL2J7WOYTIT64yeu7yaDPIm1BET3aw3yd+Nl LJmA== X-Gm-Message-State: AMke39kJYexsHze1xrqwocG76MzwKDp2HUAZSQaKKhsksMX/EDFCBV0rjNbkMR7NXfByOg== X-Received: by 10.200.54.10 with SMTP id m10mr22240308qtb.63.1487021183910; Mon, 13 Feb 2017 13:26:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 14 Feb 2017 08:25:24 +1100 Message-Id: <20170213212536.31871-13-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170213212536.31871-1-rth@twiddle.net> References: <20170213212536.31871-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PULL 12/24] target/openrisc: Keep SR_F in a separate variable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This avoids having to keep merging and extracting the flag from SR. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- linux-user/elfload.c | 3 +- linux-user/main.c | 3 +- target/openrisc/cpu.h | 15 +++++- target/openrisc/gdbstub.c | 4 +- target/openrisc/interrupt.c | 2 +- target/openrisc/interrupt_helper.c | 2 +- target/openrisc/machine.c | 38 +++++++++++++- target/openrisc/sys_helper.c | 5 +- target/openrisc/translate.c | 104 ++++++++++++++-------------------= ---- 9 files changed, 98 insertions(+), 78 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c66cbbe..8271227 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1054,9 +1054,8 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, for (i =3D 0; i < 32; i++) { (*regs)[i] =3D tswapreg(env->gpr[i]); } - (*regs)[32] =3D tswapreg(env->pc); - (*regs)[33] =3D tswapreg(env->sr); + (*regs)[33] =3D tswapreg(cpu_get_sr(env)); } #define ELF_HWCAP 0 #define ELF_PLATFORM NULL diff --git a/linux-user/main.c b/linux-user/main.c index 001f71c..4fd49ce 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4765,9 +4765,8 @@ int main(int argc, char **argv, char **envp) for (i =3D 0; i < 32; i++) { env->gpr[i] =3D regs->gpr[i]; } - - env->sr =3D regs->sr; env->pc =3D regs->pc; + cpu_set_sr(env, regs->sr); } #elif defined(TARGET_SH4) { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index ef90e49..bb5d363 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -286,7 +286,8 @@ typedef struct CPUOpenRISCState { target_ulong epcr; /* Exception PC register */ target_ulong eear; /* Exception EA register */ =20 - uint32_t sr; /* Supervisor register */ + target_ulong sr_f; /* the SR_F bit, values 0, 1. */ + uint32_t sr; /* Supervisor register, without SR_F */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ @@ -301,7 +302,6 @@ typedef struct CPUOpenRISCState { =20 uint32_t flags; /* cpu_flags, we only use it for exception in solt so far. */ - uint32_t btaken; /* the SR_F bit */ =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -412,6 +412,17 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env,= bool ifetch) return (env->sr & SR_SM) =3D=3D 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } =20 +static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) +{ + return env->sr + env->sr_f * SR_F; +} + +static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) +{ + env->sr_f =3D (val & SR_F) !=3D 0; + env->sr =3D (val & ~SR_F) | SR_FO; +} + #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 =20 #endif /* OPENRISC_CPU_H */ diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index cb16e76..31ea013 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -38,7 +38,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t = *mem_buf, int n) return gdb_get_reg32(mem_buf, env->npc); =20 case 34: /* SR */ - return gdb_get_reg32(mem_buf, env->sr); + return gdb_get_reg32(mem_buf, cpu_get_sr(env)); =20 default: break; @@ -73,7 +73,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) break; =20 case 34: /* SR */ - env->sr =3D tmp; + cpu_set_sr(env, tmp); break; =20 default: diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index a981638..042506f 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -54,7 +54,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) we need flush TLB when we enter&exit EXCP. */ tlb_flush(cs); =20 - env->esr =3D env->sr; + env->esr =3D cpu_get_sr(env); env->sr &=3D ~SR_DME; env->sr &=3D ~SR_IME; env->sr |=3D SR_SM; diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt= _helper.c index a6d4df3..c7fa97a 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -33,7 +33,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) #endif cpu->env.pc =3D cpu->env.epcr; cpu->env.npc =3D cpu->env.epcr; - cpu->env.sr =3D cpu->env.esr; + cpu_set_sr(&cpu->env, cpu->env.esr); cpu->env.lock_addr =3D -1; =20 #ifndef CONFIG_USER_ONLY diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index d0b47ef..b723138 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,6 +24,27 @@ #include "hw/boards.h" #include "migration/cpu.h" =20 +static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *fi= eld) +{ + CPUOpenRISCState *env =3D opaque; + cpu_set_sr(env, qemu_get_be32(f)); + return 0; +} + +static int put_sr(QEMUFile *f, void *opaque, size_t size, + VMStateField *field, QJSON *vmdesc) +{ + CPUOpenRISCState *env =3D opaque; + qemu_put_be32(f, cpu_get_sr(env)); + return 0; +} + +static const VMStateInfo vmstate_sr =3D { + .name =3D "sr", + .get =3D get_sr, + .put =3D put_sr, +}; + static const VMStateDescription vmstate_env =3D { .name =3D "env", .version_id =3D 2, @@ -38,7 +59,22 @@ static const VMStateDescription vmstate_env =3D { VMSTATE_UINTTL(lock_value, CPUOpenRISCState), VMSTATE_UINTTL(epcr, CPUOpenRISCState), VMSTATE_UINTTL(eear, CPUOpenRISCState), - VMSTATE_UINT32(sr, CPUOpenRISCState), + + /* Save the architecture value of the SR, not the internally + expanded version. Since this architecture value does not + exist in memory to be stored, this requires a but of hoop + jumping. We want OFFSET=3D0 so that we effectively pass ENV + to the helper functions, and we need to fill in the name by + hand since there's no field of that name. */ + { + .name =3D "sr", + .version_id =3D 0, + .size =3D sizeof(uint32_t), + .info =3D &vmstate_sr, + .flags =3D VMS_SINGLE, + .offset =3D 0 + }, + VMSTATE_UINT32(vr, CPUOpenRISCState), VMSTATE_UINT32(upr, CPUOpenRISCState), VMSTATE_UINT32(cpucfgr, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index daea902..4a59728 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -49,8 +49,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, (rb & (SR_IME | SR_DME | SR_SM))) { tlb_flush(cs); } - env->sr =3D rb; - env->sr |=3D SR_FO; /* FO is const equal to 1 */ + cpu_set_sr(env, rb); if (env->sr & SR_DME) { env->tlb->cpu_openrisc_map_address_data =3D &cpu_openrisc_get_phys_data; @@ -200,7 +199,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->npc; =20 case TO_SPR(0, 17): /* SR */ - return env->sr; + return cpu_get_sr(env); =20 case TO_SPR(0, 18): /* PPC */ return env->ppc; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 1f3f22c..405a1a0 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -54,7 +54,7 @@ static TCGv cpu_pc; static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ static TCGv cpu_npc; static TCGv cpu_ppc; -static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */ +static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ static TCGv cpu_lock_addr; static TCGv cpu_lock_value; static TCGv_i32 fpcsr; @@ -88,9 +88,8 @@ void openrisc_translate_init(void) offsetof(CPUOpenRISCState, ppc), "ppc"); jmp_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, jmp_pc), "jmp_p= c"); - env_btaken =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUOpenRISCState, btaken), - "btaken"); + cpu_sr_f =3D tcg_global_mem_new(cpu_env, + offsetof(CPUOpenRISCState, sr_f), "sr_f"= ); cpu_lock_addr =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, lock_add= r), "lock_addr"); @@ -119,16 +118,6 @@ void openrisc_translate_init(void) } } =20 -/* Writeback SR_F translation space to execution space. */ -static inline void wb_SR_F(void) -{ - TCGLabel *label =3D gen_new_label(); - tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F); - tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label); - tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F); - gen_set_label(label); -} - static inline void gen_sync_flags(DisasContext *dc) { /* Sync the tb dependent flag between translate and runtime. */ @@ -220,14 +209,11 @@ static void gen_jump(DisasContext *dc, int32_t n26, u= int32_t reg, uint32_t op0) case 0x04: /* l.bf */ { TCGLabel *lab =3D gen_new_label(); - TCGv sr_f =3D tcg_temp_new(); tcg_gen_movi_tl(jmp_pc, dc->pc+8); - tcg_gen_andi_tl(sr_f, cpu_sr, SR_F); - tcg_gen_brcondi_i32(op0 =3D=3D 0x03 ? TCG_COND_EQ : TCG_COND_N= E, - sr_f, SR_F, lab); + tcg_gen_brcondi_tl(op0 =3D=3D 0x03 ? TCG_COND_NE : TCG_COND_EQ, + cpu_sr_f, 0, lab); tcg_gen_movi_tl(jmp_pc, tmp_pc); gen_set_label(lab); - tcg_temp_free(sr_f); } break; case 0x11: /* l.jr */ @@ -441,17 +427,16 @@ static void gen_swa(DisasContext *dc, TCGv rb, TCGv r= a, int32_t ofs) val =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, rb, dc->mem_idx, MO_TEUL); - tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, val, cpu_lock_value); + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); tcg_temp_free(val); =20 tcg_gen_br(lab_done); =20 gen_set_label(lab_fail); - tcg_gen_movi_tl(env_btaken, 0); + tcg_gen_movi_tl(cpu_sr_f, 0); =20 gen_set_label(lab_done); tcg_gen_movi_tl(cpu_lock_addr, -1); - wb_SR_F(); } =20 static void dec_calc(DisasContext *dc, uint32_t insn) @@ -558,14 +543,11 @@ static void dec_calc(DisasContext *dc, uint32_t insn) { TCGLabel *lab =3D gen_new_label(); TCGv res =3D tcg_temp_local_new(); - TCGv sr_f =3D tcg_temp_new(); - tcg_gen_andi_tl(sr_f, cpu_sr, SR_F); tcg_gen_mov_tl(res, cpu_R[rb]); - tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_sr_f, 0, lab); tcg_gen_mov_tl(res, cpu_R[ra]); gen_set_label(lab); tcg_gen_mov_tl(cpu_R[rd], res); - tcg_temp_free(sr_f); tcg_temp_free(res); } return; @@ -1046,7 +1028,6 @@ static void dec_comp(DisasContext *dc, uint32_t insn) ra =3D extract32(insn, 16, 5); rb =3D extract32(insn, 11, 5); =20 - tcg_gen_movi_i32(env_btaken, 0x0); /* unsigned integers */ tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]); tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]); @@ -1054,59 +1035,58 @@ static void dec_comp(DisasContext *dc, uint32_t ins= n) switch (op0) { case 0x0: /* l.sfeq */ LOG_DIS("l.sfeq r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0x1: /* l.sfne */ LOG_DIS("l.sfne r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0x2: /* l.sfgtu */ LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0x3: /* l.sfgeu */ LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0x4: /* l.sfltu */ LOG_DIS("l.sfltu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0x5: /* l.sfleu */ LOG_DIS("l.sfleu r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0xa: /* l.sfgts */ LOG_DIS("l.sfgts r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0xb: /* l.sfges */ LOG_DIS("l.sfges r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0xc: /* l.sflts */ LOG_DIS("l.sflts r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 case 0xd: /* l.sfles */ LOG_DIS("l.sfles r%d, r%d\n", ra, rb); - tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]); + tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); break; =20 default: gen_illegal_exception(dc); break; } - wb_SR_F(); } =20 static void dec_compi(DisasContext *dc, uint32_t insn) @@ -1118,64 +1098,61 @@ static void dec_compi(DisasContext *dc, uint32_t in= sn) ra =3D extract32(insn, 16, 5); I16 =3D sextract32(insn, 0, 16); =20 - tcg_gen_movi_i32(env_btaken, 0x0); - switch (op0) { case 0x0: /* l.sfeqi */ LOG_DIS("l.sfeqi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0x1: /* l.sfnei */ LOG_DIS("l.sfnei r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0x2: /* l.sfgtui */ LOG_DIS("l.sfgtui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0x3: /* l.sfgeui */ LOG_DIS("l.sfgeui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0x4: /* l.sfltui */ LOG_DIS("l.sfltui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0x5: /* l.sfleui */ LOG_DIS("l.sfleui r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0xa: /* l.sfgtsi */ LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0xb: /* l.sfgesi */ LOG_DIS("l.sfgesi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0xc: /* l.sfltsi */ LOG_DIS("l.sfltsi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], I16); break; =20 case 0xd: /* l.sflesi */ LOG_DIS("l.sflesi r%d, %d\n", ra, I16); - tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16); + tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], I16); break; =20 default: gen_illegal_exception(dc); break; } - wb_SR_F(); } =20 static void dec_sys(DisasContext *dc, uint32_t insn) @@ -1308,32 +1285,32 @@ static void dec_float(DisasContext *dc, uint32_t in= sn) =20 case 0x08: /* lf.sfeq.s */ LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb); - gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x09: /* lf.sfne.s */ LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb); - gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_ne_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x0a: /* lf.sfgt.s */ LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb); - gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_gt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x0b: /* lf.sfge.s */ LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb); - gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_ge_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x0c: /* lf.sflt.s */ LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb); - gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x0d: /* lf.sfle.s */ LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb); - gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 /* not used yet, open it when we need or64. */ @@ -1394,37 +1371,37 @@ static void dec_float(DisasContext *dc, uint32_t in= sn) case 0x18: lf.sfeq.d LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x1a: lf.sfgt.d LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_gt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x1b: lf.sfge.d LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_ge_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x19: lf.sfne.d LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_ne_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x1c: lf.sflt.d LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; =20 case 0x1d: lf.sfle.d LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); break; #endif*/ =20 @@ -1432,7 +1409,6 @@ static void dec_float(DisasContext *dc, uint32_t insn) gen_illegal_exception(dc); break; } - wb_SR_F(); } =20 static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) --=20 2.9.3