From nobody Mon Feb 9 12:25:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486616591466825.0355053313583; Wed, 8 Feb 2017 21:03:11 -0800 (PST) Received: from localhost ([::1]:35559 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbgsw-00034f-3D for importer@patchew.org; Thu, 09 Feb 2017 00:03:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbgj8-0002Zp-0T for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:53:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbgj6-0007zb-Ni for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:53:02 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:35960) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cbgj6-0007ye-G1 for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:53:00 -0500 Received: by mail-pg0-x243.google.com with SMTP id 75so16791742pgf.3 for ; Wed, 08 Feb 2017 20:53:00 -0800 (PST) Received: from bigtime.home ([1.128.80.123]) by smtp.gmail.com with ESMTPSA id b75sm24202832pfb.90.2017.02.08.20.52.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Feb 2017 20:52:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=6toDeGKdX3CXyF7D8WrTwQb4Ku+A6/WjSffQ/EWrH/4=; b=iQPhYgMqTU+UCrMeLrlsc1k6mUG30uGpmN7wD4yfDMVOBuUhD7YJJbVerPMWqlQCsz 3PB2Q0dKTL4Jql6wHb8iIwV+N2u6JnZ0M+QGf9pxRXDahCCDlmU5SeIVtqk0vO3xJtOk 2eUiGqDF7HMO982UQwTgk0yhIGcoogJhcAiU4MalBYCLHW2yIYxfySRFri2HsLuqkWiV j8gKm+Wrx8x+2gZo0MEawswa90TwQZVzARnM7WNuhVtcOZCvJZZExDR5cdjSIte0ElaO RQCx8e3pSCoDWnG8N+pASff/Lno/CxlXfKR7+zyM3m8IXQIHzrjumE4UJzbu9b1xTiWR ryTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=6toDeGKdX3CXyF7D8WrTwQb4Ku+A6/WjSffQ/EWrH/4=; b=HQwobYG34oaM5adh+f6KMb5zN5NYOAYoB80HWeOENMggeTbtLm720z+bJUFi8NfhmM XsSsF9ov1vPwA9gU1cnc10HiKx0rlw4/bPNZv36Fa8hEPgvyMNrSa9JPtMexopRLSblE wGFZ2AIn8yYecxcgtRmOudso0CEBW08VnzMWv2LyLgj03FC3BWnH7lYtpjsIFMDrH0bP T3q6BNoxDVdy9rv1SURngRUsa2fqTOPkbCup6piqkCrHXTjG6BOrYgncN1GrfK32km1k m6teX/0Q9mW12/mMjlzCQVs7bm/aGzr8fu7F5y6tddk6nEinROpmpB8kaZBfvvTUARdV heJQ== X-Gm-Message-State: AMke39lNTROhv+HEb2bDSOBM8R3xXkSCY/gPbfAgzGQDnL1CRboF3rDvlcfzthLNKWlH5Q== X-Received: by 10.98.71.7 with SMTP id u7mr1535215pfa.76.1486615979406; Wed, 08 Feb 2017 20:52:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Feb 2017 20:51:51 -0800 Message-Id: <20170209045154.16868-20-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170209045154.16868-1-rth@twiddle.net> References: <20170209045154.16868-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 19/22] target/openrisc: Fix madd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 3 -- target/openrisc/fpu_helper.c | 68 ++++++++++++++++------------------------= ---- target/openrisc/helper.h | 7 ++--- target/openrisc/translate.c | 13 +++------ 4 files changed, 30 insertions(+), 61 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 1ee1210..6426e32 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -279,9 +279,6 @@ typedef struct CPUOpenRISCState { =20 uint64_t mac; /* Multiply registers MACHI:MACLO */ =20 - target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI = */ - target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO = */ - target_ulong epcr; /* Exception PC register */ target_ulong eear; /* Exception EA register */ =20 diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index c54404b..1375cea 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -146,52 +146,32 @@ FLOAT_CALC(div) FLOAT_CALC(rem) #undef FLOAT_CALC =20 -#define FLOAT_TERNOP(name1, name2) \ -uint64_t helper_float_ ## name1 ## name2 ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, \ - uint64_t fdt1) \ -{ \ - uint64_t result, temp, hi, lo; \ - uint32_t val1, val2; \ - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); = \ - hi =3D env->fpmaddhi; = \ - lo =3D env->fpmaddlo; = \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - result =3D float64_ ## name1(fdt0, fdt1, &cpu->env.fp_status); = \ - lo &=3D 0xffffffff; = \ - hi &=3D 0xffffffff; = \ - temp =3D (hi << 32) | lo; = \ - result =3D float64_ ## name2(result, temp, &cpu->env.fp_status); = \ - val1 =3D result >> 32; = \ - val2 =3D (uint32_t) (result & 0xffffffff); = \ - update_fpcsr(cpu); \ - cpu->env.fpmaddlo =3D val2; = \ - cpu->env.fpmaddhi =3D val1; = \ - return 0; \ -} \ - \ -uint32_t helper_float_ ## name1 ## name2 ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ -{ \ - uint64_t result, temp, hi, lo; \ - uint32_t val1, val2; \ - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); = \ - hi =3D cpu->env.fpmaddhi; = \ - lo =3D cpu->env.fpmaddlo; = \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - result =3D float64_ ## name1(fdt0, fdt1, &cpu->env.fp_status); = \ - temp =3D (hi << 32) | lo; = \ - result =3D float64_ ## name2(result, temp, &cpu->env.fp_status); = \ - val1 =3D result >> 32; = \ - val2 =3D (uint32_t) (result & 0xffffffff); = \ - update_fpcsr(cpu); \ - cpu->env.fpmaddlo =3D val2; = \ - cpu->env.fpmaddhi =3D val1; = \ - return 0; \ + +uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, + uint64_t b, uint64_t c) +{ + OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); + uint64_t result; + set_float_exception_flags(0, &cpu->env.fp_status); + /* Note that or1ksim doesn't use merged operation. */ + result =3D float64_mul(b, c, &cpu->env.fp_status); + result =3D float64_add(result, a, &cpu->env.fp_status); + update_fpcsr(cpu); + return result; } =20 -FLOAT_TERNOP(mul, add) -#undef FLOAT_TERNOP +uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, + uint32_t b, uint32_t c) +{ + OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); + uint32_t result; + set_float_exception_flags(0, &cpu->env.fp_status); + /* Note that or1ksim doesn't use merged operation. */ + result =3D float32_mul(b, c, &cpu->env.fp_status); + result =3D float32_add(result, a, &cpu->env.fp_status); + update_fpcsr(cpu); + return result; +} =20 =20 #define FLOAT_CMP(name) \ diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index 78a123d..4fd1a6b 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -29,11 +29,8 @@ DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32) DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32) =20 -#define FOP_MADD(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32)= \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) -FOP_MADD(muladd) -#undef FOP_MADD +DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64) =20 #define FOP_CALC(op) \ DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32)= \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ce9672e..66064e1 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -61,7 +61,6 @@ static TCGv cpu_lock_addr; static TCGv cpu_lock_value; static TCGv_i32 fpcsr; static TCGv_i64 cpu_mac; /* MACHI:MACLO */ -static TCGv fpmaddhi, fpmaddlo; static TCGv_i32 env_flags; #include "exec/gen-icount.h" =20 @@ -108,12 +107,6 @@ void openrisc_translate_init(void) cpu_mac =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUOpenRISCState, mac), "mac"); - fpmaddhi =3D tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, fpmaddhi), - "fpmaddhi"); - fpmaddlo =3D tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, fpmaddlo), - "fpmaddlo"); for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, gpr[i]), @@ -1324,7 +1317,8 @@ static void dec_float(DisasContext *dc, uint32_t insn) =20 case 0x07: /* lf.madd.s */ LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); - gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]= ); + gen_helper_float_madd_s(cpu_R[rd], cpu_env, cpu_R[rd], + cpu_R[ra], cpu_R[rb]); break; =20 case 0x08: /* lf.sfeq.s */ @@ -1409,7 +1403,8 @@ static void dec_float(DisasContext *dc, uint32_t insn) case 0x17: lf.madd.d LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); - gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]= ); + gen_helper_float_madd_d(cpu_R[rd], cpu_env, cpu_R[rd], + cpu_R[ra], cpu_R[rb]); break; =20 case 0x18: lf.sfeq.d --=20 2.9.3