From nobody Mon Feb 9 14:02:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 148661639808286.18068600058234; Wed, 8 Feb 2017 20:59:58 -0800 (PST) Received: from localhost ([::1]:35538 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbgpn-0008Tk-IV for importer@patchew.org; Wed, 08 Feb 2017 23:59:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38126) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbgir-0002Li-4O for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbgim-0007pr-NY for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:45 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:36030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cbgim-0007pf-Fe for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:40 -0500 Received: by mail-pf0-x244.google.com with SMTP id 19so12928147pfo.3 for ; Wed, 08 Feb 2017 20:52:40 -0800 (PST) Received: from bigtime.home ([1.128.80.123]) by smtp.gmail.com with ESMTPSA id b75sm24202832pfb.90.2017.02.08.20.52.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Feb 2017 20:52:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=8LtZSWHe2KugH4DLkAkKczHhvH7Jcu7d/uv7Rt5GrZY=; b=HEnsCvzaz0Z3Vxyn8qqmlVotVwbR60UY+TZJTDCklsAMXVsUHjdLvtJKm6RzG/LwkO b3KyTE+9Y3XC/h9Fw1KvktwDzSQLh629nb8rNv/DQIJMeGecMLouACyjvA4CG2hufrB8 ibVCuMjl2cW2glq5+nidu+OPPsROoWXpgvee6EL7hDKo4eTuwCuL3xmVVqgAhhHQo6Wk IQmG5mr7gZFIuarhFTy+c4Mm9gNw8USPTljhqS5z1MHyDRv6BzOBqmQn32CHABJWLUDa GBaGC8q/6G+xgGUwzvxjhWn99h637lUOzlIGeLtG3Wl77I2Z22LdauQMlHBlDIuBHNGK F7rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=8LtZSWHe2KugH4DLkAkKczHhvH7Jcu7d/uv7Rt5GrZY=; b=MPqBVwo2htE4YeuvLbiOZ3rBsxlnodVXSJfHwlXccRwCh/1xvcTgUpz9PITpXyk6On PaIOE+ijBnagyjyIvZXZdBocDNkMSpCw7jz0wm/N7K395sS3g1YcQHuQEZ3BN+W1bF+7 ExaKpomvYr6fnQoFmSWM6SiaFp/vTSNX6RfrFv8mJbu8q10FLuu9MVe1CBt6pjoCg6iN p2QBfmrqpP/oJ1vDqV2O6LXJR5lhJXs/Qx63TZxKeqh6hmq8yLSQpdWd9GDBKkH7QGK+ QrqZb1SLolREpAdpXHmCiCygR93CMOZIE5m0TMZTHkd64WQKUzYfZeLGXalmzuaX+v14 gxKA== X-Gm-Message-State: AMke39n/SblRxeRlMUfWNO82UMHX5b58TXONVCoOsWnrb+Yw1PI1gmjQ1GQpirCs93RHWA== X-Received: by 10.84.194.129 with SMTP id h1mr1668676pld.70.1486615959525; Wed, 08 Feb 2017 20:52:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Feb 2017 20:51:44 -0800 Message-Id: <20170209045154.16868-13-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170209045154.16868-1-rth@twiddle.net> References: <20170209045154.16868-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH 12/22] target/openrisc: Keep SR_CY and SR_OV in a separate variables X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This significantly streamlines carry and overflow production. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 13 +++- target/openrisc/exception_helper.c | 31 ++++++++-- target/openrisc/helper.h | 4 +- target/openrisc/translate.c | 119 +++++++++++++--------------------= ---- 4 files changed, 78 insertions(+), 89 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9e349f9..82b87b3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -287,7 +287,9 @@ typedef struct CPUOpenRISCState { target_ulong eear; /* Exception EA register */ =20 target_ulong sr_f; /* the SR_F bit, values 0, 1. */ - uint32_t sr; /* Supervisor register, without SR_F */ + target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ + target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ + uint32_t sr; /* Supervisor register, without SR_{F,CY,OV}= */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ @@ -414,13 +416,18 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env= , bool ifetch) =20 static inline uint32_t cpu_get_sr(CPUOpenRISCState *env) { - return env->sr + env->sr_f * SR_F; + return (env->sr + + env->sr_f * SR_F + + env->sr_cy * SR_CY + + (env->sr_ov < 0) * SR_OV); } =20 static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) { env->sr_f =3D (val & SR_F) !=3D 0; - env->sr =3D (val & ~SR_F) | SR_FO; + env->sr_cy =3D (val & SR_CY) !=3D 0; + env->sr_ov =3D (val & SR_OV ? -1 : 0); + env->sr =3D (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; } =20 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception= _helper.c index 5147da6..1536053 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -30,13 +30,32 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t = excp) raise_exception(cpu, excp); } =20 -void HELPER(ove)(CPUOpenRISCState *env, target_ulong test) +static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc) { - if (unlikely(test)) { - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + + cs->exception_index =3D EXCP_RANGE; + cpu_loop_exit_restore(cs, pc); +} + +void HELPER(ove_cy)(CPUOpenRISCState *env) +{ + if (env->sr_cy) { + do_range(env, GETPC()); + } +} + +void HELPER(ove_ov)(CPUOpenRISCState *env) +{ + if (env->sr_ov < 0) { + do_range(env, GETPC()); + } +} =20 - cs->exception_index =3D EXCP_RANGE; - cpu_loop_exit_restore(cs, GETPC()); +void HELPER(ove_cyov)(CPUOpenRISCState *env) +{ + if (env->sr_cy || env->sr_ov < 0) { + do_range(env, GETPC()); } } diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index c2c8098..f4d97a2 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -19,7 +19,9 @@ =20 /* exception */ DEF_HELPER_FLAGS_2(exception, 0, void, env, i32) -DEF_HELPER_FLAGS_2(ove, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_1(ove_cy, TCG_CALL_NO_WG, void, env) +DEF_HELPER_FLAGS_1(ove_ov, TCG_CALL_NO_WG, void, env) +DEF_HELPER_FLAGS_1(ove_cyov, TCG_CALL_NO_WG, void, env) =20 /* float */ DEF_HELPER_FLAGS_2(itofd, 0, i64, env, i64) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 405a1a0..6c745d3 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -55,6 +55,8 @@ static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ static TCGv cpu_npc; static TCGv cpu_ppc; static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ +static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ +static TCGv cpu_sr_ov; /* signed overflow */ static TCGv cpu_lock_addr; static TCGv cpu_lock_value; static TCGv_i32 fpcsr; @@ -90,6 +92,10 @@ void openrisc_translate_init(void) offsetof(CPUOpenRISCState, jmp_pc), "jmp_p= c"); cpu_sr_f =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, sr_f), "sr_f"= ); + cpu_sr_cy =3D tcg_global_mem_new(cpu_env, + offsetof(CPUOpenRISCState, sr_cy), "sr_= cy"); + cpu_sr_ov =3D tcg_global_mem_new(cpu_env, + offsetof(CPUOpenRISCState, sr_ov), "sr_= ov"); cpu_lock_addr =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, lock_add= r), "lock_addr"); @@ -233,27 +239,24 @@ static void gen_jump(DisasContext *dc, int32_t n26, u= int32_t reg, uint32_t op0) gen_sync_flags(dc); } =20 -static void gen_ove_cy(DisasContext *dc, TCGv cy) +static void gen_ove_cy(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { - gen_helper_ove(cpu_env, cy); + gen_helper_ove_cy(cpu_env); } } =20 -static void gen_ove_ov(DisasContext *dc, TCGv ov) +static void gen_ove_ov(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { - gen_helper_ove(cpu_env, ov); + gen_helper_ove_ov(cpu_env); } } =20 -static void gen_ove_cyov(DisasContext *dc, TCGv cy, TCGv ov) +static void gen_ove_cyov(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_or_tl(t0, cy, ov); - gen_helper_ove(cpu_env, t0); - tcg_temp_free(t0); + gen_helper_ove_cyov(cpu_env); } } =20 @@ -261,143 +264,101 @@ static void gen_add(DisasContext *dc, TCGv dest, TC= Gv srca, TCGv srcb) { TCGv t0 =3D tcg_const_tl(0); TCGv res =3D tcg_temp_new(); - TCGv sr_cy =3D tcg_temp_new(); - TCGv sr_ov =3D tcg_temp_new(); =20 - tcg_gen_add2_tl(res, sr_cy, srca, t0, srcb, t0); - tcg_gen_xor_tl(sr_ov, srca, srcb); + tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0); + tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); - tcg_gen_andc_tl(sr_ov, t0, sr_ov); + tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); tcg_temp_free(t0); =20 tcg_gen_mov_tl(dest, res); tcg_temp_free(res); =20 - tcg_gen_shri_tl(sr_ov, sr_ov, TARGET_LONG_BITS - 1); - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_cy, ctz32(SR_CY), 1); - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_ov, ctz32(SR_OV), 1); - - gen_ove_cyov(dc, sr_ov, sr_cy); - tcg_temp_free(sr_ov); - tcg_temp_free(sr_cy); + gen_ove_cyov(dc); } =20 static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { TCGv t0 =3D tcg_const_tl(0); TCGv res =3D tcg_temp_new(); - TCGv sr_cy =3D tcg_temp_new(); - TCGv sr_ov =3D tcg_temp_new(); - - tcg_gen_shri_tl(sr_cy, cpu_sr, ctz32(SR_CY)); - tcg_gen_andi_tl(sr_cy, sr_cy, 1); =20 - tcg_gen_add2_tl(res, sr_cy, srca, t0, sr_cy, t0); - tcg_gen_add2_tl(res, sr_cy, res, sr_cy, srcb, t0); - tcg_gen_xor_tl(sr_ov, srca, srcb); + tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0); + tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0); + tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); - tcg_gen_andc_tl(sr_ov, t0, sr_ov); + tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); tcg_temp_free(t0); =20 tcg_gen_mov_tl(dest, res); tcg_temp_free(res); =20 - tcg_gen_shri_tl(sr_ov, sr_ov, TARGET_LONG_BITS - 1); - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_cy, ctz32(SR_CY), 1); - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_ov, ctz32(SR_OV), 1); - - gen_ove_cyov(dc, sr_ov, sr_cy); - tcg_temp_free(sr_ov); - tcg_temp_free(sr_cy); + gen_ove_cyov(dc); } =20 static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { TCGv res =3D tcg_temp_new(); - TCGv sr_cy =3D tcg_temp_new(); - TCGv sr_ov =3D tcg_temp_new(); =20 tcg_gen_sub_tl(res, srca, srcb); - tcg_gen_xor_tl(sr_cy, srca, srcb); - tcg_gen_xor_tl(sr_ov, res, srcb); - tcg_gen_and_tl(sr_ov, sr_ov, sr_cy); - tcg_gen_setcond_tl(TCG_COND_LTU, sr_cy, srca, srcb); + tcg_gen_xor_tl(cpu_sr_cy, srca, srcb); + tcg_gen_xor_tl(cpu_sr_ov, res, srcb); + tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); + tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); =20 tcg_gen_mov_tl(dest, res); tcg_temp_free(res); =20 - tcg_gen_shri_tl(sr_ov, sr_ov, TARGET_LONG_BITS - 1); - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_cy, ctz32(SR_CY), 1); - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_ov, ctz32(SR_OV), 1); - - gen_ove_cyov(dc, sr_ov, sr_cy); - tcg_temp_free(sr_ov); - tcg_temp_free(sr_cy); + gen_ove_cyov(dc); } =20 static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv sr_ov =3D tcg_temp_new(); TCGv t0 =3D tcg_temp_new(); =20 - tcg_gen_muls2_tl(dest, sr_ov, srca, srcb); + tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); - tcg_gen_setcond_tl(TCG_COND_NE, sr_ov, sr_ov, t0); + tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); tcg_temp_free(t0); =20 - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_ov, ctz32(SR_OV), 1); - - gen_ove_ov(dc, sr_ov); - tcg_temp_free(sr_ov); + tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); + gen_ove_ov(dc); } =20 static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv sr_cy =3D tcg_temp_new(); - - tcg_gen_muls2_tl(dest, sr_cy, srca, srcb); - tcg_gen_setcondi_tl(TCG_COND_NE, sr_cy, sr_cy, 0); - - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_cy, ctz32(SR_CY), 1); + tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); =20 - gen_ove_cy(dc, sr_cy); - tcg_temp_free(sr_cy); + gen_ove_cy(dc); } =20 static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv sr_ov =3D tcg_temp_new(); TCGv t0 =3D tcg_temp_new(); =20 - tcg_gen_setcondi_tl(TCG_COND_EQ, sr_ov, srcb, 0); + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); /* The result of divide-by-zero is undefined. Supress the host-side exception by dividing by 1. */ - tcg_gen_or_tl(t0, srcb, sr_ov); + tcg_gen_or_tl(t0, srcb, cpu_sr_ov); tcg_gen_div_tl(dest, srca, t0); tcg_temp_free(t0); =20 - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_ov, ctz32(SR_OV), 1); - - gen_ove_ov(dc, sr_ov); - tcg_temp_free(sr_ov); + tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); + gen_ove_ov(dc); } =20 static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv sr_cy =3D tcg_temp_new(); TCGv t0 =3D tcg_temp_new(); =20 - tcg_gen_setcondi_tl(TCG_COND_EQ, sr_cy, srcb, 0); + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); /* The result of divide-by-zero is undefined. Supress the host-side exception by dividing by 1. */ - tcg_gen_or_tl(t0, srcb, sr_cy); + tcg_gen_or_tl(t0, srcb, cpu_sr_cy); tcg_gen_divu_tl(dest, srca, t0); tcg_temp_free(t0); =20 - tcg_gen_deposit_tl(cpu_sr, cpu_sr, sr_cy, ctz32(SR_CY), 1); - - gen_ove_cy(dc, sr_cy); - tcg_temp_free(sr_cy); + gen_ove_cy(dc); } =20 static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) --=20 2.9.3