From nobody Mon Feb 9 07:56:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 14866161450321001.7210993427216; Wed, 8 Feb 2017 20:55:45 -0800 (PST) Received: from localhost ([::1]:35518 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbglj-0004HJ-Pf for importer@patchew.org; Wed, 08 Feb 2017 23:55:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbgih-0002GE-QX for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbgig-0007mH-55 for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:35 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:34376) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cbgif-0007m9-UE for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:34 -0500 Received: by mail-pf0-x241.google.com with SMTP id y143so12939453pfb.1 for ; Wed, 08 Feb 2017 20:52:33 -0800 (PST) Received: from bigtime.home ([1.128.80.123]) by smtp.gmail.com with ESMTPSA id b75sm24202832pfb.90.2017.02.08.20.52.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Feb 2017 20:52:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=UzADiAzev3tRhpnZ/B3cyqMiFjt1ptp6pudSlYWd5Ts=; b=nhBGUfROIPWr5aeZr3BdVaquls0aEaOZr+eyesoQz/kDMP4mNB4SIL5ewFv5C6J7A7 i6tk3bjsvLtBgS3FVJVaYl/Jpxhen7uWpk2VMlSUMJ+2OTDQ6qsULXtzPK/Ka9BDVBB9 pmwxmVkgTVQlcF1y0dFQFyEKBDWWCn0LweBlNAJctOszP3YivhX9s1rh/aNK0WV6q5LZ arBICppIe32X/NMk03JrrNr6fW1s/R45TFL+Li3Z/oWPs4vb8w7nnDzzlb5L/G/Ty0h0 N93drJZM51rQr/ORhfHPX7UQWCg4dy89O/qr08QmWZz6gw2/6sI82itijjBH2/2AuvlF DIdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=UzADiAzev3tRhpnZ/B3cyqMiFjt1ptp6pudSlYWd5Ts=; b=TJGCR+dif78qb5CMH+mZ20rj5NlaGt7J5Q0+vfLKOubKuV4Y7nc0LQbiu4KRgKq/OF kdIzMrwya3o/+QKNRoG8ogY/QU66TQaHS5lqqcNDY75m1kW4kaZxuC4YTE11cKmPpsaU nlpxJPjnCyfoHuTiCaIUazr7QwCdRCNQXN01p5CCrIGidh765h8LkLb0vRoV2jHGRGAa myJR1B69ds6rocSHR9/WehQhW0C3e2HSe3dQo65u/BeqalsYD8nFmiWZMbsZ8rNNku0J iynbvscShmM1fMHFr5v/d33F9n6lMndtU3iZtdmQTA7fqfguWByPlLmC50t5Ddmh3aYu RJZA== X-Gm-Message-State: AMke39k/JAwKN6W/0P35WRbbaCO33qhDq472hnPM4O5nIkJAn5QgQ4JnuGoDikZVt/pN0Q== X-Received: by 10.99.163.2 with SMTP id s2mr1613681pge.43.1486615952852; Wed, 08 Feb 2017 20:52:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Feb 2017 20:51:42 -0800 Message-Id: <20170209045154.16868-11-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170209045154.16868-1-rth@twiddle.net> References: <20170209045154.16868-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH 10/22] target/openrisc: Invert the decoding in dec_calc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Decoding the opcodes in the right order reduces by 100+ lines. Also, it happens to put the opcodes in the same order as Chapter 17. Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 302 ++++++++++++++--------------------------= ---- 1 file changed, 95 insertions(+), 207 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index b8116ba..1f3f22c 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -465,133 +465,95 @@ static void dec_calc(DisasContext *dc, uint32_t insn) rb =3D extract32(insn, 11, 5); rd =3D extract32(insn, 21, 5); =20 - switch (op0) { - case 0x0000: - switch (op1) { - case 0x00: /* l.add */ + switch (op1) { + case 0: + switch (op0) { + case 0x0: /* l.add */ LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb); gen_add(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - default: - gen_illegal_exception(dc); - break; - } - break; + return; =20 - case 0x0001: /* l.addc */ - switch (op1) { - case 0x00: + case 0x1: /* l.addc */ LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb); gen_addc(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - default: - gen_illegal_exception(dc); - break; - } - break; + return; =20 - case 0x0002: /* l.sub */ - switch (op1) { - case 0x00: + case 0x2: /* l.sub */ LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb); gen_sub(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - default: - gen_illegal_exception(dc); - break; - } - break; + return; =20 - case 0x0003: /* l.and */ - switch (op1) { - case 0x00: + case 0x3: /* l.and */ LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb); tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - default: - gen_illegal_exception(dc); - break; - } - break; + return; =20 - case 0x0004: /* l.or */ - switch (op1) { - case 0x00: + case 0x4: /* l.or */ LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb); tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - default: - gen_illegal_exception(dc); - break; - } - break; + return; =20 - case 0x0005: - switch (op1) { - case 0x00: /* l.xor */ + case 0x5: /* l.xor */ LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb); tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - default: - gen_illegal_exception(dc); - break; - } - break; - - case 0x0006: - switch (op1) { - case 0x03: /* l.mul */ - LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb); - gen_mul(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - default: - gen_illegal_exception(dc); - break; - } - break; - - case 0x0009: - switch (op1) { - case 0x03: /* l.div */ - LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb); - gen_div(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - - default: - gen_illegal_exception(dc); - break; - } - break; - - case 0x000a: - switch (op1) { - case 0x03: /* l.divu */ - LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb); - gen_divu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; + return; =20 - default: - gen_illegal_exception(dc); + case 0x8: + switch (op2) { + case 0: /* l.sll */ + LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb); + tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); + return; + case 1: /* l.srl */ + LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb); + tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); + return; + case 2: /* l.sra */ + LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb); + tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); + return; + case 3: /* l.ror */ + LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb); + tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); + return; + } break; - } - break; =20 - case 0x000b: - switch (op1) { - case 0x03: /* l.mulu */ - LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb); - gen_mulu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + case 0xc: + switch (op2) { + case 0: /* l.exths */ + LOG_DIS("l.exths r%d, r%d\n", rd, ra); + tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]); + return; + case 1: /* l.extbs */ + LOG_DIS("l.extbs r%d, r%d\n", rd, ra); + tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]); + return; + case 2: /* l.exthz */ + LOG_DIS("l.exthz r%d, r%d\n", rd, ra); + tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]); + return; + case 3: /* l.extbz */ + LOG_DIS("l.extbz r%d, r%d\n", rd, ra); + tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]); + return; + } break; =20 - default: - gen_illegal_exception(dc); + case 0xd: + switch (op2) { + case 0: /* l.extws */ + LOG_DIS("l.extws r%d, r%d\n", rd, ra); + tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]); + return; + case 1: /* l.extwz */ + LOG_DIS("l.extwz r%d, r%d\n", rd, ra); + tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]); + return; + } break; - } - break; =20 - case 0x000e: - switch (op1) { - case 0x00: /* l.cmov */ + case 0xe: /* l.cmov */ LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb); { TCGLabel *lab =3D gen_new_label(); @@ -606,128 +568,54 @@ static void dec_calc(DisasContext *dc, uint32_t insn) tcg_temp_free(sr_f); tcg_temp_free(res); } - break; - - default: - gen_illegal_exception(dc); - break; - } - break; + return; =20 - case 0x000f: - switch (op1) { - case 0x00: /* l.ff1 */ + case 0xf: /* l.ff1 */ LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb); tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1); tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1); - break; - case 0x01: /* l.fl1 */ + return; + } + break; + + case 1: + switch (op0) { + case 0xf: /* l.fl1 */ LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb); tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS); tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]); - break; - - default: - gen_illegal_exception(dc); - break; + return; } break; =20 - case 0x0008: - switch (op1) { - case 0x00: - switch (op2) { - case 0x00: /* l.sll */ - LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - case 0x01: /* l.srl */ - LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - case 0x02: /* l.sra */ - LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - case 0x03: /* l.ror */ - LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb); - tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); - break; - - default: - gen_illegal_exception(dc); - break; - } - break; - - default: - gen_illegal_exception(dc); - break; - } + case 2: break; =20 - case 0x000c: - switch (op1) { - case 0x00: - switch (op2) { - case 0x00: /* l.exths */ - LOG_DIS("l.exths r%d, r%d\n", rd, ra); - tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]); - break; - case 0x01: /* l.extbs */ - LOG_DIS("l.extbs r%d, r%d\n", rd, ra); - tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]); - break; - case 0x02: /* l.exthz */ - LOG_DIS("l.exthz r%d, r%d\n", rd, ra); - tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]); - break; - case 0x03: /* l.extbz */ - LOG_DIS("l.extbz r%d, r%d\n", rd, ra); - tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]); - break; - - default: - gen_illegal_exception(dc); - break; - } - break; - - default: - gen_illegal_exception(dc); - break; - } - break; + case 3: + switch (op0) { + case 0x6: /* l.mul */ + LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb); + gen_mul(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + return; =20 - case 0x000d: - switch (op1) { - case 0x00: - switch (op2) { - case 0x00: /* l.extws */ - LOG_DIS("l.extws r%d, r%d\n", rd, ra); - tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]); - break; - case 0x01: /* l.extwz */ - LOG_DIS("l.extwz r%d, r%d\n", rd, ra); - tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]); - break; + case 0x9: /* l.div */ + LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb); + gen_div(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + return; =20 - default: - gen_illegal_exception(dc); - break; - } - break; + case 0xa: /* l.divu */ + LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb); + gen_divu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + return; =20 - default: - gen_illegal_exception(dc); - break; + case 0xb: /* l.mulu */ + LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb); + gen_mulu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + return; } break; - - default: - gen_illegal_exception(dc); - break; } + gen_illegal_exception(dc); } =20 static void dec_misc(DisasContext *dc, uint32_t insn) --=20 2.9.3