From nobody Mon Feb 9 12:25:51 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486617034684857.2620894429648; Wed, 8 Feb 2017 21:10:34 -0800 (PST) Received: from localhost ([::1]:35595 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbh05-0001PE-Al for importer@patchew.org; Thu, 09 Feb 2017 00:10:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38044) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbgif-0002Dy-A4 for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbgic-0007kv-MB for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:33 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:36019) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cbgic-0007kp-H2 for qemu-devel@nongnu.org; Wed, 08 Feb 2017 23:52:30 -0500 Received: by mail-pf0-x243.google.com with SMTP id 19so12927882pfo.3 for ; Wed, 08 Feb 2017 20:52:30 -0800 (PST) Received: from bigtime.home ([1.128.80.123]) by smtp.gmail.com with ESMTPSA id b75sm24202832pfb.90.2017.02.08.20.52.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Feb 2017 20:52:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=NAeV/9Hl3z0Laf8P0LzXu0AtY3X7ErTyEMIoGp94IvM=; b=ZpHlZsl+hQjISVzVKKzgmZwLwuMDBLbyzCWl0UtYw1av+PZjincpOPazbqvJ6ojPOZ aRDxjCaZiImN/BW5o116uMqHjCSlaB59EaIwDC/wMKTTEFsxSHHvGtzwCVZa/vAysQd/ zH02np74hU6gPPzkOccq1y0+3Cb/0z8JBey/EY/sBU3eapc+Qj6XLtyrGBFjI0haJJjt qR+r8Xyqv/74NaveanZIjmnm488TL4SpY7P4NOGOVQ5bG924dM9NS1Uy7AkRmx6JPhnP mielFGaY/eeTd58ADjEklWstmcNkv7wMsRGREedC58ywHRqiy3b7QV8k7m+dne9XHO3Z gZzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=NAeV/9Hl3z0Laf8P0LzXu0AtY3X7ErTyEMIoGp94IvM=; b=bcR8Zy0V2Z5M0tK1W7PHKO46SZ8YUH6xbzvbh8+6wGTSTOzFP+ucGJZLP9CBncYpHa FIC1sUCXbXBPwRz/Hi0VqaGGhSBBv1EvqwCuyQByxXxV4BUPHQ3Q+cKaG1eaPnZ8yAAC QNEw+GzptEoZNkSW7vcdJQRytVDPC2iowBOCLBQoFAFCfbqm537akEY6a5YQzsWW28KU XrHsx3i+uUZFih/ndUiWSVJ6HeitpFoXemk8JOUpCGmUH5jQVb7jvvF5/Z2ABeYo9uLt 5fEC4l9qJ378hWB7qJhGdEG1Ejqejz6mSmYhOypJv0DyPDSTacQLpApy8cHTPrNB+gnq cIbQ== X-Gm-Message-State: AMke39mldyJJ386bbRx6UUT1hBiTPfhA4Xrkad1bbcocJd4obFMR8yIOOm8LyPU3UYZWIQ== X-Received: by 10.99.95.151 with SMTP id t145mr1559997pgb.75.1486615949561; Wed, 08 Feb 2017 20:52:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Feb 2017 20:51:41 -0800 Message-Id: <20170209045154.16868-10-rth@twiddle.net> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170209045154.16868-1-rth@twiddle.net> References: <20170209045154.16868-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 09/22] target/openrisc: Put SR[OVE] in TB flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Removes a call at execution time for overflow exceptions. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 4 ++-- target/openrisc/exception_helper.c | 2 +- target/openrisc/translate.c | 24 +++++++++++++++--------- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 06d0e89..ef90e49 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -400,8 +400,8 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCStat= e *env, { *pc =3D env->pc; *cs_base =3D 0; - /* D_FLAG -- branch instruction exception */ - *flags =3D (env->flags & D_FLAG); + /* D_FLAG -- branch instruction exception, OVE overflow trap enable. = */ + *flags =3D (env->flags & D_FLAG) | (env->sr & SR_OVE); } =20 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception= _helper.c index 7e54c97..5147da6 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -32,7 +32,7 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t ex= cp) =20 void HELPER(ove)(CPUOpenRISCState *env, target_ulong test) { - if (unlikely(test) && (env->sr & SR_OVE)) { + if (unlikely(test)) { OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); CPUState *cs =3D CPU(cpu); =20 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c6cd1c..b8116ba 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -132,8 +132,8 @@ static inline void wb_SR_F(void) static inline void gen_sync_flags(DisasContext *dc) { /* Sync the tb dependent flag between translate and runtime. */ - if (dc->tb_flags !=3D dc->synced_flags) { - tcg_gen_movi_tl(env_flags, dc->tb_flags); + if ((dc->tb_flags ^ dc->synced_flags) & D_FLAG) { + tcg_gen_movi_tl(env_flags, dc->tb_flags & D_FLAG); dc->synced_flags =3D dc->tb_flags; } } @@ -249,20 +249,26 @@ static void gen_jump(DisasContext *dc, int32_t n26, u= int32_t reg, uint32_t op0) =20 static void gen_ove_cy(DisasContext *dc, TCGv cy) { - gen_helper_ove(cpu_env, cy); + if (dc->tb_flags & SR_OVE) { + gen_helper_ove(cpu_env, cy); + } } =20 static void gen_ove_ov(DisasContext *dc, TCGv ov) { - gen_helper_ove(cpu_env, ov); + if (dc->tb_flags & SR_OVE) { + gen_helper_ove(cpu_env, ov); + } } =20 static void gen_ove_cyov(DisasContext *dc, TCGv cy, TCGv ov) { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_or_tl(t0, cy, ov); - gen_helper_ove(cpu_env, t0); - tcg_temp_free(t0); + if (dc->tb_flags & SR_OVE) { + TCGv t0 =3D tcg_temp_new(); + tcg_gen_or_tl(t0, cy, ov); + gen_helper_ove(cpu_env, t0); + tcg_temp_free(t0); + } } =20 static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) @@ -1606,7 +1612,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) dc->flags =3D cpu->env.cpucfgr; dc->mem_idx =3D cpu_mmu_index(&cpu->env, false); dc->synced_flags =3D dc->tb_flags =3D tb->flags; - dc->delayed_branch =3D !!(dc->tb_flags & D_FLAG); + dc->delayed_branch =3D (dc->tb_flags & D_FLAG) !=3D 0; dc->singlestep_enabled =3D cs->singlestep_enabled; =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; --=20 2.9.3