From nobody Sun May 5 01:24:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486345480446727.4931097478574; Sun, 5 Feb 2017 17:44:40 -0800 (PST) Received: from localhost ([::1]:45167 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1caYMB-00082g-7S for importer@patchew.org; Sun, 05 Feb 2017 20:44:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35335) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1caYHM-0004dR-GV for qemu-devel@nongnu.org; Sun, 05 Feb 2017 20:39:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1caYHI-00008J-8w for qemu-devel@nongnu.org; Sun, 05 Feb 2017 20:39:40 -0500 Received: from ozlabs.org ([103.22.144.67]:37899) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1caYHH-00007s-LM; Sun, 05 Feb 2017 20:39:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vGqrz540Bz9s1y; Mon, 6 Feb 2017 12:39:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1486345171; bh=GQ6OTX3sMEnj69FcJEf7/BdTWll5MFOnJDd3XlDjnAk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZGbD9dk9obNQQKdHxykqCgGQYkbh7WU0rRWNwOACfHIRgIWbta6YY9KDQignd3aDj 5+U3xsxyyAmgY29MVAj+1/+rkSm+Qs3x23AE99zGVcHccYp6sDt3Jwh31YWQl4UnWu na6ai0ODStaGghcPjRILwhI06mjwM+334qM8h58Y= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 6 Feb 2017 12:39:25 +1100 Message-Id: <20170206013927.13693-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170206013927.13693-1-david@gibson.dropbear.id.au> References: <20170206013927.13693-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 1/3] Split serial-isa into its own config option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: veroniabahaa@gmail.com, agraf@suse.de, proljc@gmail.com, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, mst@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, borntraeger@de.ibm.com, michael@walle.cc, qemu-ppc@nongnu.org, pbonzini@redhat.com, cornelia.huck@de.ibm.com, edgar.iglesias@gmail.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At present, the core device model code for 8250-like serial ports (serial.c) and the code for serial ports attached to ISA-style legacy IO (serial-isa.c) are both controlled by the CONFIG_SERIAL variable. There are lots and lots of embedded platforms that have 8250-like serial ports but have never had anything resembling ISA legacy IO. Therefore, split serial-isa into its own CONFIG_SERIAL_ISA option so it can be disabled for platforms where it's not appropriate. For now, I enabled CONFIG_SERIAL_ISA in every default-config where CONFIG_SERIAL is enabled, excepting microblaze, or32, and xtensa. As best as I can tell, those platforms never used legacy ISA, and also don't include PCI support (which would allow connection of a PCI->ISA bridge and/or a southbridge including legacy ISA serial ports). Signed-off-by: David Gibson Reviewed-by: Thomas Huth Acked-by: Christian Borntraeger Reviewed-by: Markus Armbruster Reviewed-by: Edgar E. Iglesias Reviewed-by: Michael S. Tsirkin --- default-configs/alpha-softmmu.mak | 1 + default-configs/arm-softmmu.mak | 1 + default-configs/i386-softmmu.mak | 1 + default-configs/mips-softmmu-common.mak | 1 + default-configs/moxie-softmmu.mak | 1 + default-configs/pci.mak | 1 + default-configs/ppc-softmmu.mak | 1 + default-configs/ppc64-softmmu.mak | 1 + default-configs/ppcemb-softmmu.mak | 1 + default-configs/sh4-softmmu.mak | 1 + default-configs/sh4eb-softmmu.mak | 1 + default-configs/sparc64-softmmu.mak | 1 + default-configs/x86_64-softmmu.mak | 1 + hw/char/Makefile.objs | 3 ++- 14 files changed, 15 insertions(+), 1 deletion(-) diff --git a/default-configs/alpha-softmmu.mak b/default-configs/alpha-soft= mmu.mak index 7f6161e..e0d75e3 100644 --- a/default-configs/alpha-softmmu.mak +++ b/default-configs/alpha-softmmu.mak @@ -3,6 +3,7 @@ include pci.mak include usb.mak CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_I8254=3Dy CONFIG_PCKBD=3Dy CONFIG_VGA_CIRRUS=3Dy diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 6f2a180..824fa71 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -6,6 +6,7 @@ CONFIG_VGA=3Dy CONFIG_NAND=3Dy CONFIG_ECC=3Dy CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_PTIMER=3Dy CONFIG_SD=3Dy CONFIG_MAX7310=3Dy diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmm= u.mak index 384cefb..48b07a4 100644 --- a/default-configs/i386-softmmu.mak +++ b/default-configs/i386-softmmu.mak @@ -15,6 +15,7 @@ CONFIG_IPMI_EXTERN=3Dy CONFIG_ISA_IPMI_KCS=3Dy CONFIG_ISA_IPMI_BT=3Dy CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_PARALLEL=3Dy CONFIG_I8254=3Dy CONFIG_PCSPK=3Dy diff --git a/default-configs/mips-softmmu-common.mak b/default-configs/mips= -softmmu-common.mak index f0676f5..7d8f5db 100644 --- a/default-configs/mips-softmmu-common.mak +++ b/default-configs/mips-softmmu-common.mak @@ -9,6 +9,7 @@ CONFIG_VGA_ISA_MM=3Dy CONFIG_VGA_CIRRUS=3Dy CONFIG_VMWARE_VGA=3Dy CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_PARALLEL=3Dy CONFIG_I8254=3Dy CONFIG_PCSPK=3Dy diff --git a/default-configs/moxie-softmmu.mak b/default-configs/moxie-soft= mmu.mak index 1a95476..7e22863 100644 --- a/default-configs/moxie-softmmu.mak +++ b/default-configs/moxie-softmmu.mak @@ -2,4 +2,5 @@ =20 CONFIG_MC146818RTC=3Dy CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_VGA=3Dy diff --git a/default-configs/pci.mak b/default-configs/pci.mak index fff7ce3..d8d6548 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -27,6 +27,7 @@ CONFIG_AHCI=3Dy CONFIG_ESP=3Dy CONFIG_ESP_PCI=3Dy CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_SERIAL_PCI=3Dy CONFIG_IPACK=3Dy CONFIG_WDT_IB6300ESB=3Dy diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.= mak index 7dd004e..09c1d45 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -46,6 +46,7 @@ CONFIG_PLATFORM_BUS=3Dy CONFIG_ETSEC=3Dy CONFIG_LIBDECNUMBER=3Dy # For PReP +CONFIG_SERIAL_ISA=3Dy CONFIG_MC146818RTC=3Dy CONFIG_ISA_TESTDEV=3Dy CONFIG_RS6000_MC=3Dy diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-soft= mmu.mak index 9ae6563..05c8335 100644 --- a/default-configs/ppc64-softmmu.mak +++ b/default-configs/ppc64-softmmu.mak @@ -52,6 +52,7 @@ CONFIG_XICS=3D$(CONFIG_PSERIES) CONFIG_XICS_SPAPR=3D$(CONFIG_PSERIES) CONFIG_XICS_KVM=3D$(and $(CONFIG_PSERIES),$(CONFIG_KVM)) # For PReP +CONFIG_SERIAL_ISA=3Dy CONFIG_MC146818RTC=3Dy CONFIG_ISA_TESTDEV=3Dy CONFIG_MEM_HOTPLUG=3Dy diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-so= ftmmu.mak index 54acc4d..7f56004 100644 --- a/default-configs/ppcemb-softmmu.mak +++ b/default-configs/ppcemb-softmmu.mak @@ -5,6 +5,7 @@ include sound.mak include usb.mak CONFIG_M48T59=3Dy CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_I8257=3Dy CONFIG_OPENPIC=3Dy CONFIG_PFLASH_CFI01=3Dy diff --git a/default-configs/sh4-softmmu.mak b/default-configs/sh4-softmmu.= mak index 8e00390..546d855 100644 --- a/default-configs/sh4-softmmu.mak +++ b/default-configs/sh4-softmmu.mak @@ -3,6 +3,7 @@ include pci.mak include usb.mak CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_PTIMER=3Dy CONFIG_PFLASH_CFI02=3Dy CONFIG_SH4=3Dy diff --git a/default-configs/sh4eb-softmmu.mak b/default-configs/sh4eb-soft= mmu.mak index efdd058..2d3fd49 100644 --- a/default-configs/sh4eb-softmmu.mak +++ b/default-configs/sh4eb-softmmu.mak @@ -3,6 +3,7 @@ include pci.mak include usb.mak CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_PTIMER=3Dy CONFIG_PFLASH_CFI02=3Dy CONFIG_SH4=3Dy diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-= softmmu.mak index c581e61..d07876a 100644 --- a/default-configs/sparc64-softmmu.mak +++ b/default-configs/sparc64-softmmu.mak @@ -5,6 +5,7 @@ include usb.mak CONFIG_M48T59=3Dy CONFIG_PTIMER=3Dy CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_PARALLEL=3Dy CONFIG_PCKBD=3Dy CONFIG_FDC=3Dy diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-so= ftmmu.mak index 491a191..fd96345 100644 --- a/default-configs/x86_64-softmmu.mak +++ b/default-configs/x86_64-softmmu.mak @@ -15,6 +15,7 @@ CONFIG_IPMI_EXTERN=3Dy CONFIG_ISA_IPMI_KCS=3Dy CONFIG_ISA_IPMI_BT=3Dy CONFIG_SERIAL=3Dy +CONFIG_SERIAL_ISA=3Dy CONFIG_PARALLEL=3Dy CONFIG_I8254=3Dy CONFIG_PCSPK=3Dy diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 69a553c..6ea76fe 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -2,7 +2,8 @@ common-obj-$(CONFIG_IPACK) +=3D ipoctal232.o common-obj-$(CONFIG_ESCC) +=3D escc.o common-obj-$(CONFIG_PARALLEL) +=3D parallel.o common-obj-$(CONFIG_PL011) +=3D pl011.o -common-obj-$(CONFIG_SERIAL) +=3D serial.o serial-isa.o +common-obj-$(CONFIG_SERIAL) +=3D serial.o +common-obj-$(CONFIG_SERIAL_ISA) +=3D serial-isa.o common-obj-$(CONFIG_SERIAL_PCI) +=3D serial-pci.o common-obj-$(CONFIG_VIRTIO) +=3D virtio-console.o common-obj-$(CONFIG_XILINX) +=3D xilinx_uartlite.o --=20 2.9.3 From nobody Sun May 5 01:24:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486345288415996.1077706692437; Sun, 5 Feb 2017 17:41:28 -0800 (PST) Received: from localhost ([::1]:45152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1caYJ4-0005Xp-Mc for importer@patchew.org; Sun, 05 Feb 2017 20:41:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35293) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1caYHJ-0004cY-HM for qemu-devel@nongnu.org; Sun, 05 Feb 2017 20:39:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1caYHI-00008U-FK for qemu-devel@nongnu.org; Sun, 05 Feb 2017 20:39:37 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:45887) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1caYHI-00007u-2i; Sun, 05 Feb 2017 20:39:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vGqs00qfKz9s7F; Mon, 6 Feb 2017 12:39:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1486345172; bh=DWJlLqcCPGnbqY8oVi8UgVQz8NJ04AlyAqgfJBUYrpU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DpOsvpIL2apC+t00R6TF6LNTCHcYFWcBlVajBar4ipPTnDYt8R3vIhAfNFMT8HikF n5IS6PCBhq4JyFPtAMP4N0pzKZH7qm/Rpc+5izdncZJNPcdyNjw8ITs15Zm4xM5m92 +DKO1RVa9eedcwzUEsXusZ9qbHWzQa2XMlqMdq3U= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 6 Feb 2017 12:39:26 +1100 Message-Id: <20170206013927.13693-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170206013927.13693-1-david@gibson.dropbear.id.au> References: <20170206013927.13693-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 2/3] Allow ISA bus to be configured out X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: veroniabahaa@gmail.com, agraf@suse.de, proljc@gmail.com, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, mst@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, borntraeger@de.ibm.com, michael@walle.cc, qemu-ppc@nongnu.org, pbonzini@redhat.com, cornelia.huck@de.ibm.com, edgar.iglesias@gmail.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, the code to handle the legacy ISA bus is always included in qemu. However there are lots of platforms that don't include ISA legacy devies, and quite a few that have never used ISA legacy devices at all. This patch allows the ISA bus code to be disabled in the configuration for platforms where it doesn't make sense. For now, the default configs are adjusted to include ISA on all platforms including PCI: anything with PCI can at least in principle add an i82378 PCI->ISA bridge. Also, CONFIG_IDE_CORE which is already in pci.mak requires ISA support. We also explicitly enable ISA on some other non-PCI platforms which include ISA devices: moxie, sparc and unicore32. We may want to pare this down in future. The platforms that will lose ISA by default are: cris, lm32, microblazeel, microblaze, openrisc, s390x, tricore, xtensaeb, xtensa. As far as I can tell none of these ever used ISA. Signed-off-by: David Gibson Acked-by: Michael S. Tsirkin Reviewed-by: Markus Armbruster Reviewed-by: Edgar E. Iglesias Reviewed-by: Michael S. Tsirkin --- default-configs/moxie-softmmu.mak | 1 + default-configs/pci.mak | 2 ++ default-configs/sparc-softmmu.mak | 1 + default-configs/unicore32-softmmu.mak | 1 + hw/isa/Makefile.objs | 2 +- 5 files changed, 6 insertions(+), 1 deletion(-) diff --git a/default-configs/moxie-softmmu.mak b/default-configs/moxie-soft= mmu.mak index 7e22863..e00d099 100644 --- a/default-configs/moxie-softmmu.mak +++ b/default-configs/moxie-softmmu.mak @@ -1,5 +1,6 @@ # Default configuration for moxie-softmmu =20 +CONFIG_ISA_BUS=3Dy CONFIG_MC146818RTC=3Dy CONFIG_SERIAL=3Dy CONFIG_SERIAL_ISA=3Dy diff --git a/default-configs/pci.mak b/default-configs/pci.mak index d8d6548..60dc651 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -1,4 +1,6 @@ CONFIG_PCI=3Dy +# For now, CONFIG_IDE_CORE requires ISA, so we enable it here +CONFIG_ISA_BUS=3Dy CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO=3Dy CONFIG_USB_UHCI=3Dy diff --git a/default-configs/sparc-softmmu.mak b/default-configs/sparc-soft= mmu.mak index ab796b3..004b0f4 100644 --- a/default-configs/sparc-softmmu.mak +++ b/default-configs/sparc-softmmu.mak @@ -1,5 +1,6 @@ # Default configuration for sparc-softmmu =20 +CONFIG_ISA_BUS=3Dy CONFIG_ECC=3Dy CONFIG_ESP=3Dy CONFIG_ESCC=3Dy diff --git a/default-configs/unicore32-softmmu.mak b/default-configs/unicor= e32-softmmu.mak index de38577..5f6c4a8 100644 --- a/default-configs/unicore32-softmmu.mak +++ b/default-configs/unicore32-softmmu.mak @@ -1,4 +1,5 @@ # Default configuration for unicore32-softmmu +CONFIG_ISA_BUS=3Dy CONFIG_PUV3=3Dy CONFIG_PTIMER=3Dy CONFIG_PCKBD=3Dy diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs index 9164556..fb37c55 100644 --- a/hw/isa/Makefile.objs +++ b/hw/isa/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-y +=3D isa-bus.o +common-obj-$(CONFIG_ISA_BUS) +=3D isa-bus.o common-obj-$(CONFIG_APM) +=3D apm.o common-obj-$(CONFIG_I82378) +=3D i82378.o common-obj-$(CONFIG_PC87312) +=3D pc87312.o --=20 2.9.3 From nobody Sun May 5 01:24:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486345595929395.86449876699135; Sun, 5 Feb 2017 17:46:35 -0800 (PST) Received: from localhost ([::1]:45177 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1caYO2-0000da-7b for importer@patchew.org; Sun, 05 Feb 2017 20:46:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1caYHL-0004cm-I6 for qemu-devel@nongnu.org; Sun, 05 Feb 2017 20:39:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1caYHI-00008h-SR for qemu-devel@nongnu.org; Sun, 05 Feb 2017 20:39:39 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:47745) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1caYHI-00007w-4I; Sun, 05 Feb 2017 20:39:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vGqrz6qvjz9s2s; Mon, 6 Feb 2017 12:39:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1486345171; bh=i6GW93qtu9gWqJmAI9yTTQy8nDfmM2KQKM0H7MPDW88=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KKYxASXOeRCCv4Do3d4i2P5mQADHKekC40drKxQ44MJ9vourI75P2ewtLQSdGJITZ RmoWxq3I9f9tjAlz7jJtnlVk03HqEZy4/701L3DUta1Xi+/NT97dlx77b41A8GIH/R OMDqNsEiE+DUPQTWY1wYUTPAfY0raBCR0wmhyz5w= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 6 Feb 2017 12:39:27 +1100 Message-Id: <20170206013927.13693-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170206013927.13693-1-david@gibson.dropbear.id.au> References: <20170206013927.13693-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 3/3] Split ISA and sysbus versions of m48t59 device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: veroniabahaa@gmail.com, agraf@suse.de, proljc@gmail.com, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, mst@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, borntraeger@de.ibm.com, michael@walle.cc, qemu-ppc@nongnu.org, pbonzini@redhat.com, cornelia.huck@de.ibm.com, edgar.iglesias@gmail.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The m48t59 device supports both ISA and direct sysbus attached versions of the device in the one .c file. This can be awkward for some embedded machine types which need the sysbus M48T59, but don't want to pull in the ISA bus code and its other dependencies. Therefore, this patch splits out the code for the ISA attached M48T59 into its own C file. It will be built when both CONFIG_M48T59 and CONFIG_ISA_BUS are enabled. Signed-off-by: David Gibson Reviewed-by: Edgar E. Iglesias Reviewed-by: Michael S. Tsirkin --- hw/timer/Makefile.objs | 3 + hw/timer/m48t59-internal.h | 82 ++++++++++++++++ hw/timer/m48t59-isa.c | 181 +++++++++++++++++++++++++++++++++++ hw/timer/m48t59.c | 228 ++++-------------------------------------= ---- 4 files changed, 284 insertions(+), 210 deletions(-) create mode 100644 hw/timer/m48t59-internal.h create mode 100644 hw/timer/m48t59-isa.c diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 71994f2..fc99668 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -6,6 +6,9 @@ common-obj-$(CONFIG_DS1338) +=3D ds1338.o common-obj-$(CONFIG_HPET) +=3D hpet.o common-obj-$(CONFIG_I8254) +=3D i8254_common.o i8254.o common-obj-$(CONFIG_M48T59) +=3D m48t59.o +ifeq ($(CONFIG_ISA_BUS),y) +common-obj-$(CONFIG_M48T59) +=3D m48t59-isa.o +endif common-obj-$(CONFIG_PL031) +=3D pl031.o common-obj-$(CONFIG_PUV3) +=3D puv3_ost.o common-obj-$(CONFIG_TWL92230) +=3D twl92230.o diff --git a/hw/timer/m48t59-internal.h b/hw/timer/m48t59-internal.h new file mode 100644 index 0000000..32ae957 --- /dev/null +++ b/hw/timer/m48t59-internal.h @@ -0,0 +1,82 @@ +/* + * QEMU M48T59 and M48T08 NVRAM emulation (common header) + * + * Copyright (c) 2003-2005, 2007 Jocelyn Mayer + * Copyright (c) 2013 Herv=C3=A9 Poussineau + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#ifndef HW_M48T59_INTERNAL_H +#define HW_M48T59_INTERNAL_H 1 + +//#define DEBUG_NVRAM + +#if defined(DEBUG_NVRAM) +#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while = (0) +#else +#define NVRAM_PRINTF(fmt, ...) do { } while (0) +#endif + +/* + * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has + * alarm and a watchdog timer and related control registers. In the + * PPC platform there is also a nvram lock function. + */ + +typedef struct M48txxInfo { + const char *bus_name; + uint32_t model; /* 2 =3D m48t02, 8 =3D m48t08, 59 =3D m48t59 */ + uint32_t size; +} M48txxInfo; + +typedef struct M48t59State { + /* Hardware parameters */ + qemu_irq IRQ; + MemoryRegion iomem; + uint32_t size; + int32_t base_year; + /* RTC management */ + time_t time_offset; + time_t stop_time; + /* Alarm & watchdog */ + struct tm alarm; + QEMUTimer *alrm_timer; + QEMUTimer *wd_timer; + /* NVRAM storage */ + uint8_t *buffer; + /* Model parameters */ + uint32_t model; /* 2 =3D m48t02, 8 =3D m48t08, 59 =3D m48t59 */ + /* NVRAM storage */ + uint16_t addr; + uint8_t lock; +} M48t59State; + +uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr); +void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val); +void m48t59_reset_common(M48t59State *NVRAM); +void m48t59_realize_common(M48t59State *s, Error **errp); + +static inline void m48t59_toggle_lock(M48t59State *NVRAM, int lock) +{ + NVRAM->lock ^=3D 1 << lock; +} + +extern const MemoryRegionOps m48t59_io_ops; + +#endif /* HW_M48T59_INTERNAL_H */ diff --git a/hw/timer/m48t59-isa.c b/hw/timer/m48t59-isa.c new file mode 100644 index 0000000..ea1ba70 --- /dev/null +++ b/hw/timer/m48t59-isa.c @@ -0,0 +1,181 @@ +/* + * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface + * + * Copyright (c) 2003-2005, 2007 Jocelyn Mayer + * Copyright (c) 2013 Herv=C3=A9 Poussineau + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "hw/isa/isa.h" +#include "hw/timer/m48t59.h" +#include "m48t59-internal.h" + +#define TYPE_M48TXX_ISA "isa-m48txx" +#define M48TXX_ISA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA) +#define M48TXX_ISA_CLASS(klass) \ + OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) +#define M48TXX_ISA(obj) \ + OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) + +typedef struct M48txxISAState { + ISADevice parent_obj; + M48t59State state; + uint32_t io_base; + MemoryRegion io; +} M48txxISAState; + +typedef struct M48txxISADeviceClass { + ISADeviceClass parent_class; + M48txxInfo info; +} M48txxISADeviceClass; + +static M48txxInfo m48txx_isa_info[] =3D { + { + .bus_name =3D "isa-m48t59", + .model =3D 59, + .size =3D 0x2000, + } +}; + +Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, + int base_year, int model) +{ + DeviceState *dev; + int i; + + for (i =3D 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { + if (m48txx_isa_info[i].size !=3D size || + m48txx_isa_info[i].model !=3D model) { + continue; + } + + dev =3D DEVICE(isa_create(bus, m48txx_isa_info[i].bus_name)); + qdev_prop_set_uint32(dev, "iobase", io_base); + qdev_prop_set_int32(dev, "base-year", base_year); + qdev_init_nofail(dev); + return NVRAM(dev); + } + + assert(false); + return NULL; +} + +static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) +{ + M48txxISAState *d =3D M48TXX_ISA(obj); + return m48t59_read(&d->state, addr); +} + +static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) +{ + M48txxISAState *d =3D M48TXX_ISA(obj); + m48t59_write(&d->state, addr, val); +} + +static void m48txx_isa_toggle_lock(Nvram *obj, int lock) +{ + M48txxISAState *d =3D M48TXX_ISA(obj); + m48t59_toggle_lock(&d->state, lock); +} + +static Property m48t59_isa_properties[] =3D { + DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0), + DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), + DEFINE_PROP_END_OF_LIST(), +}; + +static void m48t59_reset_isa(DeviceState *d) +{ + M48txxISAState *isa =3D M48TXX_ISA(d); + M48t59State *NVRAM =3D &isa->state; + + m48t59_reset_common(NVRAM); +} + +static void m48t59_isa_realize(DeviceState *dev, Error **errp) +{ + M48txxISADeviceClass *u =3D M48TXX_ISA_GET_CLASS(dev); + ISADevice *isadev =3D ISA_DEVICE(dev); + M48txxISAState *d =3D M48TXX_ISA(dev); + M48t59State *s =3D &d->state; + + s->model =3D u->info.model; + s->size =3D u->info.size; + isa_init_irq(isadev, &s->IRQ, 8); + m48t59_realize_common(s, errp); + memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59"= , 4); + if (d->io_base !=3D 0) { + isa_register_ioport(isadev, &d->io, d->io_base); + } +} + +static void m48txx_isa_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + NvramClass *nc =3D NVRAM_CLASS(klass); + + dc->realize =3D m48t59_isa_realize; + dc->reset =3D m48t59_reset_isa; + dc->props =3D m48t59_isa_properties; + nc->read =3D m48txx_isa_read; + nc->write =3D m48txx_isa_write; + nc->toggle_lock =3D m48txx_isa_toggle_lock; +} + +static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) +{ + M48txxISADeviceClass *u =3D M48TXX_ISA_CLASS(klass); + M48txxInfo *info =3D data; + + u->info =3D *info; +} + +static const TypeInfo m48txx_isa_type_info =3D { + .name =3D TYPE_M48TXX_ISA, + .parent =3D TYPE_ISA_DEVICE, + .instance_size =3D sizeof(M48txxISAState), + .abstract =3D true, + .class_init =3D m48txx_isa_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_NVRAM }, + { } + } +}; + +static void m48t59_isa_register_types(void) +{ + TypeInfo isa_type_info =3D { + .parent =3D TYPE_M48TXX_ISA, + .class_size =3D sizeof(M48txxISADeviceClass), + .class_init =3D m48txx_isa_concrete_class_init, + }; + int i; + + type_register_static(&m48txx_isa_type_info); + + for (i =3D 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { + isa_type_info.name =3D m48txx_isa_info[i].bus_name; + isa_type_info.class_data =3D &m48txx_isa_info[i]; + type_register(&isa_type_info); + } +} + +type_init(m48t59_isa_register_types) diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c index e46ca88..0157977 100644 --- a/hw/timer/m48t59.c +++ b/hw/timer/m48t59.c @@ -29,17 +29,10 @@ #include "qemu/timer.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" -#include "hw/isa/isa.h" #include "exec/address-spaces.h" #include "qemu/bcd.h" =20 -//#define DEBUG_NVRAM - -#if defined(DEBUG_NVRAM) -#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while = (0) -#else -#define NVRAM_PRINTF(fmt, ...) do { } while (0) -#endif +#include "m48t59-internal.h" =20 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx" #define M48TXX_SYS_BUS_GET_CLASS(obj) \ @@ -49,27 +42,6 @@ #define M48TXX_SYS_BUS(obj) \ OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS) =20 -#define TYPE_M48TXX_ISA "isa-m48txx" -#define M48TXX_ISA_GET_CLASS(obj) \ - OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA) -#define M48TXX_ISA_CLASS(klass) \ - OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) -#define M48TXX_ISA(obj) \ - OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) - -/* - * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has - * alarm and a watchdog timer and related control registers. In the - * PPC platform there is also a nvram lock function. - */ - -typedef struct M48txxInfo { - const char *isa_name; - const char *sysbus_name; - uint32_t model; /* 2 =3D m48t02, 8 =3D m48t08, 59 =3D m48t59 */ - uint32_t size; -} M48txxInfo; - /* * Chipset docs: * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf @@ -77,40 +49,6 @@ typedef struct M48txxInfo { * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf */ =20 -typedef struct M48t59State { - /* Hardware parameters */ - qemu_irq IRQ; - MemoryRegion iomem; - uint32_t size; - int32_t base_year; - /* RTC management */ - time_t time_offset; - time_t stop_time; - /* Alarm & watchdog */ - struct tm alarm; - QEMUTimer *alrm_timer; - QEMUTimer *wd_timer; - /* NVRAM storage */ - uint8_t *buffer; - /* Model parameters */ - uint32_t model; /* 2 =3D m48t02, 8 =3D m48t08, 59 =3D m48t59 */ - /* NVRAM storage */ - uint16_t addr; - uint8_t lock; -} M48t59State; - -typedef struct M48txxISAState { - ISADevice parent_obj; - M48t59State state; - uint32_t io_base; - MemoryRegion io; -} M48txxISAState; - -typedef struct M48txxISADeviceClass { - ISADeviceClass parent_class; - M48txxInfo info; -} M48txxISADeviceClass; - typedef struct M48txxSysBusState { SysBusDevice parent_obj; M48t59State state; @@ -122,21 +60,17 @@ typedef struct M48txxSysBusDeviceClass { M48txxInfo info; } M48txxSysBusDeviceClass; =20 -static M48txxInfo m48txx_info[] =3D { +static M48txxInfo m48txx_sysbus_info[] =3D { { - .sysbus_name =3D "sysbus-m48t02", + .bus_name =3D "sysbus-m48t02", .model =3D 2, .size =3D 0x800, },{ - .sysbus_name =3D "sysbus-m48t08", + .bus_name =3D "sysbus-m48t08", .model =3D 8, .size =3D 0x2000, },{ - .sysbus_name =3D "sysbus-m48t59", - .model =3D 59, - .size =3D 0x2000, - },{ - .isa_name =3D "isa-m48t59", + .bus_name =3D "sysbus-m48t59", .model =3D 59, .size =3D 0x2000, } @@ -248,7 +182,7 @@ static void set_up_watchdog(M48t59State *NVRAM, uint8_t= value) } =20 /* Direct access to NVRAM */ -static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val) +void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val) { struct tm tm; int tmp; @@ -413,7 +347,7 @@ static void m48t59_write(M48t59State *NVRAM, uint32_t a= ddr, uint32_t val) } } =20 -static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr) +uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr) { struct tm tm; uint32_t retval =3D 0xFF; @@ -517,11 +451,6 @@ static uint32_t m48t59_read(M48t59State *NVRAM, uint32= _t addr) return retval; } =20 -static void m48t59_toggle_lock(M48t59State *NVRAM, int lock) -{ - NVRAM->lock ^=3D 1 << lock; -} - /* IO access to NVRAM */ static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, unsigned size) @@ -639,7 +568,7 @@ static const VMStateDescription vmstate_m48t59 =3D { } }; =20 -static void m48t59_reset_common(M48t59State *NVRAM) +void m48t59_reset_common(M48t59State *NVRAM) { NVRAM->addr =3D 0; NVRAM->lock =3D 0; @@ -650,14 +579,6 @@ static void m48t59_reset_common(M48t59State *NVRAM) timer_del(NVRAM->wd_timer); } =20 -static void m48t59_reset_isa(DeviceState *d) -{ - M48txxISAState *isa =3D M48TXX_ISA(d); - M48t59State *NVRAM =3D &isa->state; - - m48t59_reset_common(NVRAM); -} - static void m48t59_reset_sysbus(DeviceState *d) { M48txxSysBusState *sys =3D M48TXX_SYS_BUS(d); @@ -666,7 +587,7 @@ static void m48t59_reset_sysbus(DeviceState *d) m48t59_reset_common(NVRAM); } =20 -static const MemoryRegionOps m48t59_io_ops =3D { +const MemoryRegionOps m48t59_io_ops =3D { .read =3D NVRAM_readb, .write =3D NVRAM_writeb, .impl =3D { @@ -685,14 +606,13 @@ Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base, SysBusDevice *s; int i; =20 - for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { - if (!m48txx_info[i].sysbus_name || - m48txx_info[i].size !=3D size || - m48txx_info[i].model !=3D model) { + for (i =3D 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) { + if (m48txx_sysbus_info[i].size !=3D size || + m48txx_sysbus_info[i].model !=3D model) { continue; } =20 - dev =3D qdev_create(NULL, m48txx_info[i].sysbus_name); + dev =3D qdev_create(NULL, m48txx_sysbus_info[i].bus_name); qdev_prop_set_int32(dev, "base-year", base_year); qdev_init_nofail(dev); s =3D SYS_BUS_DEVICE(dev); @@ -712,31 +632,7 @@ Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base, return NULL; } =20 -Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, - int base_year, int model) -{ - DeviceState *dev; - int i; - - for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { - if (!m48txx_info[i].isa_name || - m48txx_info[i].size !=3D size || - m48txx_info[i].model !=3D model) { - continue; - } - - dev =3D DEVICE(isa_create(bus, m48txx_info[i].isa_name)); - qdev_prop_set_uint32(dev, "iobase", io_base); - qdev_prop_set_int32(dev, "base-year", base_year); - qdev_init_nofail(dev); - return NVRAM(dev); - } - - assert(false); - return NULL; -} - -static void m48t59_realize_common(M48t59State *s, Error **errp) +void m48t59_realize_common(M48t59State *s, Error **errp) { s->buffer =3D g_malloc0(s->size); if (s->model =3D=3D 59) { @@ -748,23 +644,6 @@ static void m48t59_realize_common(M48t59State *s, Erro= r **errp) vmstate_register(NULL, -1, &vmstate_m48t59, s); } =20 -static void m48t59_isa_realize(DeviceState *dev, Error **errp) -{ - M48txxISADeviceClass *u =3D M48TXX_ISA_GET_CLASS(dev); - ISADevice *isadev =3D ISA_DEVICE(dev); - M48txxISAState *d =3D M48TXX_ISA(dev); - M48t59State *s =3D &d->state; - - s->model =3D u->info.model; - s->size =3D u->info.size; - isa_init_irq(isadev, &s->IRQ, 8); - m48t59_realize_common(s, errp); - memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59"= , 4); - if (d->io_base !=3D 0) { - isa_register_ioport(isadev, &d->io, d->io_base); - } -} - static int m48t59_init1(SysBusDevice *dev) { M48txxSysBusDeviceClass *u =3D M48TXX_SYS_BUS_GET_CLASS(dev); @@ -791,51 +670,6 @@ static int m48t59_init1(SysBusDevice *dev) return 0; } =20 -static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) -{ - M48txxISAState *d =3D M48TXX_ISA(obj); - return m48t59_read(&d->state, addr); -} - -static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) -{ - M48txxISAState *d =3D M48TXX_ISA(obj); - m48t59_write(&d->state, addr, val); -} - -static void m48txx_isa_toggle_lock(Nvram *obj, int lock) -{ - M48txxISAState *d =3D M48TXX_ISA(obj); - m48t59_toggle_lock(&d->state, lock); -} - -static Property m48t59_isa_properties[] =3D { - DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0), - DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), - DEFINE_PROP_END_OF_LIST(), -}; - -static void m48txx_isa_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - NvramClass *nc =3D NVRAM_CLASS(klass); - - dc->realize =3D m48t59_isa_realize; - dc->reset =3D m48t59_reset_isa; - dc->props =3D m48t59_isa_properties; - nc->read =3D m48txx_isa_read; - nc->write =3D m48txx_isa_write; - nc->toggle_lock =3D m48txx_isa_toggle_lock; -} - -static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) -{ - M48txxISADeviceClass *u =3D M48TXX_ISA_CLASS(klass); - M48txxInfo *info =3D data; - - u->info =3D *info; -} - static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr) { M48txxSysBusState *d =3D M48TXX_SYS_BUS(obj); @@ -899,18 +733,6 @@ static const TypeInfo m48txx_sysbus_type_info =3D { } }; =20 -static const TypeInfo m48txx_isa_type_info =3D { - .name =3D TYPE_M48TXX_ISA, - .parent =3D TYPE_ISA_DEVICE, - .instance_size =3D sizeof(M48txxISAState), - .abstract =3D true, - .class_init =3D m48txx_isa_class_init, - .interfaces =3D (InterfaceInfo[]) { - { TYPE_NVRAM }, - { } - } -}; - static void m48t59_register_types(void) { TypeInfo sysbus_type_info =3D { @@ -918,29 +740,15 @@ static void m48t59_register_types(void) .class_size =3D sizeof(M48txxSysBusDeviceClass), .class_init =3D m48txx_sysbus_concrete_class_init, }; - TypeInfo isa_type_info =3D { - .parent =3D TYPE_M48TXX_ISA, - .class_size =3D sizeof(M48txxISADeviceClass), - .class_init =3D m48txx_isa_concrete_class_init, - }; int i; =20 type_register_static(&nvram_info); type_register_static(&m48txx_sysbus_type_info); - type_register_static(&m48txx_isa_type_info); =20 - for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { - if (m48txx_info[i].sysbus_name) { - sysbus_type_info.name =3D m48txx_info[i].sysbus_name; - sysbus_type_info.class_data =3D &m48txx_info[i]; - type_register(&sysbus_type_info); - } - - if (m48txx_info[i].isa_name) { - isa_type_info.name =3D m48txx_info[i].isa_name; - isa_type_info.class_data =3D &m48txx_info[i]; - type_register(&isa_type_info); - } + for (i =3D 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) { + sysbus_type_info.name =3D m48txx_sysbus_info[i].bus_name; + sysbus_type_info.class_data =3D &m48txx_sysbus_info[i]; + type_register(&sysbus_type_info); } } =20 --=20 2.9.3