From nobody Tue Feb 10 03:38:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1485964061051945.9621431661557; Wed, 1 Feb 2017 07:47:41 -0800 (PST) Received: from localhost ([::1]:51685 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYx8D-0003a9-RX for importer@patchew.org; Wed, 01 Feb 2017 10:47:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYwda-000090-VY for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:16:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cYwdY-00020I-LX for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:15:58 -0500 Received: from mail-wm0-x232.google.com ([2a00:1450:400c:c09::232]:38518) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cYwdY-0001zr-FJ for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:15:56 -0500 Received: by mail-wm0-x232.google.com with SMTP id r141so42920732wmg.1 for ; Wed, 01 Feb 2017 07:15:56 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id w70sm34471655wrc.47.2017.02.01.07.15.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Feb 2017 07:15:53 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 522CA3E0FA4; Wed, 1 Feb 2017 15:05:55 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z5oUcCM/Tn3/Y7Lg6IUSTsXJ9cR5t8hB7WyuhbbUABk=; b=HbNSdX1H0DoSCfTkn3m9Z9C0i1KaVRstpZ9gL9f5wzFzJWHqi5sysw8FivYh27QktJ unSUwqfz+SnTtU8+CeAdng15tXN6nRRQNjI4DBpS1WeUiZoMoHBdL1IvP4hFj5qRd/kK 8ay3BuwHWozxY6c89MbLPmTiIjsb0Mu28tcxY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z5oUcCM/Tn3/Y7Lg6IUSTsXJ9cR5t8hB7WyuhbbUABk=; b=mvXn00Cq2gRD7jYxH0EtmBhGk7rLWMSejixWouaM+b2oPjWlcvdDkexwVaT/xN4qd+ xF/NZZ6Km9IspEOI73KpojoFjfKrPZMf53ye8U5ZJ0YNOekqyUpReFsCWtf+eTcTODb/ khK5uyleF50gsQqhhUeAEDcn7eHHSFtJ6PQkfWW+0lip3RCtW0t5d1wiSK7iv2C6dQtn snEUQASHAJxgXE6crdGLgmJD72qEXrNP5zJXCr68wh9m1JdniRYbCzfwGmrkGf93z41B 4BRCW2gxh/QigFUayEzmqEjhMLp263wUdrm89rdGeeYClXvc9UlNVPJDEzSmHj7nC/u3 cO+Q== X-Gm-Message-State: AIkVDXK+laiFi8tWcCQMbC1alnYr1gUVoaBLmQBYbozrm2dYsGFWsnYMYoD/CP0x0CV7IM70 X-Received: by 10.223.160.84 with SMTP id l20mr3093502wrl.106.1485962155357; Wed, 01 Feb 2017 07:15:55 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com Date: Wed, 1 Feb 2017 15:05:53 +0000 Message-Id: <20170201150553.9381-26-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170201150553.9381-1-alex.bennee@linaro.org> References: <20170201150553.9381-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [PATCH v9 25/25] tcg: enable MTTCG by default for ARM on x86 hosts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , jan.kiszka@siemens.com, mark.burton@greensocs.com, "open list:ARM" , serge.fdrv@gmail.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This enables the multi-threaded system emulation by default for ARMv7 and ARMv8 guests using the x86_64 TCG backend. This is because on the guest side: - The ARM translate.c/translate-64.c have been converted to - use MTTCG safe atomic primitives - emit the appropriate barrier ops - The ARM machine has been updated to - hold the BQL when modifying shared cross-vCPU state - defer cpu_reset to async safe work All the host backends support the barrier and atomic primitives but need to provide same-or-better support for normal load/store operations. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Acked-by: Peter Maydell --- v7 - drop configure check for backend - declare backend memory order for x86 - declare guest memory order for ARM - add configure snippet to set TARGET_SUPPORTS_MTTCG v8 - TCG_DEFAULT_MO -> TCG_GUEST_DEFAULT_MO - ~TCG_MO_LD_ST -> ~TCG_MO_ST_LD --- configure | 6 ++++++ cpus.c | 4 ++-- target/arm/cpu.h | 3 +++ tcg/i386/tcg-target.h | 11 +++++++++++ 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 86fd833feb..9f2a665f5b 100755 --- a/configure +++ b/configure @@ -5879,6 +5879,7 @@ mkdir -p $target_dir echo "# Automatically generated by configure - do not modify" > $config_ta= rget_mak =20 bflt=3D"no" +mttcg=3D"no" interp_prefix1=3D$(echo "$interp_prefix" | sed "s/%M/$target_name/g") gdb_xml_files=3D"" =20 @@ -5897,11 +5898,13 @@ case "$target_name" in arm|armeb) TARGET_ARCH=3Darm bflt=3D"yes" + mttcg=3D"yes" gdb_xml_files=3D"arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; aarch64) TARGET_BASE_ARCH=3Darm bflt=3D"yes" + mttcg=3D"yes" gdb_xml_files=3D"aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp= .xml arm-vfp3.xml arm-neon.xml" ;; cris) @@ -6066,6 +6069,9 @@ if test "$target_bigendian" =3D "yes" ; then fi if test "$target_softmmu" =3D "yes" ; then echo "CONFIG_SOFTMMU=3Dy" >> $config_target_mak + if test "$mttcg" =3D "yes" ; then + echo "TARGET_SUPPORTS_MTTCG=3Dy" >> $config_target_mak + fi fi if test "$target_user_only" =3D "yes" ; then echo "CONFIG_USER_ONLY=3Dy" >> $config_target_mak diff --git a/cpus.c b/cpus.c index e3d9f3fe21..e1b82bcd49 100644 --- a/cpus.c +++ b/cpus.c @@ -176,8 +176,8 @@ bool mttcg_enabled; =20 static bool check_tcg_memory_orders_compatible(void) { -#if defined(TCG_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) - return (TCG_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) =3D=3D 0; +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) + return (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) =3D=3D 0; #else return false; #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a3c4d07817..0ef31db3e0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -30,6 +30,9 @@ # define TARGET_LONG_BITS 32 #endif =20 +/* ARM processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #define CPUArchState struct CPUARMState =20 #include "qemu-common.h" diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 21d96ec35c..4275787db9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -165,4 +165,15 @@ static inline void flush_icache_range(uintptr_t start,= uintptr_t stop) { } =20 +/* This defines the natural memory order supported by this + * architecture before guarantees made by various barrier + * instructions. + * + * The x86 has a pretty strong memory ordering which only really + * allows for some stores to be re-ordered after loads. + */ +#include "tcg-mo.h" + +#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif --=20 2.11.0