From nobody Mon Nov 25 09:57:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716765427887636.7534476392194; Sun, 26 May 2024 16:17:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBN5P-0006Nr-DB; Sun, 26 May 2024 19:15:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBN5C-0005m4-BX; Sun, 26 May 2024 19:15:18 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBN55-0003oY-Qk; Sun, 26 May 2024 19:15:18 -0400 Received: from zero.eik.bme.hu (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id 0B7524E654F; Mon, 27 May 2024 01:13:18 +0200 (CEST) Received: from zero.eik.bme.hu ([127.0.0.1]) by zero.eik.bme.hu (zero.eik.bme.hu [127.0.0.1]) (amavisd-new, port 10028) with ESMTP id P9gle9qPYjkE; Mon, 27 May 2024 01:13:16 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 16EA34E6550; Mon, 27 May 2024 01:13:16 +0200 (CEST) X-Virus-Scanned: amavisd-new at eik.bme.hu Message-Id: <1fdc0583f2e14924123c9a99c250710129b61dfb.1716763435.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 39/43] target/ppc: Change parameter type of some inline functions MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza Date: Mon, 27 May 2024 01:13:16 +0200 (CEST) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716765429198100008 Content-Type: text/plain; charset="utf-8" These functions take PowerPCCPU but only need the env from it. Change their parameter to CPUPPCState *env. Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin --- target/ppc/mmu-hash32.c | 13 +++++++------ target/ppc/mmu-hash32.h | 12 ++++++------ target/ppc/mmu_common.c | 20 +++++++++----------- 3 files changed, 22 insertions(+), 23 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 6d0adf3357..f18faf0f46 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -244,10 +244,11 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, target_ulong sr, target_ulong eaddr, ppc_hash_pte32_t *pte) { + CPUPPCState *env =3D &cpu->env; hwaddr hpt_base, pteg_off, pte_addr, hash; uint32_t vsid, pgidx, ptem; =20 - hpt_base =3D ppc_hash32_hpt_base(cpu); + hpt_base =3D ppc_hash32_hpt_base(env); vsid =3D sr & SR32_VSID; pgidx =3D (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS; hash =3D vsid ^ pgidx; @@ -256,21 +257,21 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, /* Page address translation */ qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx " htab_mask " HWADDR_FMT_plx " hash " HWADDR_FMT_plx "\n", - hpt_base, ppc_hash32_hpt_mask(cpu), hash); + hpt_base, ppc_hash32_hpt_mask(env), hash); =20 /* Primary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, "0 htab=3D" HWADDR_FMT_plx "/" HWADDR_FMT_p= lx " vsid=3D%" PRIx32 " ptem=3D%" PRIx32 " hash=3D" HWADDR_= FMT_plx - "\n", hpt_base, ppc_hash32_hpt_mask(cpu), vsid, ptem, ha= sh); - pteg_off =3D get_pteg_offset32(cpu, hash); + "\n", hpt_base, ppc_hash32_hpt_mask(env), vsid, ptem, ha= sh); + pteg_off =3D get_pteg_offset32(env, hash); pte_addr =3D ppc_hash32_pteg_search(cpu, hpt_base + pteg_off, 0, ptem,= pte); if (pte_addr =3D=3D -1) { /* Secondary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, "1 htab=3D" HWADDR_FMT_plx "/" HWADDR_F= MT_plx " vsid=3D%" PRIx32 " api=3D%" PRIx32 " hash=3D" HWAD= DR_FMT_plx - "\n", hpt_base, ppc_hash32_hpt_mask(cpu), vsid, ptem, + "\n", hpt_base, ppc_hash32_hpt_mask(env), vsid, ptem, ~hash); - pteg_off =3D get_pteg_offset32(cpu, ~hash); + pteg_off =3D get_pteg_offset32(env, ~hash); pte_addr =3D ppc_hash32_pteg_search(cpu, hpt_base + pteg_off, 1, p= tem, pte); } diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index 4db55fb0a0..ec8d881def 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -59,19 +59,19 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMU= AccessType access_type, #define HPTE32_R_WIMG 0x00000078 #define HPTE32_R_PP 0x00000003 =20 -static inline hwaddr ppc_hash32_hpt_base(PowerPCCPU *cpu) +static inline hwaddr ppc_hash32_hpt_base(CPUPPCState *env) { - return cpu->env.spr[SPR_SDR1] & SDR_32_HTABORG; + return env->spr[SPR_SDR1] & SDR_32_HTABORG; } =20 -static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu) +static inline hwaddr ppc_hash32_hpt_mask(CPUPPCState *env) { - return ((cpu->env.spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF; + return ((env->spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF; } =20 -static inline hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash) +static inline hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash) { - return (hash * HASH_PTEG_SIZE_32) & ppc_hash32_hpt_mask(cpu); + return (hash * HASH_PTEG_SIZE_32) & ppc_hash32_hpt_mask(env); } =20 static inline bool ppc_hash32_key(bool pr, target_ulong sr) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 60f8736210..b45eb64f6e 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -166,8 +166,8 @@ static int ppc6xx_tlb_check(CPUPPCState *env, hwaddr *r= addr, int *prot, #if defined(DUMP_PAGE_TABLES) if (qemu_loglevel_mask(CPU_LOG_MMU)) { CPUState *cs =3D env_cpu(env); - hwaddr base =3D ppc_hash32_hpt_base(env_archcpu(env)); - hwaddr len =3D ppc_hash32_hpt_mask(env_archcpu(env)) + 0x80; + hwaddr base =3D ppc_hash32_hpt_base(env); + hwaddr len =3D ppc_hash32_hpt_mask(env) + 0x80; uint32_t a0, a1, a2, a3; =20 qemu_log("Page table: " HWADDR_FMT_plx " len " HWADDR_FMT_plx "\n", @@ -263,7 +263,6 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , hwaddr *raddr, hwaddr *hashp, bool *keyp, MMUAccessType access_type, int type) { - PowerPCCPU *cpu =3D env_archcpu(env); hwaddr hash; target_ulong vsid, sr, pgidx, ptem; bool key, ds, nx; @@ -305,7 +304,7 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , hwaddr *raddr, /* Page address translation */ qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx " htab_mask= " HWADDR_FMT_plx " hash " HWADDR_FMT_plx "\n", - ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), = hash); + ppc_hash32_hpt_base(env), ppc_hash32_hpt_mask(env), = hash); *hashp =3D hash; =20 /* Software TLB search */ @@ -499,13 +498,12 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int ty= pe) =20 static void mmu6xx_dump_mmu(CPUPPCState *env) { - PowerPCCPU *cpu =3D env_archcpu(env); ppc6xx_tlb_t *tlb; target_ulong sr; int type, way, entry, i; =20 - qemu_printf("HTAB base =3D 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cp= u)); - qemu_printf("HTAB mask =3D 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cp= u)); + qemu_printf("HTAB base =3D 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(en= v)); + qemu_printf("HTAB mask =3D 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(en= v)); =20 qemu_printf("\nSegment registers:\n"); for (i =3D 0; i < 32; i++) { @@ -743,10 +741,10 @@ static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eadd= r, env->spr[SPR_DCMP] |=3D 0x80000000; tlb_miss: env->error_code |=3D key << 19; - env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + - get_pteg_offset32(cpu, hash); - env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(cpu) + - get_pteg_offset32(cpu, ~hash); + env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(env) + + get_pteg_offset32(env, hash); + env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(env) + + get_pteg_offset32(env, ~hash); break; case -2: /* Access rights violation */ --=20 2.30.9