From nobody Fri Sep 26 20:12:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1758221621046346.6604254475101; Thu, 18 Sep 2025 11:53:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uzJiE-00022A-JL; Thu, 18 Sep 2025 14:50:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uzJiA-0001wS-IH; Thu, 18 Sep 2025 14:50:30 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uzJi7-0003KS-2c; Thu, 18 Sep 2025 14:50:30 -0400 Received: from localhost (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id 0ED5A56F355; Thu, 18 Sep 2025 20:50:18 +0200 (CEST) Received: from zero.eik.bme.hu ([127.0.0.1]) by localhost (zero.eik.bme.hu [127.0.0.1]) (amavis, port 10028) with ESMTP id kJmFMmkNCiHc; Thu, 18 Sep 2025 20:50:16 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 11C7356F353; Thu, 18 Sep 2025 20:50:16 +0200 (CEST) X-Virus-Scanned: amavis at eik.bme.hu Message-ID: <1ce9e69c55653d66dd2ead1a19ee779937847caa.1758219840.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v3 11/14] hw/pci-host/raven: Simpify discontiguous IO access MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Artyom Tarasenko , Nicholas Piggin Date: Thu, 18 Sep 2025 20:50:16 +0200 (CEST) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1758221622625116600 Content-Type: text/plain; charset="utf-8" PREP allows remapping of the 64k ISA IO addresses from the normal contiguous IO space into a discontiguous 8MB region and can switch between the two modes. We can implement this in a simpler way than is done currently using an io region that forwards access to the contiguous pci_io region and enabling/disabling the discontiguous region as needed. Signed-off-by: BALATON Zoltan --- hw/pci-host/raven.c | 88 ++++++++++++--------------------------------- 1 file changed, 22 insertions(+), 66 deletions(-) diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index bb0be40eb4..bf4f4b7f71 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -42,17 +42,14 @@ struct PREPPCIState { PCIHostState parent_obj; =20 qemu_irq irq; - AddressSpace pci_io_as; MemoryRegion pci_io; - MemoryRegion pci_io_non_contiguous; + MemoryRegion pci_discontiguous_io; MemoryRegion pci_memory; MemoryRegion pci_intack; MemoryRegion bm; MemoryRegion bm_ram_alias; MemoryRegion bm_pci_memory_alias; AddressSpace bm_as; - - int contiguous_map; }; =20 #define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */ @@ -103,63 +100,28 @@ static const MemoryRegionOps raven_intack_ops =3D { }, }; =20 -static inline hwaddr raven_io_address(PREPPCIState *s, - hwaddr addr) +/* Convert 8 MB non-contiguous address to 64k ISA IO address */ +static inline hwaddr raven_io_addr(hwaddr addr) { - if (s->contiguous_map =3D=3D 0) { - /* 64 KB contiguous space for IOs */ - addr &=3D 0xFFFF; - } else { - /* 8 MB non-contiguous space for IOs */ - addr =3D (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); - } - - /* FIXME: handle endianness switch */ - - return addr; + return ((addr & 0x007FFF000) >> 7) | (addr & 0x1F); } =20 -static uint64_t raven_io_read(void *opaque, hwaddr addr, - unsigned int size) +static uint64_t raven_io_read(void *opaque, hwaddr addr, unsigned int size) { - PREPPCIState *s =3D opaque; - uint8_t buf[4]; - - addr =3D raven_io_address(s, addr); - address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR, - MEMTXATTRS_UNSPECIFIED, buf, size); - - if (size =3D=3D 1) { - return buf[0]; - } else if (size =3D=3D 2) { - return lduw_le_p(buf); - } else if (size =3D=3D 4) { - return ldl_le_p(buf); - } else { - g_assert_not_reached(); - } + uint64_t val =3D 0xffffffffULL; + + memory_region_dispatch_read(opaque, raven_io_addr(addr), &val, + size_memop(size) | MO_LE, + MEMTXATTRS_UNSPECIFIED); + return val; } =20 -static void raven_io_write(void *opaque, hwaddr addr, - uint64_t val, unsigned int size) +static void raven_io_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) { - PREPPCIState *s =3D opaque; - uint8_t buf[4]; - - addr =3D raven_io_address(s, addr); - - if (size =3D=3D 1) { - buf[0] =3D val; - } else if (size =3D=3D 2) { - stw_le_p(buf, val); - } else if (size =3D=3D 4) { - stl_le_p(buf, val); - } else { - g_assert_not_reached(); - } - - address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR, - MEMTXATTRS_UNSPECIFIED, buf, size); + memory_region_dispatch_write(opaque, raven_io_addr(addr), val, + size_memop(size) | MO_LE, + MEMTXATTRS_UNSPECIFIED); } =20 static const MemoryRegionOps raven_io_ops =3D { @@ -208,7 +170,7 @@ static void raven_change_gpio(void *opaque, int n, int = level) { PREPPCIState *s =3D opaque; =20 - s->contiguous_map =3D level; + memory_region_set_enabled(&s->pci_discontiguous_io, !!level); } =20 static void raven_pcihost_realizefn(DeviceState *d, Error **errp) @@ -254,23 +216,17 @@ static void raven_pcihost_initfn(Object *obj) MemoryRegion *address_space_mem =3D get_system_memory(); =20 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); - memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, - "pci-io-non-contiguous", 0x00800000); + memory_region_init_io(&s->pci_discontiguous_io, obj, + &raven_io_ops, &s->pci_io, + "pci-discontiguous-io", 8 * MiB); memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000); - address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); - - /* - * Raven's raven_io_ops use the address-space API to access pci-conf-i= dx - * (which is also owned by the raven device). As such, mark the - * pci_io_non_contiguous as re-entrancy safe. - */ - s->pci_io_non_contiguous.disable_reentrancy_guard =3D true; =20 /* CPU address space */ memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR, &s->pci_io); memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADD= R, - &s->pci_io_non_contiguous, 1); + &s->pci_discontiguous_io, 1); + memory_region_set_enabled(&s->pci_discontiguous_io, false); memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_mem= ory); =20 /* Bus master address space */ --=20 2.41.3