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[37.6.0.26]) by smtp.gmail.com with ESMTPSA id a10-20020a05600c224a00b003fe23b10fdfsm1798183wmm.36.2023.10.13.00.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:59:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697183991; x=1697788791; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QiMWjDPU72IsVNa9l2Ta4NPkoq4odvg3UORhQ7BascA=; b=Aj1Y83vQAO6YgzvckAe3gb62NBgi2hbuKJkg582lIkbEnwZz9mgoB8Uls8zyia1UlG 701QP6/YH6hRakpmvg5JIFEPkDNvQbAcfg2bhC+ZP04YTfCh06uoWq2ac3eugRmrpTvU DPDodwaUhHLDXtJH3+uO48U5JOKNob0WDOOa7iSucXdmaqkjAwZ37JXy+yx983wYiWMS NJVZ2RbaZFKTFFXmNozYw6dzORCvBjIizG1pRBdWx7pdVDNYypQrgLs5IyiheAM1prSk 2IyN2Ay3lR7cD+y+Bq0rR9uamooD2Kta3V3ecu0PK2NhhRGYif9TG3fAX+o4H+QE2ww6 UKQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697183991; x=1697788791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QiMWjDPU72IsVNa9l2Ta4NPkoq4odvg3UORhQ7BascA=; b=geYLMG0LyETlEX106LDVpvlmtlfH+NxBcOfJ/vxtlL8Aw6cCkw1EUgiCxiw57/rl3i RLYyHkTqdrgAVQCyUY5g/6/L2FOV4A42rdVXoy1TYjvfGtAnCKhzpJw3BRGk8WYzJywO VrPgI8y2d6KSgeGy01C9byKWgqre3XPHyXqELK+cyqb4FYpYlb7wNDVzbl6VY5JmzWoL gt2DhXYG1z8SC8EXpJ83uYtKS67KfDL2RADmjbTQ4KJCkDUrMGYDF8LsA4GMAnWXE8ay 8Wu2MqAYkudwssWY3PvEFd6lmwVwoh1bhBOLQSCvQNTLvErPoY+Igxozf0msCAwEnP3U 6ZvA== X-Gm-Message-State: AOJu0Yxvovy+MBHrQzCm2+c+0+z4z5bGiaFclqQzgObZ37YSfbXwE+Gj wKzXvPiYc4M7b15JfnJIKKNJGVPDWLnAICVwthw= X-Google-Smtp-Source: AGHT+IHzJqRi8VwV+b9ORKHndCtRGT3t1PnNdmpY5FvA4dDZh8/fxZA38uIsR9/RsWmGWepdGDaoYA== X-Received: by 2002:ac2:5e69:0:b0:505:6fcd:dc32 with SMTP id a9-20020ac25e69000000b005056fcddc32mr19173839lfr.28.1697183991174; Fri, 13 Oct 2023 00:59:51 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org Cc: Emmanouil Pitsidianakis , Keith Busch , Klaus Jensen , qemu-block@nongnu.org (open list:nvme) Subject: [RFC PATCH v2 65/78] hw/nvme: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:57:32 +0300 Message-Id: <19e648431bdf3967c309a17b74fe775d92a72dc9.1697183699.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697184461757100003 Content-Type: text/plain; charset="utf-8" In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- hw/nvme/ctrl.c | 24 ++++++++++++------------ hw/nvme/dif.c | 4 ++-- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index f026245d1e..acb2012fb9 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1912,29 +1912,29 @@ static uint16_t nvme_check_zone_read(NvmeNamespace = *ns, uint64_t slba, static uint16_t nvme_zrm_finish(NvmeNamespace *ns, NvmeZone *zone) { switch (nvme_get_zone_state(zone)) { case NVME_ZONE_STATE_FULL: return NVME_SUCCESS; =20 case NVME_ZONE_STATE_IMPLICITLY_OPEN: case NVME_ZONE_STATE_EXPLICITLY_OPEN: nvme_aor_dec_open(ns); - /* fallthrough */ + fallthrough; case NVME_ZONE_STATE_CLOSED: nvme_aor_dec_active(ns); =20 if (zone->d.za & NVME_ZA_ZRWA_VALID) { zone->d.za &=3D ~NVME_ZA_ZRWA_VALID; if (ns->params.numzrwa) { ns->zns.numzrwa++; } } =20 - /* fallthrough */ + fallthrough; case NVME_ZONE_STATE_EMPTY: nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_FULL); return NVME_SUCCESS; =20 default: return NVME_ZONE_INVAL_TRANSITION; } } @@ -1942,15 +1942,15 @@ static uint16_t nvme_zrm_finish(NvmeNamespace *ns, = NvmeZone *zone) static uint16_t nvme_zrm_close(NvmeNamespace *ns, NvmeZone *zone) { switch (nvme_get_zone_state(zone)) { case NVME_ZONE_STATE_EXPLICITLY_OPEN: case NVME_ZONE_STATE_IMPLICITLY_OPEN: nvme_aor_dec_open(ns); nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_CLOSED); - /* fall through */ + fallthrough; case NVME_ZONE_STATE_CLOSED: return NVME_SUCCESS; =20 default: return NVME_ZONE_INVAL_TRANSITION; } } @@ -1958,29 +1958,29 @@ static uint16_t nvme_zrm_close(NvmeNamespace *ns, N= vmeZone *zone) static uint16_t nvme_zrm_reset(NvmeNamespace *ns, NvmeZone *zone) { switch (nvme_get_zone_state(zone)) { case NVME_ZONE_STATE_EXPLICITLY_OPEN: case NVME_ZONE_STATE_IMPLICITLY_OPEN: nvme_aor_dec_open(ns); - /* fallthrough */ + fallthrough; case NVME_ZONE_STATE_CLOSED: nvme_aor_dec_active(ns); =20 if (zone->d.za & NVME_ZA_ZRWA_VALID) { if (ns->params.numzrwa) { ns->zns.numzrwa++; } } =20 - /* fallthrough */ + fallthrough; case NVME_ZONE_STATE_FULL: zone->w_ptr =3D zone->d.zslba; zone->d.wp =3D zone->w_ptr; nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_EMPTY); - /* fallthrough */ + fallthrough; case NVME_ZONE_STATE_EMPTY: return NVME_SUCCESS; =20 default: return NVME_ZONE_INVAL_TRANSITION; } } @@ -2010,57 +2010,57 @@ enum { static uint16_t nvme_zrm_open_flags(NvmeCtrl *n, NvmeNamespace *ns, NvmeZone *zone, int flags) { int act =3D 0; uint16_t status; =20 switch (nvme_get_zone_state(zone)) { case NVME_ZONE_STATE_EMPTY: act =3D 1; =20 - /* fallthrough */ + fallthrough; =20 case NVME_ZONE_STATE_CLOSED: if (n->params.auto_transition_zones) { nvme_zrm_auto_transition_zone(ns); } status =3D nvme_zns_check_resources(ns, act, 1, (flags & NVME_ZRM_ZRWA) ? 1 : 0); if (status) { return status; } =20 if (act) { nvme_aor_inc_active(ns); } =20 nvme_aor_inc_open(ns); =20 if (flags & NVME_ZRM_AUTO) { nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_IMPLICITLY_OP= EN); return NVME_SUCCESS; } =20 - /* fallthrough */ + fallthrough; =20 case NVME_ZONE_STATE_IMPLICITLY_OPEN: if (flags & NVME_ZRM_AUTO) { return NVME_SUCCESS; } =20 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_EXPLICITLY_OPEN); =20 - /* fallthrough */ + fallthrough; =20 case NVME_ZONE_STATE_EXPLICITLY_OPEN: if (flags & NVME_ZRM_ZRWA) { ns->zns.numzrwa--; =20 zone->d.za |=3D NVME_ZA_ZRWA_VALID; } =20 return NVME_SUCCESS; =20 default: return NVME_ZONE_INVAL_TRANSITION; } } @@ -3508,135 +3508,135 @@ static void nvme_do_write_fdp(NvmeCtrl *n, NvmeRe= quest *req, uint64_t slba, static uint16_t nvme_do_write(NvmeCtrl *n, NvmeRequest *req, bool append, bool wrz) { NvmeRwCmd *rw =3D (NvmeRwCmd *)&req->cmd; NvmeNamespace *ns =3D req->ns; uint64_t slba =3D le64_to_cpu(rw->slba); uint32_t nlb =3D (uint32_t)le16_to_cpu(rw->nlb) + 1; uint16_t ctrl =3D le16_to_cpu(rw->control); uint8_t prinfo =3D NVME_RW_PRINFO(ctrl); uint64_t data_size =3D nvme_l2b(ns, nlb); uint64_t mapped_size =3D data_size; uint64_t data_offset; NvmeZone *zone; NvmeZonedResult *res =3D (NvmeZonedResult *)&req->cqe; BlockBackend *blk =3D ns->blkconf.blk; uint16_t status; =20 if (nvme_ns_ext(ns)) { mapped_size +=3D nvme_m2b(ns, nlb); =20 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { bool pract =3D prinfo & NVME_PRINFO_PRACT; =20 if (pract && ns->lbaf.ms =3D=3D nvme_pi_tuple_size(ns)) { mapped_size -=3D nvme_m2b(ns, nlb); } } } =20 trace_pci_nvme_write(nvme_cid(req), nvme_io_opc_str(rw->opcode), nvme_nsid(ns), nlb, mapped_size, slba); =20 if (!wrz) { status =3D nvme_check_mdts(n, mapped_size); if (status) { goto invalid; } } =20 status =3D nvme_check_bounds(ns, slba, nlb); if (status) { goto invalid; } =20 if (ns->params.zoned) { zone =3D nvme_get_zone_by_slba(ns, slba); assert(zone); =20 if (append) { bool piremap =3D !!(ctrl & NVME_RW_PIREMAP); =20 if (unlikely(zone->d.za & NVME_ZA_ZRWA_VALID)) { return NVME_INVALID_ZONE_OP | NVME_DNR; } =20 if (unlikely(slba !=3D zone->d.zslba)) { trace_pci_nvme_err_append_not_at_start(slba, zone->d.zslba= ); status =3D NVME_INVALID_FIELD; goto invalid; } =20 if (n->params.zasl && data_size > (uint64_t)n->page_size << n->params.zasl) { trace_pci_nvme_err_zasl(data_size); return NVME_INVALID_FIELD | NVME_DNR; } =20 slba =3D zone->w_ptr; rw->slba =3D cpu_to_le64(slba); res->slba =3D cpu_to_le64(slba); =20 switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { case NVME_ID_NS_DPS_TYPE_1: if (!piremap) { return NVME_INVALID_PROT_INFO | NVME_DNR; } =20 - /* fallthrough */ + fallthrough; =20 case NVME_ID_NS_DPS_TYPE_2: if (piremap) { uint32_t reftag =3D le32_to_cpu(rw->reftag); rw->reftag =3D cpu_to_le32(reftag + (slba - zone->d.zs= lba)); } =20 break; =20 case NVME_ID_NS_DPS_TYPE_3: if (piremap) { return NVME_INVALID_PROT_INFO | NVME_DNR; } =20 break; } } =20 status =3D nvme_check_zone_write(ns, zone, slba, nlb); if (status) { goto invalid; } =20 status =3D nvme_zrm_auto(n, ns, zone); if (status) { goto invalid; } =20 if (!(zone->d.za & NVME_ZA_ZRWA_VALID)) { zone->w_ptr +=3D nlb; } } else if (ns->endgrp && ns->endgrp->fdp.enabled) { nvme_do_write_fdp(n, req, slba, nlb); } =20 data_offset =3D nvme_l2b(ns, slba); =20 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { return nvme_dif_rw(n, req); } =20 if (!wrz) { status =3D nvme_map_data(n, nlb, req); if (status) { goto invalid; } =20 block_acct_start(blk_get_stats(blk), &req->acct, data_size, BLOCK_ACCT_WRITE); nvme_blk_write(blk, data_offset, BDRV_SECTOR_SIZE, nvme_rw_cb, req= ); } else { req->aiocb =3D blk_aio_pwrite_zeroes(blk, data_offset, data_size, BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req); } =20 return NVME_NO_COMPLETE; @@ -3734,13 +3734,13 @@ static uint16_t nvme_finish_zone(NvmeNamespace *ns,= NvmeZone *zone, static uint16_t nvme_offline_zone(NvmeNamespace *ns, NvmeZone *zone, NvmeZoneState state, NvmeRequest *req) { switch (state) { case NVME_ZONE_STATE_READ_ONLY: nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_OFFLINE); - /* fall through */ + fallthrough; case NVME_ZONE_STATE_OFFLINE: return NVME_SUCCESS; default: return NVME_ZONE_INVAL_TRANSITION; } } @@ -4902,39 +4902,39 @@ static uint16_t nvme_changed_nslist(NvmeCtrl *n, ui= nt8_t rae, uint32_t buf_len, static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8_t csi, uint32_t buf_le= n, uint64_t off, NvmeRequest *req) { NvmeEffectsLog log =3D {}; const uint32_t *src_iocs =3D NULL; uint32_t trans_len; =20 if (off >=3D sizeof(log)) { trace_pci_nvme_err_invalid_log_page_offset(off, sizeof(log)); return NVME_INVALID_FIELD | NVME_DNR; } =20 switch (NVME_CC_CSS(ldl_le_p(&n->bar.cc))) { case NVME_CC_CSS_NVM: src_iocs =3D nvme_cse_iocs_nvm; - /* fall through */ + fallthrough; case NVME_CC_CSS_ADMIN_ONLY: break; case NVME_CC_CSS_CSI: switch (csi) { case NVME_CSI_NVM: src_iocs =3D nvme_cse_iocs_nvm; break; case NVME_CSI_ZONED: src_iocs =3D nvme_cse_iocs_zoned; break; } } =20 memcpy(log.acs, nvme_cse_acs, sizeof(nvme_cse_acs)); =20 if (src_iocs) { memcpy(log.iocs, src_iocs, sizeof(log.iocs)); } =20 trans_len =3D MIN(sizeof(log) - off, buf_len); =20 return nvme_c2h(n, ((uint8_t *)&log) + off, trans_len, req); } diff --git a/hw/nvme/dif.c b/hw/nvme/dif.c index 01b19c3373..00dd96bdb3 100644 --- a/hw/nvme/dif.c +++ b/hw/nvme/dif.c @@ -153,58 +153,58 @@ void nvme_dif_pract_generate_dif(NvmeNamespace *ns, u= int8_t *buf, size_t len, static uint16_t nvme_dif_prchk_crc16(NvmeNamespace *ns, NvmeDifTuple *dif, uint8_t *buf, uint8_t *mbuf, size_t p= il, uint8_t prinfo, uint16_t apptag, uint16_t appmask, uint64_t reftag) { switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { case NVME_ID_NS_DPS_TYPE_3: if (be32_to_cpu(dif->g16.reftag) !=3D 0xffffffff) { break; } =20 - /* fallthrough */ + fallthrough; case NVME_ID_NS_DPS_TYPE_1: case NVME_ID_NS_DPS_TYPE_2: if (be16_to_cpu(dif->g16.apptag) !=3D 0xffff) { break; } =20 trace_pci_nvme_dif_prchk_disabled_crc16(be16_to_cpu(dif->g16.appta= g), be32_to_cpu(dif->g16.refta= g)); =20 return NVME_SUCCESS; } =20 if (prinfo & NVME_PRINFO_PRCHK_GUARD) { uint16_t crc =3D crc16_t10dif(0x0, buf, ns->lbasz); =20 if (pil) { crc =3D crc16_t10dif(crc, mbuf, pil); } =20 trace_pci_nvme_dif_prchk_guard_crc16(be16_to_cpu(dif->g16.guard), = crc); =20 if (be16_to_cpu(dif->g16.guard) !=3D crc) { return NVME_E2E_GUARD_ERROR; } } =20 if (prinfo & NVME_PRINFO_PRCHK_APP) { trace_pci_nvme_dif_prchk_apptag(be16_to_cpu(dif->g16.apptag), appt= ag, appmask); =20 if ((be16_to_cpu(dif->g16.apptag) & appmask) !=3D (apptag & appmas= k)) { return NVME_E2E_APP_ERROR; } } =20 if (prinfo & NVME_PRINFO_PRCHK_REF) { trace_pci_nvme_dif_prchk_reftag_crc16(be32_to_cpu(dif->g16.reftag), reftag); =20 if (be32_to_cpu(dif->g16.reftag) !=3D reftag) { return NVME_E2E_REF_ERROR; } } =20 return NVME_SUCCESS; } @@ -212,66 +212,66 @@ static uint16_t nvme_dif_prchk_crc16(NvmeNamespace *n= s, NvmeDifTuple *dif, static uint16_t nvme_dif_prchk_crc64(NvmeNamespace *ns, NvmeDifTuple *dif, uint8_t *buf, uint8_t *mbuf, size_t p= il, uint8_t prinfo, uint16_t apptag, uint16_t appmask, uint64_t reftag) { uint64_t r =3D 0; =20 r |=3D (uint64_t)dif->g64.sr[0] << 40; r |=3D (uint64_t)dif->g64.sr[1] << 32; r |=3D (uint64_t)dif->g64.sr[2] << 24; r |=3D (uint64_t)dif->g64.sr[3] << 16; r |=3D (uint64_t)dif->g64.sr[4] << 8; r |=3D (uint64_t)dif->g64.sr[5]; =20 switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { case NVME_ID_NS_DPS_TYPE_3: if (r !=3D 0xffffffffffff) { break; } =20 - /* fallthrough */ + fallthrough; case NVME_ID_NS_DPS_TYPE_1: case NVME_ID_NS_DPS_TYPE_2: if (be16_to_cpu(dif->g64.apptag) !=3D 0xffff) { break; } =20 trace_pci_nvme_dif_prchk_disabled_crc64(be16_to_cpu(dif->g16.appta= g), r); =20 return NVME_SUCCESS; } =20 if (prinfo & NVME_PRINFO_PRCHK_GUARD) { uint64_t crc =3D crc64_nvme(~0ULL, buf, ns->lbasz); =20 if (pil) { crc =3D crc64_nvme(~crc, mbuf, pil); } =20 trace_pci_nvme_dif_prchk_guard_crc64(be64_to_cpu(dif->g64.guard), = crc); =20 if (be64_to_cpu(dif->g64.guard) !=3D crc) { return NVME_E2E_GUARD_ERROR; } } =20 if (prinfo & NVME_PRINFO_PRCHK_APP) { trace_pci_nvme_dif_prchk_apptag(be16_to_cpu(dif->g64.apptag), appt= ag, appmask); =20 if ((be16_to_cpu(dif->g64.apptag) & appmask) !=3D (apptag & appmas= k)) { return NVME_E2E_APP_ERROR; } } =20 if (prinfo & NVME_PRINFO_PRCHK_REF) { trace_pci_nvme_dif_prchk_reftag_crc64(r, reftag); =20 if (r !=3D reftag) { return NVME_E2E_REF_ERROR; } } =20 return NVME_SUCCESS; } --=20 2.39.2