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Sat, 07 Mar 2026 23:20:54 -0800 (PST) From: Chao Liu To: Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier Cc: tangtao1634@phytium.com.cn, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 24/28] tests/qtest: add initial RISC-V Debug Module tests Date: Sun, 8 Mar 2026 15:17:27 +0800 Message-ID: <18d94d4d321cd011e7d61fffdff3218ad5a23cc7.1772936778.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1341; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772954587578158500 Content-Type: text/plain; charset="utf-8" Add the first qtest coverage for the virt Debug Module model. The new riscv-dm-test binary checks dmactive gating, dmstatus, hartinfo, and abstractcs reset values, then drives a basic halt/resume cycle by writing the ROM mailbox words used by the CPU park loop. Register the test for both riscv32 and riscv64 when CONFIG_RISCV_DM is enabled. Signed-off-by: Chao Liu --- MAINTAINERS | 1 + tests/qtest/meson.build | 7 +- tests/qtest/riscv-dm-test.c | 208 ++++++++++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/riscv-dm-test.c diff --git a/MAINTAINERS b/MAINTAINERS index d8f326c8b2..faaa7114ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -361,6 +361,7 @@ F: tests/functional/riscv32 F: tests/functional/riscv64 F: tests/tcg/riscv64/ F: tests/qtest/iommu-riscv-test.c +F: tests/qtest/riscv-dm-test.c =20 RISC-V XThead* extensions M: Christoph Muellner diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index ba9f59d2f8..3bb9e3cc16 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -282,13 +282,16 @@ qtests_s390x =3D \ 'migration-test'] =20 qtests_riscv32 =3D \ - (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watc= hdog-test'] : []) + (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watc= hdog-test'] : []) + \ + (config_all_devices.has_key('CONFIG_RISCV_DM') ? ['riscv-dm-test'] : []) =20 qtests_riscv64 =3D ['riscv-csr-test'] + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? - ['iommu-riscv-test'] : []) + ['iommu-riscv-test'] : []) + \ + (config_all_devices.has_key('CONFIG_RISCV_DM') ? + ['riscv-dm-test'] : []) =20 qos_test_ss =3D ss.source_set() qos_test_ss.add( diff --git a/tests/qtest/riscv-dm-test.c b/tests/qtest/riscv-dm-test.c new file mode 100644 index 0000000000..c9e3c22a20 --- /dev/null +++ b/tests/qtest/riscv-dm-test.c @@ -0,0 +1,208 @@ +/* + * QTest for RISC-V Debug Module v1.0 + * + * Copyright (c) 2025 Chao Liu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define DM_BASE 0x0 + +#define ROM_HARTID 0x104 +#define ROM_RESUME 0x10c + +#define A_DATA0 0x10 +#define A_DMCONTROL 0x40 +#define A_DMSTATUS 0x44 +#define A_HARTINFO 0x48 +#define A_ABSTRACTCS 0x58 + +#define DMCONTROL_DMACTIVE (1u << 0) +#define DMCONTROL_HALTREQ (1u << 31) +#define DMCONTROL_RESUMEREQ (1u << 30) + +#define DMSTATUS_VERSION_MASK 0xf +#define DMSTATUS_AUTHENTICATED (1u << 7) +#define DMSTATUS_ANYHALTED (1u << 8) +#define DMSTATUS_ALLHALTED (1u << 9) +#define DMSTATUS_ANYRUNNING (1u << 10) +#define DMSTATUS_ALLRUNNING (1u << 11) +#define DMSTATUS_ANYRESUMEACK (1u << 16) +#define DMSTATUS_ALLRESUMEACK (1u << 17) +#define DMSTATUS_ANYHAVERESET (1u << 18) +#define DMSTATUS_IMPEBREAK (1u << 22) + +#define HARTINFO_DATAADDR_MASK 0xfffu +#define HARTINFO_DATASIZE_SHIFT 12 +#define HARTINFO_DATASIZE_MASK (0xfu << HARTINFO_DATASIZE_SHIFT) +#define HARTINFO_DATAACCESS (1u << 16) +#define HARTINFO_NSCRATCH_SHIFT 20 +#define HARTINFO_NSCRATCH_MASK (0xfu << HARTINFO_NSCRATCH_SHIFT) + +#define ABSTRACTCS_DATACOUNT_MASK 0xf +#define ABSTRACTCS_BUSY (1u << 12) +#define ABSTRACTCS_PROGBUFSIZE_SHIFT 24 +#define ABSTRACTCS_PROGBUFSIZE_MASK (0x1fu << ABSTRACTCS_PROGBUFSIZE_S= HIFT) + +static uint32_t dm_read(QTestState *qts, uint32_t reg) +{ + return qtest_readl(qts, DM_BASE + reg); +} + +static void dm_write(QTestState *qts, uint32_t reg, uint32_t val) +{ + qtest_writel(qts, DM_BASE + reg, val); +} + +static void dm_set_active(QTestState *qts) +{ + dm_write(qts, A_DMCONTROL, DMCONTROL_DMACTIVE); +} + +static void rom_write32(QTestState *qts, uint32_t offset, uint32_t val) +{ + qtest_writel(qts, DM_BASE + offset, val); +} + +static void sim_cpu_halt_ack(QTestState *qts, uint32_t hartid) +{ + rom_write32(qts, ROM_HARTID, hartid); +} + +static void sim_cpu_resume_ack(QTestState *qts, uint32_t hartid) +{ + rom_write32(qts, ROM_RESUME, hartid); +} + +static void test_dmactive_gate(void) +{ + QTestState *qts =3D qtest_init("-machine virt"); + + g_assert_cmpuint(dm_read(qts, A_DMCONTROL), =3D=3D, 0); + g_assert_cmpuint(dm_read(qts, A_DMSTATUS), =3D=3D, 0); + g_assert_cmpuint(dm_read(qts, A_HARTINFO), =3D=3D, 0); + g_assert_cmpuint(dm_read(qts, A_ABSTRACTCS), =3D=3D, 0); + g_assert_cmpuint(dm_read(qts, A_DATA0), =3D=3D, 0); + + dm_write(qts, A_DATA0, 0xdeadbeef); + g_assert_cmpuint(dm_read(qts, A_DATA0), =3D=3D, 0); + + dm_set_active(qts); + g_assert_cmpuint(dm_read(qts, A_DMCONTROL) & DMCONTROL_DMACTIVE, =3D= =3D, + DMCONTROL_DMACTIVE); + g_assert_cmpuint(dm_read(qts, A_DMSTATUS), !=3D, 0); + + qtest_quit(qts); +} + +static void test_dmstatus(void) +{ + QTestState *qts =3D qtest_init("-machine virt"); + uint32_t status; + + dm_set_active(qts); + status =3D dm_read(qts, A_DMSTATUS); + + g_assert_cmpuint(status & DMSTATUS_VERSION_MASK, =3D=3D, 3); + g_assert_cmpuint(status & DMSTATUS_AUTHENTICATED, =3D=3D, + DMSTATUS_AUTHENTICATED); + g_assert_cmpuint(status & DMSTATUS_ANYRUNNING, =3D=3D, + DMSTATUS_ANYRUNNING); + g_assert_cmpuint(status & DMSTATUS_ALLRUNNING, =3D=3D, + DMSTATUS_ALLRUNNING); + g_assert_cmpuint(status & DMSTATUS_ANYHALTED, =3D=3D, 0); + g_assert_cmpuint(status & DMSTATUS_ANYHAVERESET, =3D=3D, + DMSTATUS_ANYHAVERESET); + g_assert_cmpuint(status & DMSTATUS_IMPEBREAK, =3D=3D, DMSTATUS_IMPEBRE= AK); + + qtest_quit(qts); +} + +static void test_hartinfo(void) +{ + QTestState *qts =3D qtest_init("-machine virt"); + uint32_t info; + + dm_set_active(qts); + info =3D dm_read(qts, A_HARTINFO); + + g_assert_cmpuint(info & HARTINFO_DATAADDR_MASK, =3D=3D, 0x3c0); + g_assert_cmpuint(info & HARTINFO_DATAACCESS, =3D=3D, HARTINFO_DATAACCE= SS); + g_assert_cmpuint((info & HARTINFO_DATASIZE_MASK) >> + HARTINFO_DATASIZE_SHIFT, =3D=3D, 2); + g_assert_cmpuint((info & HARTINFO_NSCRATCH_MASK) >> + HARTINFO_NSCRATCH_SHIFT, =3D=3D, 1); + + qtest_quit(qts); +} + +static void test_abstractcs_config(void) +{ + QTestState *qts =3D qtest_init("-machine virt"); + uint32_t acs; + + dm_set_active(qts); + acs =3D dm_read(qts, A_ABSTRACTCS); + + g_assert_cmpuint(acs & ABSTRACTCS_DATACOUNT_MASK, =3D=3D, 2); + g_assert_cmpuint((acs & ABSTRACTCS_PROGBUFSIZE_MASK) >> + ABSTRACTCS_PROGBUFSIZE_SHIFT, =3D=3D, 8); + g_assert_cmpuint(acs & ABSTRACTCS_BUSY, =3D=3D, 0); + + qtest_quit(qts); +} + +static void test_halt_resume(void) +{ + QTestState *qts =3D qtest_init("-machine virt"); + uint32_t status; + + dm_set_active(qts); + status =3D dm_read(qts, A_DMSTATUS); + g_assert_cmpuint(status & DMSTATUS_ANYRUNNING, =3D=3D, + DMSTATUS_ANYRUNNING); + g_assert_cmpuint(status & DMSTATUS_ANYHALTED, =3D=3D, 0); + + dm_write(qts, A_DMCONTROL, DMCONTROL_DMACTIVE | DMCONTROL_HALTREQ); + sim_cpu_halt_ack(qts, 0); + + status =3D dm_read(qts, A_DMSTATUS); + g_assert_cmpuint(status & DMSTATUS_ANYHALTED, =3D=3D, + DMSTATUS_ANYHALTED); + g_assert_cmpuint(status & DMSTATUS_ALLHALTED, =3D=3D, + DMSTATUS_ALLHALTED); + g_assert_cmpuint(status & DMSTATUS_ANYRUNNING, =3D=3D, 0); + g_assert_cmpuint(status & DMSTATUS_ALLRUNNING, =3D=3D, 0); + + dm_write(qts, A_DMCONTROL, DMCONTROL_DMACTIVE | DMCONTROL_RESUMEREQ); + sim_cpu_resume_ack(qts, 0); + + status =3D dm_read(qts, A_DMSTATUS); + g_assert_cmpuint(status & DMSTATUS_ANYRESUMEACK, =3D=3D, + DMSTATUS_ANYRESUMEACK); + g_assert_cmpuint(status & DMSTATUS_ALLRESUMEACK, =3D=3D, + DMSTATUS_ALLRESUMEACK); + g_assert_cmpuint(status & DMSTATUS_ANYRUNNING, =3D=3D, + DMSTATUS_ANYRUNNING); + g_assert_cmpuint(status & DMSTATUS_ALLRUNNING, =3D=3D, + DMSTATUS_ALLRUNNING); + g_assert_cmpuint(status & DMSTATUS_ANYHALTED, =3D=3D, 0); + + qtest_quit(qts); +} + +int main(int argc, char *argv[]) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/riscv-dm/dmactive-gate", test_dmactive_gate); + qtest_add_func("/riscv-dm/dmstatus", test_dmstatus); + qtest_add_func("/riscv-dm/hartinfo", test_hartinfo); + qtest_add_func("/riscv-dm/abstractcs-config", test_abstractcs_config); + qtest_add_func("/riscv-dm/halt-resume", test_halt_resume); + + return g_test_run(); +} --=20 2.53.0