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charset="utf-8" Add PAT, cr8 and EFER for 32-bit qemu to hax ioctl interface, part of HAX P= R 204 Signed-off-by: Alexey Romko --- =C2=A0target/i386/hax-all.c=C2=A0 =C2=A0 =C2=A0 =C2=A0| 32 ++++++++++++++++= ++++++++++++---- =C2=A0target/i386/hax-i386.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 +- =C2=A0target/i386/hax-interface.h |=C2=A0 2 ++ =C2=A03 files changed, 31 insertions(+), 5 deletions(-) diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index a8b6e5aeb8..0bdd309665 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -45,7 +45,7 @@ =C2=A0 =C2=A0 =C2=A0} while (0) =C2=A0 =C2=A0/* Current version */ -const uint32_t hax_cur_version =3D 0x4; /* API v4: unmapping and MMIO move= s */ +const uint32_t hax_cur_version =3D 0x5; /* API v5: supports CR8/EFER/PAT */ =C2=A0/* Minimum HAX kernel version */ =C2=A0const uint32_t hax_min_version =3D 0x4; /* API v4: supports unmapping= */ =C2=A0 @@ -137,6 +137,7 @@ static int hax_version_support(struct hax_state *hax) =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0; =C2=A0 =C2=A0 =C2=A0} =C2=A0 +=C2=A0 =C2=A0 hax_global.cur_api_version =3D version.cur_version; =C2=A0 =C2=A0 =C2=A0return 1; =C2=A0} =C2=A0 @@ -845,12 +846,24 @@ static int hax_sync_vcpu_register(CPUArchState *env, = int set) =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs._cr2 =3D env->cr[2]; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs._cr3 =3D env->cr[3]; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs._cr4 =3D env->cr[4]; + +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if( hax_global.cur_api_version >=3D 0x5 ) { +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 X86CPU *x86_cpu =3D X86_CPU(cs); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 regs._cr8 =3D cpu_get_apic_tpr(x86_cpu-= >apic_state); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hax_set_segments(env, ®s); =C2=A0 =C2=A0 =C2=A0} else { =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cr[0] =3D regs._cr0; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cr[2] =3D regs._cr2; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cr[3] =3D regs._cr3; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cr[4] =3D regs._cr4; + +=C2=A0 =C2=A0 =C2=A0 =C2=A0 //if( hax_global.cur_api_version >=3D 0x5 ) { +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 //no need to update TPR from regs._cr8,= since all changes are notified. +=C2=A0 =C2=A0 =C2=A0 =C2=A0 //} + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hax_get_segments(env, ®s); =C2=A0 =C2=A0 =C2=A0} =C2=A0 @@ -881,14 +894,18 @@ static int hax_get_msrs(CPUArchState *env) =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_IA32_SYSENTER_ESP; =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_IA32_SYSENTER_EIP; =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_IA32_TSC; -#ifdef TARGET_X86_64 =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_EFER; +#ifdef TARGET_X86_64 =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_STAR; =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_LSTAR; =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_CSTAR; =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_FMASK; =C2=A0 =C2=A0 =C2=A0msrs[n++].entry =3D MSR_KERNELGSBASE; =C2=A0#endif +=C2=A0 =C2=A0 if( hax_global.cur_api_version >=3D 0x5 ) { +=C2=A0 =C2=A0 =C2=A0 msrs[n++].entry =3D MSR_PAT; +=C2=A0 =C2=A0 } + =C2=A0 =C2=A0 =C2=A0md.nr_msr =3D n; =C2=A0 =C2=A0 =C2=A0ret =3D hax_sync_msr(env, &md, 0); =C2=A0 =C2=A0 =C2=A0if (ret < 0) { @@ -909,10 +926,10 @@ static int hax_get_msrs(CPUArchState *env) =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0case MSR_IA32_TSC: =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->tsc =3D msrs[i].value; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break; -#ifdef TARGET_X86_64 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0case MSR_EFER: =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->efer =3D msrs[i].value; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break; +#ifdef TARGET_X86_64 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0case MSR_STAR: =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->star =3D msrs[i].value; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break; @@ -929,6 +946,9 @@ static int hax_get_msrs(CPUArchState *env) =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->kernelgsbase =3D msrs[= i].value; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break; =C2=A0#endif +=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MSR_PAT: +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->pat =3D msrs[i].value; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} =C2=A0 =C2=A0 =C2=A0} =C2=A0 @@ -947,14 +967,18 @@ static int hax_set_msrs(CPUArchState *env) =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, en= v->sysenter_esp); =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, en= v->sysenter_eip); =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); -#ifdef TARGET_X86_64 =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_EFER, env->efer); +#ifdef TARGET_X86_64 =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_STAR, env->star); =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); =C2=A0 =C2=A0 =C2=A0hax_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->ke= rnelgsbase); =C2=A0#endif +=C2=A0 =C2=A0 if( hax_global.cur_api_version >=3D 0x5 ) { +=C2=A0 =C2=A0 =C2=A0 hax_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); +=C2=A0 =C2=A0 } + =C2=A0 =C2=A0 =C2=A0md.nr_msr =3D n; =C2=A0 =C2=A0 =C2=A0md.done =3D 0; =C2=A0 diff --git a/target/i386/hax-i386.h b/target/i386/hax-i386.h index 54e9d8b057..9515803184 100644 --- a/target/i386/hax-i386.h +++ b/target/i386/hax-i386.h @@ -34,7 +34,7 @@ struct hax_vcpu_state { =C2=A0 =C2=A0struct hax_state { =C2=A0 =C2=A0 =C2=A0hax_fd fd; /* the global hax device interface */ -=C2=A0 =C2=A0 uint32_t version; +=C2=A0 =C2=A0 uint32_t cur_api_version; =C2=A0 =C2=A0 =C2=A0struct hax_vm *vm; =C2=A0 =C2=A0 =C2=A0uint64_t mem_quota; =C2=A0 =C2=A0 =C2=A0bool supports_64bit_ramblock; diff --git a/target/i386/hax-interface.h b/target/i386/hax-interface.h index 537ae084e9..c87aedbc2e 100644 --- a/target/i386/hax-interface.h +++ b/target/i386/hax-interface.h @@ -218,6 +218,8 @@ struct vcpu_state_t { =C2=A0 =C2=A0 =C2=A0uint32_t _activity_state; =C2=A0 =C2=A0 =C2=A0uint32_t pad; =C2=A0 =C2=A0 =C2=A0interruptibility_state_t _interruptibility_state; + +=C2=A0 =C2=A0 uint64_t _cr8; =C2=A0}; =C2=A0 =C2=A0/* HAX exit status */ --=C2=A0 2.15.0.windows.1