From nobody Sat Apr 11 20:14:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775677438599933.8033769662837; Wed, 8 Apr 2026 12:43:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wAYWr-0000iF-BF; Wed, 08 Apr 2026 15:25:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wAY7R-0007eq-KB; Wed, 08 Apr 2026 14:59:20 -0400 Received: from mail-a.sr.ht ([46.23.81.152]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wAQmk-00035v-8n; Wed, 08 Apr 2026 07:09:29 -0400 Received: from git.sr.ht (unknown [46.23.81.155]) by mail-a.sr.ht (Postfix) with ESMTPSA id BEF10207F8; Wed, 08 Apr 2026 11:07:20 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=I2vJF8Ao5uoGzmkiFFS4anH8vSW24HuJ9ZbFaJQD0us=; c=simple/simple; d=git.sr.ht; h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113; t=1775646440; v=1; b=mjm+bSDIhe9pAR8EbLd96UGMmRKB1LNHJkwh8mDXpvAkBZkwz1LGbuh3mYHHiR2w69T+48fv io05KU1HzZnFbtZ7MlFwraxVBxX1z6/nvqFXkaYJE/iAvTEqFMPx+Jl0Pp2GuQ+DEN9MBROs0Fa 2RBIkhEzl04ZeP2vXUDaUwQ+EOuK9941dPcL09AJs2dqMrrQq4z5J9AwxAU2ic8rmPzoI84A0hm CNp/KHPerSXvMG5tgnmHe5qsPQXLp7OimHcDi+p7cgpSbOCPknO8QSjUuW3baConSQlhM2rlC72 aGU2HpXil27ZqX9LTwos/2x/RVIuKY82w1bnzE+zvyxWg== From: ~lexbaileylowrisc Date: Tue, 07 Apr 2026 14:38:47 +0100 Subject: [PATCH qemu v2 4/7] ot_uart: replace individual IRQ fields with array, add missing IRQs Message-ID: <177564643888.23414.7922925369077631439-4@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <177564643888.23414.7922925369077631439-0@git.sr.ht> To: qemu-riscv@nongnu.org, Alistair Francis Cc: Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9?= Lureau , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-devel@nongnu.org, Amit Kumar-Hermosillo , nabihestefan@google.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht; helo=mail-a.sr.ht X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_12_24=1.049, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~lexbaileylowrisc Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1775677442248158500 From: Lex Bailey There are 9 interrupts in the OpenTitan UART device. These are documented here: https://opentitan.org/book/hw/ip/uart/doc/theory_of_operation.html#interrup= ts This commit removes the individually named interrupts (of which there was o= nly four) and replaces them with an array of 9 interrupts. Signed-off-by: Lex Bailey Reviewed-by: Alistair Francis --- hw/char/ot_uart.c | 44 +++++++++++++-------------------------- include/hw/char/ot_uart.h | 5 +---- 2 files changed, 15 insertions(+), 34 deletions(-) diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c index 3bf3295b1b..923aab12af 100644 --- a/hw/char/ot_uart.c +++ b/hw/char/ot_uart.c @@ -107,6 +107,7 @@ REG32(TIMEOUT_CTRL, 0x30) #define OT_UART_NCO_BITS 16 #define OT_UART_TX_FIFO_SIZE 128 #define OT_UART_RX_FIFO_SIZE 128 +#define OT_UART_IRQ_NUM 9 =20 #define R32_OFF(_r_) ((_r_) / sizeof(uint32_t)) =20 @@ -116,31 +117,11 @@ REG32(TIMEOUT_CTRL, 0x30) =20 static void ot_uart_update_irqs(OtUARTState *s) { - if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE] - & INTR_TX_WATERMARK_MASK) { - qemu_set_irq(s->tx_watermark, 1); - } else { - qemu_set_irq(s->tx_watermark, 0); - } - - if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE] - & INTR_RX_WATERMARK_MASK) { - qemu_set_irq(s->rx_watermark, 1); - } else { - qemu_set_irq(s->rx_watermark, 0); - } + uint32_t state_masked =3D s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABL= E]; =20 - if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE] & INTR_TX_EMPTY_MAS= K) { - qemu_set_irq(s->tx_empty, 1); - } else { - qemu_set_irq(s->tx_empty, 0); - } - - if (s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE] - & INTR_RX_OVERFLOW_MASK) { - qemu_set_irq(s->rx_overflow, 1); - } else { - qemu_set_irq(s->rx_overflow, 0); + for (int index =3D 0; index < OT_UART_IRQ_NUM; index++) { + bool level =3D (state_masked & (1U << index)) !=3D 0; + qemu_set_irq(s->irqs[index], level); } } =20 @@ -291,6 +272,9 @@ static void ot_uart_reset_enter(Object *obj, ResetType = type) s->regs[R_STATUS] =3D 0x0000003c; =20 s->tx_watermark_level =3D 0; + for (unsigned index =3D 0; index < ARRAY_SIZE(s->irqs); index++) { + qemu_set_irq(s->irqs[index], 0); + } ot_uart_reset_tx_fifo(s); ot_uart_reset_rx_fifo(s); =20 @@ -562,21 +546,21 @@ static void ot_uart_init(Object *obj) ot_uart_clk_update, s, ClockUpdate); clock_set_hz(s->f_clk, OT_UART_CLOCK); =20 - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark); - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark); - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty); - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow); + for (unsigned index =3D 0; index < OT_UART_IRQ_NUM; index++) { + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irqs[index]); + } =20 memory_region_init_io(&s->mmio, obj, &ot_uart_ops, s, TYPE_OT_UART, 0x400); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); =20 /* - * This array has a fixed size in the header. This assertion is used to - * check that it is consistent with the definition in this file. This = is + * These arrays have fixed sizes in the header. These assertions are u= sed to + * check that they are consistent with the definitions in this file. T= his is * ostensibly a runtime check, but may be optimised away by the compil= er. */ assert(REGS_SIZE =3D=3D sizeof(s->regs)); + assert(OT_UART_IRQ_NUM * sizeof(qemu_irq) =3D=3D sizeof(s->irqs)); } =20 static void ot_uart_realize(DeviceState *dev, Error **errp) diff --git a/include/hw/char/ot_uart.h b/include/hw/char/ot_uart.h index f489612700..a2c5ff8b33 100644 --- a/include/hw/char/ot_uart.h +++ b/include/hw/char/ot_uart.h @@ -42,6 +42,7 @@ struct OtUARTState { =20 /* */ MemoryRegion mmio; + qemu_irq irqs[9]; =20 uint32_t tx_level; =20 @@ -59,10 +60,6 @@ struct OtUARTState { Clock *f_clk; =20 CharFrontend chr; - qemu_irq tx_watermark; - qemu_irq rx_watermark; - qemu_irq tx_empty; - qemu_irq rx_overflow; }; =20 struct OtUARTClass { --=20 2.49.1