From nobody Wed Nov 5 05:17:43 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532702412403220.5231431817415; Fri, 27 Jul 2018 07:40:12 -0700 (PDT) Received: from localhost ([::1]:41598 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fj3uc-0004RP-HL for importer@patchew.org; Fri, 27 Jul 2018 10:40:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34370) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fj3sH-0003FD-R3 for qemu-devel@nongnu.org; Fri, 27 Jul 2018 10:37:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fj3sG-0008Ii-Mm for qemu-devel@nongnu.org; Fri, 27 Jul 2018 10:37:45 -0400 Received: from greensocs.com ([193.104.36.180]:50635) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fj3sC-0008Ds-8z; Fri, 27 Jul 2018 10:37:40 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 89B63443552; Fri, 27 Jul 2018 16:37:32 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t87wm-J9GX67; Fri, 27 Jul 2018 16:37:31 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id B6A784434A4; Fri, 27 Jul 2018 16:37:31 +0200 (CEST) Received: from kouign-amann.hive.antfield.fr (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: damien.hedde@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 470F6443548; Fri, 27 Jul 2018 16:37:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532702252; bh=OCks8lWEHQrMx7BDLkkH3U8NABen5kUobqryDET58Pk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=SlvREz96J3eGu0J53zSUVOmF6MG+kMruZOyp6QFAoQydwa+OG8RN/XrnVLVejrBmX kcjuxh5VJmD+KfEqKgzheDwYVt6vHjTIJW3/vbrEl6UVCA+6lH/01Jl0mdToXoT8Cs cUAWfNJoQSKR4Y1TeoN5Lja+5VxEyX5xO6eppEhg= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=2ypbAFVA; dkim=pass (1024-bit key) header.d=greensocs.com header.b=2ypbAFVA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532702251; bh=OCks8lWEHQrMx7BDLkkH3U8NABen5kUobqryDET58Pk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=2ypbAFVAMnIrBd/57IUj3OD7egi2rAslQnEnl0UFOPk/viD2CdxFj3lkK0snEJ1uH AR6dVGEd3UjvdSqW5hZVG7IlN8pQJdbqAPGGMmumGUYhXE/N1K26rCropihnCRny8w 9Lnh0QqnPEy0VnL5+LPivKNBLU8gE0p1OJUiQxNE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532702251; bh=OCks8lWEHQrMx7BDLkkH3U8NABen5kUobqryDET58Pk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=2ypbAFVAMnIrBd/57IUj3OD7egi2rAslQnEnl0UFOPk/viD2CdxFj3lkK0snEJ1uH AR6dVGEd3UjvdSqW5hZVG7IlN8pQJdbqAPGGMmumGUYhXE/N1K26rCropihnCRny8w 9Lnh0QqnPEy0VnL5+LPivKNBLU8gE0p1OJUiQxNE= From: Damien Hedde To: qemu-devel@nongnu.org Date: Fri, 27 Jul 2018 16:37:24 +0200 Message-Id: <172aa4f0544c31a22603c783a836aef3c29d564e.1532701430.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 5/6] zynq_slcr: add uart clock gating and soft reset support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair@alistair23.me, mark.burton@greensocs.com, saipava@xilinx.com, qemu-arm@nongnu.org, Damien Hedde , pbonzini@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Clock gating and reset of uart0 and uart1 is controlled by UART_CLK_CTRL and UART_RST_CTRL. Uart0 and uart1 links are kept in properties to allow taking action. The CLKACT bit in UART_CLK_CTRL is used to driver the clock gating. In order to implement the reset behavior, which can be hold: when reset is asserted, device_reset is called on the uart and the clock is also disabled until reset is deasserted. Signed-off-by: Damien Hedde --- hw/misc/zynq_slcr.c | 63 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index d6bdd027ef..55dd586066 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -168,6 +168,14 @@ enum { #define DDRIOB_LENGTH 14 }; =20 +enum { + UART_CLK_CTRL_CLKACT0 =3D 0x0001, + UART_CLK_CTRL_CLKACT1 =3D 0x0002, + + UART_RST_CTRL_UART0_REF_RST =3D 0x04, + UART_RST_CTRL_UART1_REF_RST =3D 0x08, +}; + #define ZYNQ_SLCR_MMIO_SIZE 0x1000 #define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4) =20 @@ -180,6 +188,9 @@ typedef struct ZynqSLCRState { MemoryRegion iomem; =20 uint32_t regs[ZYNQ_SLCR_NUM_REGS]; + + DeviceState *uart0; + DeviceState *uart1; } ZynqSLCRState; =20 static void zynq_slcr_reset(DeviceState *d) @@ -355,6 +366,35 @@ static uint64_t zynq_slcr_read(void *opaque, hwaddr of= fset, return ret; } =20 +/* + * zynq_slcr_update_clock: + * Update a device clock state given its: + * + clock enable bit + * + reset asserted bit + * Since reset cannot be enabled and disabled, the clock is disabled when + * reset is asserted + */ +static void zynq_slcr_update_clock(DeviceState *dev, bool clken, bool rste= n) +{ + if (dev) { + device_set_clock(dev, clken && !rsten); + } +} + +/* + * zynq_slcr_update_reset: + * Update a device reset state given its: + * + reset asserted bit + * Also trigger a clock update + */ +static void zynq_slcr_update_reset(DeviceState *dev, bool clken, bool rste= n) +{ + if (dev && rsten) { + device_reset(dev); + } + zynq_slcr_update_clock(dev, clken, rsten); +} + static void zynq_slcr_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { @@ -408,6 +448,22 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; + case UART_CLK_CTRL: + zynq_slcr_update_clock(s->uart0, + s->regs[UART_CLK_CTRL] & UART_CLK_CTRL_CLKACT0, + s->regs[UART_RST_CTRL] & UART_RST_CTRL_UART0_REF_RST); + zynq_slcr_update_clock(s->uart1, + s->regs[UART_CLK_CTRL] & UART_CLK_CTRL_CLKACT1, + s->regs[UART_RST_CTRL] & UART_RST_CTRL_UART1_REF_RST); + break; + case UART_RST_CTRL: + zynq_slcr_update_reset(s->uart0, + s->regs[UART_CLK_CTRL] & UART_CLK_CTRL_CLKACT0, + s->regs[UART_RST_CTRL] & UART_RST_CTRL_UART0_REF_RST); + zynq_slcr_update_reset(s->uart1, + s->regs[UART_CLK_CTRL] & UART_CLK_CTRL_CLKACT1, + s->regs[UART_RST_CTRL] & UART_RST_CTRL_UART1_REF_RST); + break; } } =20 @@ -436,12 +492,19 @@ static const VMStateDescription vmstate_zynq_slcr =3D= { } }; =20 +static Property zynq_slcr_properties[] =3D { + DEFINE_PROP_LINK("uart0", ZynqSLCRState, uart0, TYPE_DEVICE, DeviceSta= te *), + DEFINE_PROP_LINK("uart1", ZynqSLCRState, uart1, TYPE_DEVICE, DeviceSta= te *), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->vmsd =3D &vmstate_zynq_slcr; dc->reset =3D zynq_slcr_reset; + dc->props =3D zynq_slcr_properties; } =20 static const TypeInfo zynq_slcr_info =3D { --=20 2.18.0