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b=iseYvR9jBJNYNmGHZoGQKnsKXwzC6byWr+rTHybDAQV3qd0ZrndXho0svPIvaByh7EQK H5uICEWtBsHB2ZGVHXXvKwBB/hYbO2gWWl8ggvXJL8dKz1Ex0tya+KgNjoGnmoXwp8V9 5T7Kr3vScE8pppJU8RihgIwZzboEmA+VXEXTsh4G1Eryw+C2vl/4eWhojdnHPJmSl09s mWqCzdDat0RXfgoEm4yFUNcup0EOAvd2MITi45n52a264bVncB102q/pfWuoBJe7TFe+ Mxijf+74FM5+LxfF5qiKJZLd2Jr+bh39wAtgOOk6k04toYkUVCtS8fZfZes0NS/EzXR/ FA== Subject: [PATCH v8 1/2] ppc: Enable 2nd DAWR support on Power10 PowerNV machine From: Shivaprasad G Bhat To: danielhb413@gmail.com, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, harshpb@linux.ibm.com, clg@kaod.org, npiggin@gmail.com, groug@kaod.org Cc: sbhat@linux.ibm.com, pbonzini@redhat.com, kvm@vger.kernel.org, qemu-devel@nongnu.org Date: Thu, 01 Feb 2024 09:46:22 -0500 Message-ID: <170679877410.188422.2597832350300436754.stgit@ltc-boston1.aus.stglabs.ibm.com> In-Reply-To: <170679876639.188422.11634974895844092362.stgit@ltc-boston1.aus.stglabs.ibm.com> References: <170679876639.188422.11634974895844092362.stgit@ltc-boston1.aus.stglabs.ibm.com> User-Agent: StGit/1.5 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 9S1DR3eqNH0H2GOQhqMwsNSew9HY2ryn X-Proofpoint-ORIG-GUID: Oy0BgFSyxQlkWOhQW9ptbdIpglvu1aVa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-01_02,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=950 priorityscore=1501 mlxscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402010117 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=sbhat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1706798940275100001 Extend the existing watchpoint facility from TCG DAWR0 emulation to DAWR1 on POWER10. Signed-off-by: Shivaprasad G Bhat Reviewed-by: Nicholas Piggin --- target/ppc/cpu.c | 45 ++++++++++++++++++++++++---------- target/ppc/cpu.h | 8 +++++- target/ppc/cpu_init.c | 15 +++++++++++ target/ppc/excp_helper.c | 61 ++++++++++++++++++++++++++----------------= ---- target/ppc/helper.h | 2 ++ target/ppc/machine.c | 3 ++ target/ppc/misc_helper.c | 10 ++++++++ target/ppc/spr_common.h | 2 ++ target/ppc/translate.c | 12 +++++++++ 9 files changed, 115 insertions(+), 43 deletions(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index e3ad8e0c27..d5ac9bb888 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -130,11 +130,13 @@ void ppc_store_ciabr(CPUPPCState *env, target_ulong v= al) ppc_update_ciabr(env); } =20 -void ppc_update_daw0(CPUPPCState *env) +void ppc_update_daw(CPUPPCState *env, int rid) { CPUState *cs =3D env_cpu(env); - target_ulong deaw =3D env->spr[SPR_DAWR0] & PPC_BITMASK(0, 60); - uint32_t dawrx =3D env->spr[SPR_DAWRX0]; + int spr_dawr =3D !rid ? SPR_DAWR0 : SPR_DAWR1; + int spr_dawrx =3D !rid ? SPR_DAWRX0 : SPR_DAWRX1; + target_ulong deaw =3D env->spr[spr_dawr] & PPC_BITMASK(0, 60); + uint32_t dawrx =3D env->spr[spr_dawrx]; int mrd =3D extract32(dawrx, PPC_BIT_NR(48), 54 - 48); bool dw =3D extract32(dawrx, PPC_BIT_NR(57), 1); bool dr =3D extract32(dawrx, PPC_BIT_NR(58), 1); @@ -144,9 +146,9 @@ void ppc_update_daw0(CPUPPCState *env) vaddr len; int flags; =20 - if (env->dawr0_watchpoint) { - cpu_watchpoint_remove_by_ref(cs, env->dawr0_watchpoint); - env->dawr0_watchpoint =3D NULL; + if (env->dawr_watchpoint[rid]) { + cpu_watchpoint_remove_by_ref(cs, env->dawr_watchpoint[rid]); + env->dawr_watchpoint[rid] =3D NULL; } =20 if (!dr && !dw) { @@ -166,28 +168,45 @@ void ppc_update_daw0(CPUPPCState *env) flags |=3D BP_MEM_WRITE; } =20 - cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr0_watchpoint); + cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr_watchpoint[rid]= ); } =20 void ppc_store_dawr0(CPUPPCState *env, target_ulong val) { env->spr[SPR_DAWR0] =3D val; - ppc_update_daw0(env); + ppc_update_daw(env, 0); } =20 -void ppc_store_dawrx0(CPUPPCState *env, uint32_t val) +static void ppc_store_dawrx(CPUPPCState *env, uint32_t val, int rid) { int hrammc =3D extract32(val, PPC_BIT_NR(56), 1); =20 if (hrammc) { /* This might be done with a second watchpoint at the xor of DEAW[= 0] */ - qemu_log_mask(LOG_UNIMP, "%s: DAWRX0[HRAMMC] is unimplemented\n", - __func__); + qemu_log_mask(LOG_UNIMP, "%s: DAWRX%d[HRAMMC] is unimplemented\n", + __func__, rid); } =20 - env->spr[SPR_DAWRX0] =3D val; - ppc_update_daw0(env); + env->spr[!rid ? SPR_DAWRX0 : SPR_DAWRX1] =3D val; + ppc_update_daw(env, rid); +} + +void ppc_store_dawrx0(CPUPPCState *env, uint32_t val) +{ + ppc_store_dawrx(env, val, 0); +} + +void ppc_store_dawr1(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_DAWR1] =3D val; + ppc_update_daw(env, 1); +} + +void ppc_store_dawrx1(CPUPPCState *env, uint32_t val) +{ + ppc_store_dawrx(env, val, 1); } + #endif #endif =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..18dcc438ea 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1236,7 +1236,7 @@ struct CPUArchState { #if defined(TARGET_PPC64) ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ struct CPUBreakpoint *ciabr_breakpoint; - struct CPUWatchpoint *dawr0_watchpoint; + struct CPUWatchpoint *dawr_watchpoint[2]; #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ @@ -1549,9 +1549,11 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong v= alue); void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); void ppc_update_ciabr(CPUPPCState *env); void ppc_store_ciabr(CPUPPCState *env, target_ulong value); -void ppc_update_daw0(CPUPPCState *env); +void ppc_update_daw(CPUPPCState *env, int rid); void ppc_store_dawr0(CPUPPCState *env, target_ulong value); void ppc_store_dawrx0(CPUPPCState *env, uint32_t value); +void ppc_store_dawr1(CPUPPCState *env, target_ulong value); +void ppc_store_dawrx1(CPUPPCState *env, uint32_t value); #endif /* !defined(CONFIG_USER_ONLY) */ void ppc_store_msr(CPUPPCState *env, target_ulong value); =20 @@ -1737,9 +1739,11 @@ void ppc_compat_add_property(Object *obj, const char= *name, #define SPR_PSPB (0x09F) #define SPR_DPDES (0x0B0) #define SPR_DAWR0 (0x0B4) +#define SPR_DAWR1 (0x0B5) #define SPR_RPR (0x0BA) #define SPR_CIABR (0x0BB) #define SPR_DAWRX0 (0x0BC) +#define SPR_DAWRX1 (0x0BD) #define SPR_HFSCR (0x0BE) #define SPR_VRSAVE (0x100) #define SPR_USPRG0 (0x100) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23eb5522b6..c901559859 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5131,6 +5131,20 @@ static void register_book3s_207_dbg_sprs(CPUPPCState= *env) KVM_REG_PPC_CIABR, 0x00000000); } =20 +static void register_book3s_310_dbg_sprs(CPUPPCState *env) +{ + spr_register_kvm_hv(env, SPR_DAWR1, "DAWR1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_dawr1, + KVM_REG_PPC_DAWR1, 0x00000000); + spr_register_kvm_hv(env, SPR_DAWRX1, "DAWRX1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_dawrx1, + KVM_REG_PPC_DAWRX1, 0x00000000); +} + static void register_970_dbg_sprs(CPUPPCState *env) { /* Breakpoints */ @@ -6473,6 +6487,7 @@ static void init_proc_POWER10(CPUPPCState *env) /* Common Registers */ init_proc_book3s_common(env); register_book3s_207_dbg_sprs(env); + register_book3s_310_dbg_sprs(env); =20 /* Common TCG PMU */ init_tcg_pmu_power8(env); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2ec6429e36..32eba7f725 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3314,39 +3314,46 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, C= PUWatchpoint *wp) { #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); + bool wt, wti, hv, sv, pr; + uint32_t dawrx; + + if ((env->insns_flags2 & PPC2_ISA207S) && + (wp =3D=3D env->dawr_watchpoint[0])) { + dawrx =3D env->spr[SPR_DAWRX0]; + } else if ((env->insns_flags2 & PPC2_ISA310) && + (wp =3D=3D env->dawr_watchpoint[1])) { + dawrx =3D env->spr[SPR_DAWRX1]; + } else { + return false; + } =20 - if (env->insns_flags2 & PPC2_ISA207S) { - if (wp =3D=3D env->dawr0_watchpoint) { - uint32_t dawrx =3D env->spr[SPR_DAWRX0]; - bool wt =3D extract32(dawrx, PPC_BIT_NR(59), 1); - bool wti =3D extract32(dawrx, PPC_BIT_NR(60), 1); - bool hv =3D extract32(dawrx, PPC_BIT_NR(61), 1); - bool sv =3D extract32(dawrx, PPC_BIT_NR(62), 1); - bool pr =3D extract32(dawrx, PPC_BIT_NR(62), 1); - - if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) { - return false; - } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { - return false; - } else if (!sv) { + wt =3D extract32(dawrx, PPC_BIT_NR(59), 1); + wti =3D extract32(dawrx, PPC_BIT_NR(60), 1); + hv =3D extract32(dawrx, PPC_BIT_NR(61), 1); + sv =3D extract32(dawrx, PPC_BIT_NR(62), 1); + pr =3D extract32(dawrx, PPC_BIT_NR(62), 1); + + if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) { + return false; + } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { + return false; + } else if (!sv) { + return false; + } + + if (!wti) { + if (env->msr & ((target_ulong)1 << MSR_DR)) { + if (!wt) { return false; } - - if (!wti) { - if (env->msr & ((target_ulong)1 << MSR_DR)) { - if (!wt) { - return false; - } - } else { - if (wt) { - return false; - } - } + } else { + if (wt) { + return false; } - - return true; } } + + return true; #endif =20 return false; diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 86f97ee1e7..0c008bb725 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -28,6 +28,8 @@ DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_ciabr, void, env, tl) DEF_HELPER_2(store_dawr0, void, env, tl) DEF_HELPER_2(store_dawrx0, void, env, tl) +DEF_HELPER_2(store_dawr1, void, env, tl) +DEF_HELPER_2(store_dawrx1, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 203fe28e01..082712ff16 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -325,7 +325,8 @@ static int cpu_post_load(void *opaque, int version_id) /* Re-set breaks based on regs */ #if defined(TARGET_PPC64) ppc_update_ciabr(env); - ppc_update_daw0(env); + ppc_update_daw(env, 0); + ppc_update_daw(env, 1); #endif /* * TCG needs to re-start the decrementer timer and/or raise the diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index a9d41d2802..54e402b139 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -214,6 +214,16 @@ void helper_store_dawrx0(CPUPPCState *env, target_ulon= g value) ppc_store_dawrx0(env, value); } =20 +void helper_store_dawr1(CPUPPCState *env, target_ulong value) +{ + ppc_store_dawr1(env, value); +} + +void helper_store_dawrx1(CPUPPCState *env, target_ulong value) +{ + ppc_store_dawrx1(env, value); +} + /* * DPDES register is shared. Each bit reflects the state of the * doorbell interrupt of a thread of the same core. diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 8a9d6cd994..c987a50809 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -162,6 +162,8 @@ void spr_write_cfar(DisasContext *ctx, int sprn, int gp= rn); void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn); void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn); void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn); +void spr_write_dawr1(DisasContext *ctx, int sprn, int gprn); +void spr_write_dawrx1(DisasContext *ctx, int sprn, int gprn); void spr_write_ureg(DisasContext *ctx, int sprn, int gprn); void spr_read_purr(DisasContext *ctx, int gprn, int sprn); void spr_write_purr(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 049f636927..ac2a53f3b8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -593,6 +593,18 @@ void spr_write_dawrx0(DisasContext *ctx, int sprn, int= gprn) translator_io_start(&ctx->base); gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]); } + +void spr_write_dawr1(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_dawr1(tcg_env, cpu_gpr[gprn]); +} + +void spr_write_dawrx1(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_dawrx1(tcg_env, cpu_gpr[gprn]); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ =20 /* CTR */ From nobody Tue May 14 23:09:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1706798935; cv=none; d=zohomail.com; s=zohoarc; b=YIK2Xc4Ca06q1NXySqYg9+ZRdHv9uU8tBpYNKtDBfmAJrrs1MC+DdOmCQeDpHXU9dRIVJtQ4Ga7NIAlH6Yw8C96QEXwrlvA6R1VG0TcM5MoUVMJhepI2LhG5/BrKcjTis5B7k+FjLEnoQb4bgR13f7CjbwBaxjMrOtB2TNo4Ok4= ARC-Message-Signature: i=1; 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Thu, 1 Feb 2024 14:46:36 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=subject : from : to : cc : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pp1; bh=Leqba0Wk9P5GGbwUCd+rQ2YN2BcrPM5njL6io32kLFk=; b=PU5zC4f4SdWVXm4eiQroy9P0TtgpeDN8nux3FE9x6PFVatmxyOv7gmg8PdpFTi6rjBm5 EOJZFOuENoBrI0gpmEWtFGqIv//74YCWRxeUIAdqK6OVo64V4OuXe9n+hEn/ad7X2ZqT 0TPg8YclTIGndxXnnpXY0dBUOulqJoaQzrt6Lyfl/kcObawLq11jSgQfBlgzluCOnMKa 2ucMv5g4CbbYKtUPTJn0bjWQK4g2NrodLQDuQkJHbGng/z7lUqjcHDPqF8cuH31Mv/Hj ik9X2gPLcw6aJHVoxINUV7xLfDo3mbnBNDAtohlU8EOtQBLXCS92r0S21o7EGV6BW2iq hw== Subject: [PATCH v8 2/2] ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine From: Shivaprasad G Bhat To: danielhb413@gmail.com, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, harshpb@linux.ibm.com, clg@kaod.org, npiggin@gmail.com, groug@kaod.org Cc: sbhat@linux.ibm.com, pbonzini@redhat.com, kvm@vger.kernel.org, qemu-devel@nongnu.org Date: Thu, 01 Feb 2024 09:46:35 -0500 Message-ID: <170679878985.188422.6745903342602285494.stgit@ltc-boston1.aus.stglabs.ibm.com> In-Reply-To: <170679876639.188422.11634974895844092362.stgit@ltc-boston1.aus.stglabs.ibm.com> References: <170679876639.188422.11634974895844092362.stgit@ltc-boston1.aus.stglabs.ibm.com> User-Agent: StGit/1.5 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 62Qv25RKOvaahl6JNHYKjHIx940YlQgA X-Proofpoint-ORIG-GUID: 465ySTv3rh7mTY3YOTBDU8FesB_CH-MN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-01_02,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=416 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402010117 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=sbhat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1706798936286100001 As per the PAPR, bit 0 of byte 64 in pa-features property indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find whether kvm supports 2nd DAWR or not. If it's supported, allow user to set the pa-feature bit in guest DT using cap-dawr1 machine capability. Signed-off-by: Ravi Bangoria Signed-off-by: Shivaprasad G Bhat Reviewed-by: Nicholas Piggin --- hw/ppc/spapr.c | 7 ++++++- hw/ppc/spapr_caps.c | 36 ++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_hcall.c | 25 ++++++++++++++++--------- include/hw/ppc/spapr.h | 6 +++++- target/ppc/kvm.c | 12 ++++++++++++ target/ppc/kvm_ppc.h | 12 ++++++++++++ 6 files changed, 87 insertions(+), 11 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e8dabc8614..91a97d72e7 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -262,7 +262,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spa= pr, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ /* 54: DecFP, 56: DecI, 58: SHA */ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ - /* 60: NM atomic, 62: RNG */ + /* 60: NM atomic, 62: RNG, 64: DAWR1 (ISA 3.1) */ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ }; uint8_t *pa_features =3D NULL; @@ -303,6 +303,9 @@ static void spapr_dt_pa_features(SpaprMachineState *spa= pr, * in pa-features. So hide it from them. */ pa_features[40 + 2] &=3D ~0x80; /* Radix MMU */ } + if (spapr_get_cap(spapr, SPAPR_CAP_DAWR1)) { + pa_features[66] |=3D 0x80; + } =20 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size= ))); } @@ -2138,6 +2141,7 @@ static const VMStateDescription vmstate_spapr =3D { &vmstate_spapr_cap_fwnmi, &vmstate_spapr_fwnmi, &vmstate_spapr_cap_rpt_invalidate, + &vmstate_spapr_cap_dawr1, NULL } }; @@ -4717,6 +4721,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_FWNMI] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_DAWR1] =3D SPAPR_CAP_OFF; =20 /* * This cap specifies whether the AIL 3 mode for diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index e889244e52..677f17cea6 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -655,6 +655,32 @@ static void cap_ail_mode_3_apply(SpaprMachineState *sp= apr, } } =20 +static void cap_dawr1_apply(SpaprMachineState *spapr, uint8_t val, + Error **errp) +{ + ERRP_GUARD(); + + if (!val) { + return; /* Disable by default */ + } + + if (!ppc_type_check_compat(MACHINE(spapr)->cpu_type, + CPU_POWERPC_LOGICAL_3_10, 0, + spapr->max_compat_pvr)) { + warn_report("DAWR1 supported only on POWER10 and later CPUs"); + } + + if (kvm_enabled()) { + if (!kvmppc_has_cap_dawr1()) { + error_setg(errp, "DAWR1 not supported by KVM."); + error_append_hint(errp, "Try appending -machine cap-dawr1=3Dof= f"); + } else if (kvmppc_set_cap_dawr1(val) < 0) { + error_setg(errp, "Error enabling cap-dawr1 with KVM."); + error_append_hint(errp, "Try appending -machine cap-dawr1=3Dof= f"); + } + } +} + SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] =3D { [SPAPR_CAP_HTM] =3D { .name =3D "htm", @@ -781,6 +807,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = =3D { .type =3D "bool", .apply =3D cap_ail_mode_3_apply, }, + [SPAPR_CAP_DAWR1] =3D { + .name =3D "dawr1", + .description =3D "Allow 2nd Data Address Watchpoint Register (DAWR= 1)", + .index =3D SPAPR_CAP_DAWR1, + .get =3D spapr_cap_get_bool, + .set =3D spapr_cap_set_bool, + .type =3D "bool", + .apply =3D cap_dawr1_apply, + }, }; =20 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, @@ -923,6 +958,7 @@ SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREME= NTER); SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI); SPAPR_CAP_MIG_STATE(rpt_invalidate, SPAPR_CAP_RPT_INVALIDATE); +SPAPR_CAP_MIG_STATE(dawr1, SPAPR_CAP_DAWR1); =20 void spapr_caps_init(SpaprMachineState *spapr) { diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index fcefd1d1c7..34c1c77c95 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -814,11 +814,12 @@ static target_ulong h_set_mode_resource_set_ciabr(Pow= erPCCPU *cpu, return H_SUCCESS; } =20 -static target_ulong h_set_mode_resource_set_dawr0(PowerPCCPU *cpu, - SpaprMachineState *spapr, - target_ulong mflags, - target_ulong value1, - target_ulong value2) +static target_ulong h_set_mode_resource_set_dawr(PowerPCCPU *cpu, + SpaprMachineState *sp= apr, + target_ulong mflags, + target_ulong resource, + target_ulong value1, + target_ulong value2) { CPUPPCState *env =3D &cpu->env; =20 @@ -831,8 +832,13 @@ static target_ulong h_set_mode_resource_set_dawr0(Powe= rPCCPU *cpu, return H_P4; } =20 - ppc_store_dawr0(env, value1); - ppc_store_dawrx0(env, value2); + if (resource =3D=3D H_SET_MODE_RESOURCE_SET_DAWR0) { + ppc_store_dawr0(env, value1); + ppc_store_dawrx0(env, value2); + } else { + ppc_store_dawr1(env, value1); + ppc_store_dawrx1(env, value2); + } =20 return H_SUCCESS; } @@ -911,8 +917,9 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMa= chineState *spapr, args[3]); break; case H_SET_MODE_RESOURCE_SET_DAWR0: - ret =3D h_set_mode_resource_set_dawr0(cpu, spapr, args[0], args[2], - args[3]); + case H_SET_MODE_RESOURCE_SET_DAWR1: + ret =3D h_set_mode_resource_set_dawr(cpu, spapr, args[0], args[1], + args[2], args[3]); break; case H_SET_MODE_RESOURCE_LE: ret =3D h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[= 3]); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index e91791a1a9..2b13c9a00e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -80,8 +80,10 @@ typedef enum { #define SPAPR_CAP_RPT_INVALIDATE 0x0B /* Support for AIL modes */ #define SPAPR_CAP_AIL_MODE_3 0x0C +/* DAWR1 */ +#define SPAPR_CAP_DAWR1 0x0D /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_DAWR1 + 1) =20 /* * Capability Values @@ -403,6 +405,7 @@ struct SpaprMachineState { #define H_SET_MODE_RESOURCE_SET_DAWR0 2 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 #define H_SET_MODE_RESOURCE_LE 4 +#define H_SET_MODE_RESOURCE_SET_DAWR1 5 =20 /* Flags for H_SET_MODE_RESOURCE_LE */ #define H_SET_MODE_ENDIAN_BIG 0 @@ -986,6 +989,7 @@ extern const VMStateDescription vmstate_spapr_cap_ccf_a= ssist; extern const VMStateDescription vmstate_spapr_cap_fwnmi; extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; extern const VMStateDescription vmstate_spapr_wdt; +extern const VMStateDescription vmstate_spapr_cap_dawr1; =20 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) { diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 26fa9d0575..3d8a8f35b6 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -89,6 +89,7 @@ static int cap_large_decr; static int cap_fwnmi; static int cap_rpt_invalidate; static int cap_ail_mode_3; +static int cap_dawr1; =20 static uint32_t debug_inst_opcode; =20 @@ -143,6 +144,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) cap_ppc_nested_kvm_hv =3D kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED= _HV); cap_large_decr =3D kvmppc_get_dec_bits(); cap_fwnmi =3D kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI); + cap_dawr1 =3D kvm_vm_check_extension(s, KVM_CAP_PPC_DAWR1); /* * Note: setting it to false because there is not such capability * in KVM at this moment. @@ -2109,6 +2111,16 @@ int kvmppc_set_fwnmi(PowerPCCPU *cpu) return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); } =20 +bool kvmppc_has_cap_dawr1(void) +{ + return !!cap_dawr1; +} + +int kvmppc_set_cap_dawr1(int enable) +{ + return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_DAWR1, 0, enable); +} + int kvmppc_smt_threads(void) { return cap_ppc_smt ? cap_ppc_smt : 1; diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 1975fb5ee6..493d6bb477 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -68,6 +68,8 @@ bool kvmppc_has_cap_htm(void); bool kvmppc_has_cap_mmu_radix(void); bool kvmppc_has_cap_mmu_hash_v3(void); bool kvmppc_has_cap_xive(void); +bool kvmppc_has_cap_dawr1(void); +int kvmppc_set_cap_dawr1(int enable); int kvmppc_get_cap_safe_cache(void); int kvmppc_get_cap_safe_bounds_check(void); int kvmppc_get_cap_safe_indirect_branch(void); @@ -377,6 +379,16 @@ static inline bool kvmppc_has_cap_xive(void) return false; } =20 +static inline bool kvmppc_has_cap_dawr1(void) +{ + return false; +} + +static inline int kvmppc_set_cap_dawr1(int enable) +{ + abort(); +} + static inline int kvmppc_get_cap_safe_cache(void) { return 0;