From nobody Wed Nov 27 04:31:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701524513133763.938703209957; Sat, 2 Dec 2023 05:41:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r9QEt-0005BD-ML; Sat, 02 Dec 2023 08:40:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r9QEs-0005Ah-Ed for qemu-devel@nongnu.org; Sat, 02 Dec 2023 08:40:58 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r9QEp-000063-CB for qemu-devel@nongnu.org; Sat, 02 Dec 2023 08:40:56 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 979E811F365; Sat, 2 Dec 2023 13:40:35 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~lbryndza Date: Sat, 02 Dec 2023 13:20:29 +0100 Subject: [PATCH qemu v3 13/20] Fixing the basic functionality of STM32 timers Message-ID: <170152443229.18048.53824064267512246-13@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <170152443229.18048.53824064267512246-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: Alistair Francis , Peter Maydell Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~lbryndza Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1701524514072000001 From: Lucjan Bryndza The current implementation of timers does not work properly even in basic functionality. A counter configured to report an interrupt every 10ms reports the first interrupts after a few seconds. There are also no properly implemented count up an count down modes. This commit fixes bugs with interrupt reporting and implements the basic modes of the counter's time-base block. Add update egr function Signed-off-by: Lucjan Bryndza --- hw/timer/stm32f2xx_timer.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c index 3997521610..010b5b41bd 100644 --- a/hw/timer/stm32f2xx_timer.c +++ b/hw/timer/stm32f2xx_timer.c @@ -233,6 +233,21 @@ static void stm32f2xx_update_psc(STM32F2XXTimerState *= s, uint64_t value) ptimer_transaction_commit(s->timer); DB_PRINT("write psc =3D %x\n", s->tim_psc); } + +static void stm32f2xx_update_egr(STM32F2XXTimerState *s, uint64_t value) +{ + s->tim_egr =3D value & 0x1E; + if (value & TIM_EGR_TG) { + s->tim_sr |=3D TIM_EGR_TG; + } + if (value & TIM_EGR_UG) { + /* UG bit - reload */ + ptimer_transaction_begin(s->timer); + ptimer_set_limit(s->timer, s->tim_arr, 1); + ptimer_transaction_commit(s->timer); + } + DB_PRINT("write EGR =3D %x\n", s->tim_egr); +} static void stm32f2xx_timer_write(void *opaque, hwaddr offset, uint64_t val64, unsigned size) { --=20 2.38.5