From nobody Sun Sep 14 20:30:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=ispras.ru ARC-Seal: i=1; a=rsa-sha256; t=1674120482; cv=none; d=zohomail.com; s=zohoarc; b=aMxPoYndVlYJKNjRhsaAyNIpy1iI731iIElc+lpsXweT1qAUavofLJ2jCUrcmVJ/Ehe0DimI29PIaKA/1d23ykn4ctLv3hheNDHSLH+PtL3qfRhTfAwGj+4iIwEvfrxw+78JEqipELqxT/FiXVLhCKSODxdWwEIquEGPbEqDamc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674120482; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o/aySluarGl07VSrD5n+eG+q632Cw4z1i55Kl2eM+0w=; b=Q5Iklo/Sw7xyUQayvMA81Zl8wtX01LLYFIfyLr2e8eYHqPZeJU3ULK0chSUdEsHk3EI0T+t86G4lWvqyrBpKaDPJeGhUx6ObqU3KRSdMGlYHXP/jw5A70HojG90vzvAxmUMxSvhqm4XATL3ralgpCCq1t/iqL/azAbzZGhgmJJA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16741204820201015.1401889139728; Thu, 19 Jan 2023 01:28:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIR8e-0004Gi-Kp; Thu, 19 Jan 2023 04:23:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8c-0004Fr-C1 for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:14 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8a-0006GB-QT for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:14 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 79B9940737AC; Thu, 19 Jan 2023 09:23:10 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 79B9940737AC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1674120190; bh=o/aySluarGl07VSrD5n+eG+q632Cw4z1i55Kl2eM+0w=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=qBKD1+0y7kBIVdZM1SqrydJ0u8hnbFgpgK1H5tnQgLkhorLXX+tTce4k6q1BgNaMg yqLusJRV5O73d+VUICUS4rYZk056ElejZtpa9SWyiKdCTtpxnl2R39VKPm1MPznfaD MXe9nn+5t5zLxpyexT/ZaZ73gf8NxXLBSRG9kad8= Subject: [PATCH v2 5/5] target/avr: enable icount mode From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Thu, 19 Jan 2023 12:23:10 +0300 Message-ID: <167412019026.3110454.15241120845845520583.stgit@pasha-ThinkPad-X280> In-Reply-To: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> References: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ispras.ru) X-ZM-MESSAGEID: 1674120483816100001 Icount mode requires correct can_do_io flag management for checking that IO operations are performed only in the last TB instruction. This patch sets this flag before every helper which can lead to virtual hardware access. It enables deterministic execution in icount mode for AVR. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Richard Henderson --- target/avr/translate.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 40b15d116e..ee137dfe54 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1406,6 +1406,10 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *= a) { TCGv temp =3D tcg_const_i32(a->reg); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(temp, cpu_env, temp); tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond =3D TCG_COND_EQ; @@ -1424,6 +1428,10 @@ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *= a) { TCGv temp =3D tcg_const_i32(a->reg); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(temp, cpu_env, temp); tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond =3D TCG_COND_NE; @@ -1621,6 +1629,9 @@ static TCGv gen_get_zaddr(DisasContext *ctx, bool ram) static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_fullwr(cpu_env, data, addr); } else { tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] =3D data = */ @@ -1630,6 +1641,9 @@ static void gen_data_store(DisasContext *ctx, TCGv da= ta, TCGv addr) static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_fullrd(data, cpu_env, addr); } else { tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data =3D mem[addr]= */ @@ -2335,6 +2349,10 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) TCGv Rd =3D cpu_r[a->rd]; TCGv port =3D tcg_const_i32(a->imm); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(Rd, cpu_env, port); =20 tcg_temp_free_i32(port); @@ -2351,6 +2369,10 @@ static bool trans_OUT(DisasContext *ctx, arg_OUT *a) TCGv Rd =3D cpu_r[a->rd]; TCGv port =3D tcg_const_i32(a->imm); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_outb(cpu_env, port, Rd); =20 tcg_temp_free_i32(port); @@ -2651,6 +2673,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) TCGv data =3D tcg_temp_new_i32(); TCGv port =3D tcg_const_i32(a->reg); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(data, cpu_env, port); tcg_gen_ori_tl(data, data, 1 << a->bit); gen_helper_outb(cpu_env, port, data); @@ -2670,6 +2696,10 @@ static bool trans_CBI(DisasContext *ctx, arg_CBI *a) TCGv data =3D tcg_temp_new_i32(); TCGv port =3D tcg_const_i32(a->reg); =20 + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(data, cpu_env, port); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); gen_helper_outb(cpu_env, port, data);