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envelope-from=Babu.Moger@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1670010517200100001 Add the following feature bits. no-nested-data-bp : Processor ignores nested data breakpoints. lfence-always-serializing : LFENCE instruction is always serializing. null-select-clears-base : Null Selector Clears Base. When this bit is set, a null segment load clears the segment bas= e. The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. AMD64 Architecture Programmer=E2=80=99s Manual Volumes 1=E2=80=935 Publi= cation No. Revision 40332 4.05 Date October 2022 Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf Signed-off-by: Babu Moger --- target/i386/cpu.c | 24 ++++++++++++++++++++++++ target/i386/cpu.h | 8 ++++++++ 2 files changed, 32 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b20e422b2e..e9175da92f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -918,6 +918,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .tcg_features =3D 0, .unmigratable_flags =3D 0, }, + [FEAT_8000_0021_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, + NULL, NULL, "null-select-clears-base", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { .eax =3D 0x80000021, .reg =3D R_EAX, }, + .tcg_features =3D 0, + .unmigratable_flags =3D 0, + }, [FEAT_XSAVE] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -6002,6 +6018,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ebx |=3D sev_get_reduced_phys_bits() << 6; } break; + case 0x80000021: + *eax =3D env->features[FEAT_8000_0021_EAX]; + *ebx =3D *ecx =3D *edx =3D 0; + break; default: /* reserved values: zero */ *eax =3D 0; @@ -6429,6 +6449,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); } =20 + if (env->features[FEAT_8000_0021_EAX]) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); + } + /* SGX requires CPUID[0x12] for EPC enumeration */ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8c65c92131..42b347051a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -597,6 +597,7 @@ typedef enum FeatureWord { FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ + FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ @@ -925,6 +926,13 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWor= d w, /* Predictive Store Forwarding Disable */ #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) =20 +/* Processor ignores nested data breakpoints */ +#define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0) +/* LFENCE is always serializing */ +#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) +/* Null Selector Clears Base */ +#define CPUID_8000_0021_EAX_NULL_SELECT_CLEARS_BASE (1U << 6) + #define CPUID_XSAVE_XSAVEOPT (1U << 0) #define CPUID_XSAVE_XSAVEC (1U << 1) #define CPUID_XSAVE_XGETBV1 (1U << 2)