From nobody Wed May 1 02:32:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669909498532812.1906431948985; Thu, 1 Dec 2022 07:44:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0lhW-0005Je-2I; Thu, 01 Dec 2022 10:42:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhN-0005Ep-DC; Thu, 01 Dec 2022 10:42:05 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhL-0004vw-0j; Thu, 01 Dec 2022 10:42:05 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 0AC7C11F204; Thu, 1 Dec 2022 15:42:01 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~axelheider Date: Tue, 25 Oct 2022 17:33:43 +0200 Subject: [PATCH qemu.git v3 1/8] hw/timer/imx_epit: improve comments Message-ID: <166990932074.29941.8709118178538288040-1@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166990932074.29941.8709118178538288040-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1669909498936100001 From: Axel Heider Fix typos, add background information Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index ec0fa440d7..2841fbaa1c 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -96,13 +96,14 @@ static void imx_epit_set_freq(IMXEPITState *s) } } =20 +/* + * This is called both on hardware (device) reset and software reset. + */ static void imx_epit_reset(DeviceState *dev) { IMXEPITState *s =3D IMX_EPIT(dev); =20 - /* - * Soft reset doesn't touch some bits; hard reset clears them - */ + /* Soft reset doesn't touch some bits; hard reset clears them */ s->cr &=3D (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); s->sr =3D 0; s->lr =3D EPIT_TIMER_MAX; @@ -214,6 +215,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); =20 + /* Update the frequency. Has been done already in case of a reset.= */ if (!(s->cr & CR_SWR)) { imx_epit_set_freq(s); } @@ -254,7 +256,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, break; =20 case 1: /* SR - ACK*/ - /* writing 1 to OCIF clear the OCIF bit */ + /* writing 1 to OCIF clears the OCIF bit */ if (value & 0x01) { s->sr =3D 0; imx_epit_update_int(s); @@ -352,8 +354,18 @@ static void imx_epit_realize(DeviceState *dev, Error *= *errp) 0x00001000); sysbus_init_mmio(sbd, &s->iomem); =20 + /* + * The reload timer keeps running when the peripheral is enabled. It i= s a + * kind of wall clock that does not generate any interrupts. The callb= ack + * needs to be provided, but it does nothing as the ptimer already sup= ports + * all necessary reloading functionality. + */ s->timer_reload =3D ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGA= CY); =20 + /* + * The compare timer is running only when the peripheral configuration= is + * in a state that will generate compare interrupts. + */ s->timer_cmp =3D ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); } =20 --=20 2.34.5 From nobody Wed May 1 02:32:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669909500386843.8771950246598; Thu, 1 Dec 2022 07:45:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0lhW-0005Jl-6k; Thu, 01 Dec 2022 10:42:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhN-0005En-9Y; Thu, 01 Dec 2022 10:42:05 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhK-0004vz-HY; Thu, 01 Dec 2022 10:42:05 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 24FEC11F994; Thu, 1 Dec 2022 15:42:01 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~axelheider Date: Mon, 31 Oct 2022 00:59:29 +0100 Subject: [PATCH qemu.git v3 2/8] hw/timer/imx_epit: cleanup CR defines Message-ID: <166990932074.29941.8709118178538288040-2@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166990932074.29941.8709118178538288040-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1669909500933100005 From: Axel Heider remove unused defines, add needed defines Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 4 ++-- include/hw/timer/imx_epit.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 2841fbaa1c..661e9158e3 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -82,8 +82,8 @@ static void imx_epit_set_freq(IMXEPITState *s) uint32_t clksrc; uint32_t prescaler; =20 - clksrc =3D extract32(s->cr, CR_CLKSRC_SHIFT, 2); - prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12); + clksrc =3D extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); + prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS= ); =20 s->freq =3D imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]) / prescaler; diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index 2acc41e982..e2cb96229b 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -43,7 +43,7 @@ #define CR_OCIEN (1 << 2) #define CR_RLD (1 << 3) #define CR_PRESCALE_SHIFT (4) -#define CR_PRESCALE_MASK (0xfff) +#define CR_PRESCALE_BITS (12) #define CR_SWR (1 << 16) #define CR_IOVW (1 << 17) #define CR_DBGEN (1 << 18) @@ -51,7 +51,7 @@ #define CR_DOZEN (1 << 20) #define CR_STOPEN (1 << 21) #define CR_CLKSRC_SHIFT (24) -#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT) +#define CR_CLKSRC_BITS (2) =20 #define EPIT_TIMER_MAX 0XFFFFFFFFUL =20 --=20 2.34.5 From nobody Wed May 1 02:32:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669909408403785.3649943835657; Thu, 1 Dec 2022 07:43:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0lhN-0005FC-Sd; Thu, 01 Dec 2022 10:42:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhM-0005EA-7M; Thu, 01 Dec 2022 10:42:04 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhK-0004w1-HJ; Thu, 01 Dec 2022 10:42:03 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 4BC6211F996; Thu, 1 Dec 2022 15:42:01 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~axelheider Date: Sat, 19 Nov 2022 15:59:40 +0100 Subject: [PATCH qemu.git v3 3/8] hw/timer/imx_epit: define SR_OCIF Message-ID: <166990932074.29941.8709118178538288040-3@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166990932074.29941.8709118178538288040-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1669909410283100007 From: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 12 ++++++------ include/hw/timer/imx_epit.h | 2 ++ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 661e9158e3..f148868b8c 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -66,7 +66,7 @@ static const IMXClk imx_epit_clocks[] =3D { */ static void imx_epit_update_int(IMXEPITState *s) { - if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { + if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { qemu_irq_raise(s->irq); } else { qemu_irq_lower(s->irq); @@ -256,9 +256,9 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, break; =20 case 1: /* SR - ACK*/ - /* writing 1 to OCIF clears the OCIF bit */ - if (value & 0x01) { - s->sr =3D 0; + /* writing 1 to SR.OCIF clears this bit and turns the interrupt of= f */ + if (value & SR_OCIF) { + s->sr =3D 0; /* SR.OCIF is the only bit in this register anywa= y */ imx_epit_update_int(s); } break; @@ -309,8 +309,8 @@ static void imx_epit_cmp(void *opaque) IMXEPITState *s =3D IMX_EPIT(opaque); =20 DPRINTF("sr was %d\n", s->sr); - - s->sr =3D 1; + /* Set interrupt status bit SR.OCIF and update the interrupt state */ + s->sr |=3D SR_OCIF; imx_epit_update_int(s); } =20 diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index e2cb96229b..783eaf0c3a 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -53,6 +53,8 @@ #define CR_CLKSRC_SHIFT (24) #define CR_CLKSRC_BITS (2) =20 +#define SR_OCIF (1 << 0) + #define EPIT_TIMER_MAX 0XFFFFFFFFUL =20 #define TYPE_IMX_EPIT "imx.epit" --=20 2.34.5 From nobody Wed May 1 02:32:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669909354979321.4376407872985; Thu, 1 Dec 2022 07:42:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0lhO-0005Fy-Pc; Thu, 01 Dec 2022 10:42:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhM-0005E9-4G; Thu, 01 Dec 2022 10:42:04 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhK-0004w2-FZ; Thu, 01 Dec 2022 10:42:03 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 6865F11F99F; Thu, 1 Dec 2022 15:42:01 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~axelheider Date: Tue, 25 Oct 2022 20:32:30 +0200 Subject: [PATCH qemu.git v3 4/8] hw/timer/imx_epit: update interrupt state on CR write access Message-ID: <166990932074.29941.8709118178538288040-4@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166990932074.29941.8709118178538288040-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1669909356278100001 From: Axel Heider The interrupt state can change due to: - reset clears both SR.OCIF and CR.OCIE - write to CR.EN or CR.OCIE Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index f148868b8c..7af3a8b10e 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -206,12 +206,20 @@ static void imx_epit_write(void *opaque, hwaddr offse= t, uint64_t value, if (s->cr & CR_SWR) { /* handle the reset */ imx_epit_reset(DEVICE(s)); - /* - * TODO: could we 'break' here? following operations appear - * to duplicate the work imx_epit_reset() already did. - */ } =20 + /* + * The interrupt state can change due to: + * - reset clears both SR.OCIF and CR.OCIE + * - write to CR.EN or CR.OCIE + */ + imx_epit_update_int(s); + + /* + * TODO: could we 'break' here for reset? following operations app= ear + * to duplicate the work imx_epit_reset() already did. + */ + ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); =20 --=20 2.34.5 From nobody Wed May 1 02:32:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669909367654635.2355964320699; Thu, 1 Dec 2022 07:42:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0lhT-0005IP-48; Thu, 01 Dec 2022 10:42:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhO-0005Fx-HD; Thu, 01 Dec 2022 10:42:06 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhM-0004wl-KH; Thu, 01 Dec 2022 10:42:06 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 84CDB11F9A0; Thu, 1 Dec 2022 15:42:01 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~axelheider Date: Sat, 19 Nov 2022 17:09:59 +0100 Subject: [PATCH qemu.git v3 5/8] hw/timer/imx_epit: hard reset initializes CR with 0 Message-ID: <166990932074.29941.8709118178538288040-5@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166990932074.29941.8709118178538288040-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1669909368077100001 From: Axel Heider Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 7af3a8b10e..39f47222d0 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -99,12 +99,14 @@ static void imx_epit_set_freq(IMXEPITState *s) /* * This is called both on hardware (device) reset and software reset. */ -static void imx_epit_reset(DeviceState *dev) +static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset) { - IMXEPITState *s =3D IMX_EPIT(dev); - /* Soft reset doesn't touch some bits; hard reset clears them */ - s->cr &=3D (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); + if (is_hard_reset) { + s->cr =3D 0; + } else { + s->cr &=3D (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); + } s->sr =3D 0; s->lr =3D EPIT_TIMER_MAX; s->cmp =3D 0; @@ -205,7 +207,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, s->cr =3D value & 0x03ffffff; if (s->cr & CR_SWR) { /* handle the reset */ - imx_epit_reset(DEVICE(s)); + imx_epit_reset(s, false); } =20 /* @@ -377,12 +379,18 @@ static void imx_epit_realize(DeviceState *dev, Error = **errp) s->timer_cmp =3D ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); } =20 +static void imx_epit_dev_reset(DeviceState *dev) +{ + IMXEPITState *s =3D IMX_EPIT(dev); + imx_epit_reset(s, true); +} + static void imx_epit_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D imx_epit_realize; - dc->reset =3D imx_epit_reset; + dc->reset =3D imx_epit_dev_reset; dc->vmsd =3D &vmstate_imx_timer_epit; dc->desc =3D "i.MX periodic timer"; } --=20 2.34.5 From nobody Wed May 1 02:32:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669909470298105.34716824961606; Thu, 1 Dec 2022 07:44:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0lhV-0005Jc-6m; Thu, 01 Dec 2022 10:42:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhO-0005GK-V7; Thu, 01 Dec 2022 10:42:07 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhM-0004wk-UW; Thu, 01 Dec 2022 10:42:06 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id AA96E11F9A1; Thu, 1 Dec 2022 15:42:01 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~axelheider Date: Thu, 27 Oct 2022 15:09:58 +0200 Subject: [PATCH qemu.git v3 6/8] hw/timer/imx_epit: factor out register write handlers Message-ID: <166990932074.29941.8709118178538288040-6@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166990932074.29941.8709118178538288040-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1669909470784100001 From: Axel Heider Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 207 ++++++++++++++++++++++++-------------------- 1 file changed, 113 insertions(+), 94 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 39f47222d0..e04427542f 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -191,129 +191,148 @@ static void imx_epit_reload_compare_timer(IMXEPITSt= ate *s) } } =20 -static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) +static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) { - IMXEPITState *s =3D IMX_EPIT(opaque); - uint64_t oldcr; - - DPRINTF("(%s, value =3D 0x%08x)\n", imx_epit_reg_name(offset >> 2), - (uint32_t)value); + uint32_t oldcr =3D s->cr; =20 - switch (offset >> 2) { - case 0: /* CR */ - - oldcr =3D s->cr; - s->cr =3D value & 0x03ffffff; - if (s->cr & CR_SWR) { - /* handle the reset */ - imx_epit_reset(s, false); - } + s->cr =3D value & 0x03ffffff; =20 - /* - * The interrupt state can change due to: - * - reset clears both SR.OCIF and CR.OCIE - * - write to CR.EN or CR.OCIE - */ - imx_epit_update_int(s); + if (s->cr & CR_SWR) { + /* handle the reset */ + imx_epit_reset(s, false); + } =20 - /* - * TODO: could we 'break' here for reset? following operations app= ear - * to duplicate the work imx_epit_reset() already did. - */ + /* + * The interrupt state can change due to: + * - reset clears both SR.OCIF and CR.OCIE + * - write to CR.EN or CR.OCIE + */ + imx_epit_update_int(s); =20 - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); + /* + * TODO: could we 'break' here for reset? following operations appear + * to duplicate the work imx_epit_reset() already did. + */ =20 - /* Update the frequency. Has been done already in case of a reset.= */ - if (!(s->cr & CR_SWR)) { - imx_epit_set_freq(s); - } + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); =20 - if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { - if (s->cr & CR_ENMOD) { - if (s->cr & CR_RLD) { - ptimer_set_limit(s->timer_reload, s->lr, 1); - ptimer_set_limit(s->timer_cmp, s->lr, 1); - } else { - ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); - } - } + /* Update the frequency. Has been done already in case of a reset. */ + if (!(s->cr & CR_SWR)) { + imx_epit_set_freq(s); + } =20 - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_reload, 0); - if (s->cr & CR_OCIEN) { - ptimer_run(s->timer_cmp, 0); + if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { + if (s->cr & CR_ENMOD) { + if (s->cr & CR_RLD) { + ptimer_set_limit(s->timer_reload, s->lr, 1); + ptimer_set_limit(s->timer_cmp, s->lr, 1); } else { - ptimer_stop(s->timer_cmp); - } - } else if (!(s->cr & CR_EN)) { - /* stop both timers */ - ptimer_stop(s->timer_reload); - ptimer_stop(s->timer_cmp); - } else if (s->cr & CR_OCIEN) { - if (!(oldcr & CR_OCIEN)) { - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_cmp, 0); + ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); + ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); } + } + + imx_epit_reload_compare_timer(s); + ptimer_run(s->timer_reload, 0); + if (s->cr & CR_OCIEN) { + ptimer_run(s->timer_cmp, 0); } else { ptimer_stop(s->timer_cmp); } + } else if (!(s->cr & CR_EN)) { + /* stop both timers */ + ptimer_stop(s->timer_reload); + ptimer_stop(s->timer_cmp); + } else if (s->cr & CR_OCIEN) { + if (!(oldcr & CR_OCIEN)) { + imx_epit_reload_compare_timer(s); + ptimer_run(s->timer_cmp, 0); + } + } else { + ptimer_stop(s->timer_cmp); + } =20 - ptimer_transaction_commit(s->timer_cmp); - ptimer_transaction_commit(s->timer_reload); + ptimer_transaction_commit(s->timer_cmp); + ptimer_transaction_commit(s->timer_reload); +} + +static void imx_epit_write_sr(IMXEPITState *s, uint32_t value) +{ + /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */ + if (value & SR_OCIF) { + s->sr =3D 0; /* SR.OCIF is the only bit in this register anyway */ + imx_epit_update_int(s); + } +} + +static void imx_epit_write_lr(IMXEPITState *s, uint32_t value) +{ + s->lr =3D value; + + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); + if (s->cr & CR_RLD) { + /* Also set the limit if the LRD bit is set */ + /* If IOVW bit is set then set the timer value */ + ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); + ptimer_set_limit(s->timer_cmp, s->lr, 0); + } else if (s->cr & CR_IOVW) { + /* If IOVW bit is set then set the timer value */ + ptimer_set_count(s->timer_reload, s->lr); + } + /* + * Commit the change to s->timer_reload, so it can propagate. Otherwise + * the timer interrupt may not fire properly. The commit must happen + * before calling imx_epit_reload_compare_timer(), which reads + * s->timer_reload internally again. + */ + ptimer_transaction_commit(s->timer_reload); + imx_epit_reload_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); +} + +static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value) +{ + s->cmp =3D value; + + ptimer_transaction_begin(s->timer_cmp); + imx_epit_reload_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); +} + +static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + IMXEPITState *s =3D IMX_EPIT(opaque); + + DPRINTF("(%s, value =3D 0x%08x)\n", imx_epit_reg_name(offset >> 2), + (uint32_t)value); + + switch (offset >> 2) { + case 0: /* CR */ + imx_epit_write_cr(s, (uint32_t)value); break; =20 - case 1: /* SR - ACK*/ - /* writing 1 to SR.OCIF clears this bit and turns the interrupt of= f */ - if (value & SR_OCIF) { - s->sr =3D 0; /* SR.OCIF is the only bit in this register anywa= y */ - imx_epit_update_int(s); - } + case 1: /* SR */ + imx_epit_write_sr(s, (uint32_t)value); break; =20 - case 2: /* LR - set ticks */ - s->lr =3D value; - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); - if (s->cr & CR_RLD) { - /* Also set the limit if the LRD bit is set */ - /* If IOVW bit is set then set the timer value */ - ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); - ptimer_set_limit(s->timer_cmp, s->lr, 0); - } else if (s->cr & CR_IOVW) { - /* If IOVW bit is set then set the timer value */ - ptimer_set_count(s->timer_reload, s->lr); - } - /* - * Commit the change to s->timer_reload, so it can propagate. Othe= rwise - * the timer interrupt may not fire properly. The commit must happ= en - * before calling imx_epit_reload_compare_timer(), which reads - * s->timer_reload internally again. - */ - ptimer_transaction_commit(s->timer_reload); - imx_epit_reload_compare_timer(s); - ptimer_transaction_commit(s->timer_cmp); + case 2: /* LR */ + imx_epit_write_lr(s, (uint32_t)value); break; =20 case 3: /* CMP */ - s->cmp =3D value; - - ptimer_transaction_begin(s->timer_cmp); - imx_epit_reload_compare_timer(s); - ptimer_transaction_commit(s->timer_cmp); - + imx_epit_write_cmp(s, (uint32_t)value); break; =20 default: qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); - break; } } + static void imx_epit_cmp(void *opaque) { IMXEPITState *s =3D IMX_EPIT(opaque); --=20 2.34.5 From nobody Wed May 1 02:32:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166990953899514.34317133149841; Thu, 1 Dec 2022 07:45:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0lhZ-0005Kx-ME; Thu, 01 Dec 2022 10:42:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhP-0005Gk-Ha; Thu, 01 Dec 2022 10:42:07 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhM-0004wn-Vx; Thu, 01 Dec 2022 10:42:07 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id C682A11F9A2; Thu, 1 Dec 2022 15:42:01 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~axelheider Date: Tue, 25 Oct 2022 12:33:42 +0200 Subject: [PATCH qemu.git v3 7/8] hw/timer/imx_epit: remove explicit fields cnt and freq Message-ID: <166990932074.29941.8709118178538288040-7@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166990932074.29941.8709118178538288040-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1669909539226100001 From: Axel Heider The CNT register is a read-only register. There is no need to store it's value, it can be calculated on demand. The calculated frequency is needed temporarily only. Note that this is a migration compatibility break for all boards types that use the EPIT peripheral. Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 73 ++++++++++++++----------------------- include/hw/timer/imx_epit.h | 2 - 2 files changed, 28 insertions(+), 47 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index e04427542f..cf13496165 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -73,27 +73,14 @@ static void imx_epit_update_int(IMXEPITState *s) } } =20 -/* - * Must be called from within a ptimer_transaction_begin/commit block - * for both s->timer_cmp and s->timer_reload. - */ -static void imx_epit_set_freq(IMXEPITState *s) +static uint32_t imx_epit_get_freq(IMXEPITState *s) { - uint32_t clksrc; - uint32_t prescaler; - - clksrc =3D extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); - prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS= ); - - s->freq =3D imx_ccm_get_clock_frequency(s->ccm, - imx_epit_clocks[clksrc]) / prescaler; - - DPRINTF("Setting ptimer frequency to %u\n", s->freq); - - if (s->freq) { - ptimer_set_freq(s->timer_reload, s->freq); - ptimer_set_freq(s->timer_cmp, s->freq); - } + uint32_t clksrc =3D extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); + uint32_t prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRES= CALE_BITS); + uint32_t f_in =3D imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[= clksrc]); + uint32_t freq =3D f_in / prescaler; + DPRINTF("ptimer frequency is %u\n", freq); + return freq; } =20 /* @@ -110,32 +97,23 @@ static void imx_epit_reset(IMXEPITState *s, bool is_ha= rd_reset) s->sr =3D 0; s->lr =3D EPIT_TIMER_MAX; s->cmp =3D 0; - s->cnt =3D 0; ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); - /* stop both timers */ + + /* + * The reset switches off the input clock, so even if the CR.EN is sti= ll + * set, the timers are no longer running. + */ + assert(imx_epit_get_freq(s) =3D=3D 0); ptimer_stop(s->timer_cmp); ptimer_stop(s->timer_reload); - /* compute new frequency */ - imx_epit_set_freq(s); /* init both timers to EPIT_TIMER_MAX */ ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - if (s->freq && (s->cr & CR_EN)) { - /* if the timer is still enabled, restart it */ - ptimer_run(s->timer_reload, 0); - } ptimer_transaction_commit(s->timer_cmp); ptimer_transaction_commit(s->timer_reload); } =20 -static uint32_t imx_epit_update_count(IMXEPITState *s) -{ - s->cnt =3D ptimer_get_count(s->timer_reload); - - return s->cnt; -} - static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) { IMXEPITState *s =3D IMX_EPIT(opaque); @@ -159,8 +137,7 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offs= et, unsigned size) break; =20 case 4: /* CNT */ - imx_epit_update_count(s); - reg_value =3D s->cnt; + reg_value =3D ptimer_get_count(s->timer_reload); break; =20 default: @@ -179,7 +156,7 @@ static void imx_epit_reload_compare_timer(IMXEPITState = *s) { if ((s->cr & (CR_EN | CR_OCIEN)) =3D=3D (CR_EN | CR_OCIEN)) { /* if the compare feature is on and timers are running */ - uint32_t tmp =3D imx_epit_update_count(s); + uint32_t tmp =3D ptimer_get_count(s->timer_reload); uint64_t next; if (tmp > s->cmp) { /* It'll fire in this round of the timer */ @@ -193,6 +170,7 @@ static void imx_epit_reload_compare_timer(IMXEPITState = *s) =20 static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) { + uint32_t freq =3D 0; uint32_t oldcr =3D s->cr; =20 s->cr =3D value & 0x03ffffff; @@ -217,12 +195,19 @@ static void imx_epit_write_cr(IMXEPITState *s, uint32= _t value) ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); =20 - /* Update the frequency. Has been done already in case of a reset. */ + /* + * Update the frequency. In case of a reset the input clock was + * switched off, so this can be skipped. + */ if (!(s->cr & CR_SWR)) { - imx_epit_set_freq(s); + freq =3D imx_epit_get_freq(s); + if (freq) { + ptimer_set_freq(s->timer_reload, freq); + ptimer_set_freq(s->timer_cmp, freq); + } } =20 - if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { + if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { if (s->cr & CR_ENMOD) { if (s->cr & CR_RLD) { ptimer_set_limit(s->timer_reload, s->lr, 1); @@ -356,15 +341,13 @@ static const MemoryRegionOps imx_epit_ops =3D { =20 static const VMStateDescription vmstate_imx_timer_epit =3D { .name =3D TYPE_IMX_EPIT, - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { VMSTATE_UINT32(cr, IMXEPITState), VMSTATE_UINT32(sr, IMXEPITState), VMSTATE_UINT32(lr, IMXEPITState), VMSTATE_UINT32(cmp, IMXEPITState), - VMSTATE_UINT32(cnt, IMXEPITState), - VMSTATE_UINT32(freq, IMXEPITState), VMSTATE_PTIMER(timer_reload, IMXEPITState), VMSTATE_PTIMER(timer_cmp, IMXEPITState), VMSTATE_END_OF_LIST() diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index 783eaf0c3a..79aff0cec2 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -74,9 +74,7 @@ struct IMXEPITState { uint32_t sr; uint32_t lr; uint32_t cmp; - uint32_t cnt; =20 - uint32_t freq; qemu_irq irq; }; =20 --=20 2.34.5 From nobody Wed May 1 02:32:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669909434679451.4298690064933; Thu, 1 Dec 2022 07:43:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0lhR-0005HF-HL; Thu, 01 Dec 2022 10:42:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhP-0005GL-1T; Thu, 01 Dec 2022 10:42:07 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0lhM-0004wo-Ki; Thu, 01 Dec 2022 10:42:06 -0500 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id F139C11F9A3; Thu, 1 Dec 2022 15:42:01 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~axelheider Date: Sun, 20 Nov 2022 20:05:25 +0100 Subject: [PATCH qemu.git v3 8/8] hw/timer/imx_epit: fix compare timer handling Message-ID: <166990932074.29941.8709118178538288040-8@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166990932074.29941.8709118178538288040-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1669909436494100003 From: Axel Heider - fix #1263 for CR writes - rework compare time handling - The compare timer has to run even if CR.OCIEN is not set, as SR.OCIF must be updated. - The compare timer fires exactly once when the compare value is less than the current value, but the reload values is less than the compare value. - The compare timer will never fire if the reload value is less than the compare value. Disable it in this case. Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 184 ++++++++++++++++++++++++++------------------ 1 file changed, 110 insertions(+), 74 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index cf13496165..663907f9cf 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -6,6 +6,7 @@ * Originally written by Hans Jiang * Updated by Peter Chubb * Updated by Jean-Christophe Dubois + * Updated by Axel Heider * * This code is licensed under GPL version 2 or later. See * the COPYING file in the top-level directory. @@ -151,95 +152,130 @@ static uint64_t imx_epit_read(void *opaque, hwaddr o= ffset, unsigned size) return reg_value; } =20 -/* Must be called from ptimer_transaction_begin/commit block for s->timer_= cmp */ -static void imx_epit_reload_compare_timer(IMXEPITState *s) +/* + * Must be called from a ptimer_transaction_begin/commit block for + * s->timer_cmp, but outside of a transaction block of s->timer_reload, + * so the proper counter value is read. + */ +static void imx_epit_update_compare_timer(IMXEPITState *s) { - if ((s->cr & (CR_EN | CR_OCIEN)) =3D=3D (CR_EN | CR_OCIEN)) { - /* if the compare feature is on and timers are running */ - uint32_t tmp =3D ptimer_get_count(s->timer_reload); - uint64_t next; - if (tmp > s->cmp) { - /* It'll fire in this round of the timer */ - next =3D tmp - s->cmp; - } else { /* catch it next time around */ - next =3D tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s= ->lr); + uint64_t counter =3D 0; + bool is_oneshot =3D false; + /* The compare timer only has to run if the timer peripheral is active + * and there is an input clock, Otherwise it can be switched off. + */ + bool is_active =3D (s->cr & CR_EN) && imx_epit_get_freq(s); + if (is_active) { + /* + * Calculate next timeout for compare timer. Reading the reload + * counter returns proper results only if pending transactions + * on it are committed here. Otherwise stale values are be read. + */ + counter =3D ptimer_get_count(s->timer_reload); + uint64_t limit =3D ptimer_get_limit(s->timer_cmp); + /* + * The compare timer is a periodic timer if the limit is at least + * the compare value. Otherwise it may fire at most once in the + * current round. + */ + bool is_oneshot =3D (limit >=3D s->cmp); + if (counter >=3D s->cmp) { + /* The compare timer fires in the current round. */ + counter -=3D s->cmp; + } else if (!is_oneshot) { + /* + * The compare timer fires after a reload, as it below the + * compare value already in this round. Note that the counter + * value calculated below can be above the 32-bit limit, which + * is legal here because the compare timer is an internal + * helper ptimer only. + */ + counter +=3D limit - s->cmp; + } else { + /* + * The compare timer won't fire in this round, and the limit is + * set to a value below the compare value. This practically me= ans + * it will never fire, so it can be switched off. + */ + is_active =3D false; } - ptimer_set_count(s->timer_cmp, next); } + + /* + * Set the compare timer and let it run, or stop it. This is agnostic + * of CR.OCIEN bit, as this bit affects interrupt generation only. The + * compare timer needs to run even if no interrupts are to be generate= d, + * because the SR.OCIF bit must be updated also. + * Note that the timer might already be stopped or be running with + * counter values. However, finding out when an update is needed and + * when not is not trivial. It's much easier applying the setting agai= n, + * as this does not harm either and the overhead is negligible. + */ + if (is_active) { + ptimer_set_count(s->timer_cmp, counter); + ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0); + } else { + ptimer_stop(s->timer_cmp); + } + } =20 static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) { - uint32_t freq =3D 0; uint32_t oldcr =3D s->cr; =20 s->cr =3D value & 0x03ffffff; =20 if (s->cr & CR_SWR) { - /* handle the reset */ + /* + * Reset clears CR.SWR again. It does not touch CR.EN, but the tim= ers + * are still stopped because the input clock is disabled. + */ imx_epit_reset(s, false); - } - - /* - * The interrupt state can change due to: - * - reset clears both SR.OCIF and CR.OCIE - * - write to CR.EN or CR.OCIE - */ - imx_epit_update_int(s); - - /* - * TODO: could we 'break' here for reset? following operations appear - * to duplicate the work imx_epit_reset() already did. - */ - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); - - /* - * Update the frequency. In case of a reset the input clock was - * switched off, so this can be skipped. - */ - if (!(s->cr & CR_SWR)) { - freq =3D imx_epit_get_freq(s); + } else { + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); + uint32_t freq =3D imx_epit_get_freq(s); if (freq) { ptimer_set_freq(s->timer_reload, freq); ptimer_set_freq(s->timer_cmp, freq); } - } - - if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { - if (s->cr & CR_ENMOD) { - if (s->cr & CR_RLD) { - ptimer_set_limit(s->timer_reload, s->lr, 1); - ptimer_set_limit(s->timer_cmp, s->lr, 1); - } else { - ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); + uint32_t toggled_cr_bits =3D oldcr ^ s->cr; + /* re-initialize the limits if CR.RLD has changed */ + bool set_limit =3D toggled_cr_bits & CR_RLD; + /* set the counter if the timer got just enabled and CR.ENMOD is s= et */ + bool is_switched_on =3D (toggled_cr_bits & s->cr) & CR_EN; + bool set_counter =3D is_switched_on && (s->cr & CR_ENMOD); + if (set_limit || set_counter) { + uint64_t limit =3D (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX; + ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0); + if (set_limit) { + ptimer_set_limit(s->timer_cmp, limit, 0); } } - - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_reload, 0); - if (s->cr & CR_OCIEN) { - ptimer_run(s->timer_cmp, 0); + /* + * If there is an input clock and the peripheral is enabled, then + * ensure the wall clock timer is ticking. Otherwise stop the time= rs. + * The compare timer will be updated later. + */ + if (freq && (s->cr & CR_EN)) { + ptimer_run(s->timer_reload, 0); } else { - ptimer_stop(s->timer_cmp); - } - } else if (!(s->cr & CR_EN)) { - /* stop both timers */ - ptimer_stop(s->timer_reload); - ptimer_stop(s->timer_cmp); - } else if (s->cr & CR_OCIEN) { - if (!(oldcr & CR_OCIEN)) { - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_cmp, 0); + ptimer_stop(s->timer_reload); } - } else { - ptimer_stop(s->timer_cmp); + /* Commit changes to reload timer, so they can propagate. */ + ptimer_transaction_commit(s->timer_reload); + /* Update compare timer based on the committed reload timer value.= */ + imx_epit_update_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); } =20 - ptimer_transaction_commit(s->timer_cmp); - ptimer_transaction_commit(s->timer_reload); + /* + * The interrupt state can change due to: + * - reset clears both SR.OCIF and CR.OCIE + * - write to CR.EN or CR.OCIE + */ + imx_epit_update_int(s); } =20 static void imx_epit_write_sr(IMXEPITState *s, uint32_t value) @@ -266,14 +302,10 @@ static void imx_epit_write_lr(IMXEPITState *s, uint32= _t value) /* If IOVW bit is set then set the timer value */ ptimer_set_count(s->timer_reload, s->lr); } - /* - * Commit the change to s->timer_reload, so it can propagate. Otherwise - * the timer interrupt may not fire properly. The commit must happen - * before calling imx_epit_reload_compare_timer(), which reads - * s->timer_reload internally again. - */ + /* Commit the changes to s->timer_reload, so they can propagate. */ ptimer_transaction_commit(s->timer_reload); - imx_epit_reload_compare_timer(s); + /* Update the compare timer based on the committed reload timer value.= */ + imx_epit_update_compare_timer(s); ptimer_transaction_commit(s->timer_cmp); } =20 @@ -281,8 +313,9 @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_= t value) { s->cmp =3D value; =20 + /* Update the compare timer based on the committed reload timer value.= */ ptimer_transaction_begin(s->timer_cmp); - imx_epit_reload_compare_timer(s); + imx_epit_update_compare_timer(s); ptimer_transaction_commit(s->timer_cmp); } =20 @@ -322,6 +355,9 @@ static void imx_epit_cmp(void *opaque) { IMXEPITState *s =3D IMX_EPIT(opaque); =20 + /* The cmp ptimer can't be running when the peripheral is disabled */ + assert(s->cr & CR_EN); + DPRINTF("sr was %d\n", s->sr); /* Set interrupt status bit SR.OCIF and update the interrupt state */ s->sr |=3D SR_OCIF; --=20 2.34.5