From nobody Tue Feb 10 06:43:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=ispras.ru Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654594153355185.53634695833694; Tue, 7 Jun 2022 02:29:13 -0700 (PDT) Received: from localhost ([::1]:45982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyVWR-0006Ju-JD for importer@patchew.org; Tue, 07 Jun 2022 05:29:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyV3x-00073W-I1 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 04:59:46 -0400 Received: from mail.ispras.ru ([83.149.199.84]:39530) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyV3v-0005Mi-Dt for qemu-devel@nongnu.org; Tue, 07 Jun 2022 04:59:45 -0400 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id C78324076B37; Tue, 7 Jun 2022 08:59:19 +0000 (UTC) Subject: [PATCH 1/3] target/mips: introduce generic Cavium Octeon CPU model From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, f4bug@amsat.org, jiaxun.yang@flygoat.com, aurelien@aurel32.net, aleksandar.rikalo@syrmia.com Date: Tue, 07 Jun 2022 11:59:19 +0300 Message-ID: <165459235959.143371.13189201469172149052.stgit@pasha-ThinkPad-X280> In-Reply-To: <165459235408.143371.17715826203190085295.stgit@pasha-ThinkPad-X280> References: <165459235408.143371.17715826203190085295.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1654594156051100001 This patch adds generic Octeon vCPU for providing Octeon-specific instructions. Signed-off-by: Pavel Dovgalyuk --- target/mips/cpu-defs.c.inc | 30 ++++++++++++++++++++++++++++++ target/mips/mips-defs.h | 1 + 2 files changed, 31 insertions(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 582f940070..a60e48433c 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -921,6 +921,36 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, .mmu_type =3D MMU_TYPE_R4000, }, + { + /* + * A generic CPU providing MIPS64 Cavium Octeon features. + * PRid is taken from Octeon 68xx CPUs + * FIXME: Eventually this should be replaced by a real CPU model. + */ + .name =3D "Octeon", + .CP0_PRid =3D 0x000D9100, + .CP0_Config0 =3D MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_= AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 =3D MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA)= | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA)= | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 =3D MIPS_CONFIG2, + .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSP= P) , + .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | + (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef)= | + (3U << CP0C4_MMUSizeExt), + .CP0_LLAddr_rw_bitmask =3D 0, + .CP0_LLAddr_shift =3D 4, + .CP0_PageGrain =3D (1 << CP0PG_ELPA), + .SYNCI_Step =3D 32, + .CCRes =3D 2, + .CP0_Status_rw_bitmask =3D 0x12F8FFFF, + .SEGBITS =3D 42, + .PABITS =3D 49, + .insn_flags =3D CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP, + .mmu_type =3D MMU_TYPE_R4000, + }, =20 #endif }; diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 0a12d982a7..a6cebe0265 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -42,6 +42,7 @@ #define INSN_LOONGSON2E 0x0000040000000000ULL #define INSN_LOONGSON2F 0x0000080000000000ULL #define INSN_LOONGSON3A 0x0000100000000000ULL +#define INSN_OCTEON 0x0000200000000000ULL /* * bits 52-63: vendor-specific ASEs */