From nobody Mon Feb 9 23:18:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652345413266483.1008797176644; Thu, 12 May 2022 01:50:13 -0700 (PDT) Received: from localhost ([::1]:56192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1np4WR-0004e7-GJ for importer@patchew.org; Thu, 12 May 2022 04:50:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1np49V-0004SG-TP; Thu, 12 May 2022 04:26:29 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:45218) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1np49T-0005Oz-A1; Thu, 12 May 2022 04:26:29 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 4387811EFCE; Thu, 12 May 2022 08:26:21 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Sun, 06 Mar 2022 23:10:25 -0800 Subject: [PATCH qemu v17 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions Message-ID: <165234397852.32492.1203149738524050090-6@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165234397852.32492.1203149738524050090-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , WeiWei Li , eop Chen Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1652345415119100001 From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. A vector segment load / store instruction may contain fractional lmul with nf * lmul > 1. The rest of the elements in the last register should be treated as tail elements. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 11 ++++ target/riscv/translate.c | 2 + target/riscv/vector_helper.c | 86 +++++++++++++++++++++---- 3 files changed, 86 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index efdf5d6d81..1f3eeff9eb 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -711,6 +711,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t eew) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } =20 @@ -748,6 +749,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t eew) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } =20 @@ -774,6 +776,8 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a= , uint8_t eew) /* EMUL =3D 1, NFIELDS =3D 1 */ data =3D FIELD_DP32(data, VDATA, LMUL, 0); data =3D FIELD_DP32(data, VDATA, NF, 1); + /* Mask destination register are always tail-agnostic */ + data =3D FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } =20 @@ -791,6 +795,8 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a= , uint8_t eew) /* EMUL =3D 1, NFIELDS =3D 1 */ data =3D FIELD_DP32(data, VDATA, LMUL, 0); data =3D FIELD_DP32(data, VDATA, NF, 1); + /* Mask destination register are always tail-agnostic */ + data =3D FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s); return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } =20 @@ -862,6 +868,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t eew) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 @@ -891,6 +898,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t eew) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); fn =3D fns[eew]; if (fn =3D=3D NULL) { return false; @@ -991,6 +999,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t eew) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 @@ -1043,6 +1052,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a= , uint8_t eew) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } =20 @@ -1108,6 +1118,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, u= int8_t eew) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); return ldff_trans(a->rd, a->rs1, data, fn, s); } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 832353be54..384ffcc0fa 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -95,6 +95,7 @@ typedef struct DisasContext { int8_t lmul; uint8_t sew; uint8_t vta; + bool cfg_vta_all_1s; target_ulong vstart; bool vl_eq_vlmax; uint8_t ntemp; @@ -1093,6 +1094,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); ctx->vta =3D FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_al= l_1s; + ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart =3D env->vstart; ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->misa_mxl_max =3D env->misa_mxl_max; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2248f0cbee..4e08fc3991 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -264,11 +264,14 @@ vext_ldst_stride(void *vd, void *v0, target_ulong bas= e, target_ulong stride, CPURISCVState *env, uint32_t desc, uint32_t vm, vext_ldst_elem_fn *ldst_elem, - uint32_t log2_esz, uintptr_t ra) + uint32_t log2_esz, uintptr_t ra, uint32_t is_load) { uint32_t i, k; uint32_t nf =3D vext_nf(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); + uint32_t esz =3D 1 << log2_esz; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc) & is_load; =20 for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { if (!vm && !vext_elem_mask(v0, i)) { @@ -283,6 +286,18 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, } } env->vstart =3D 0; + /* set tail elements to 1s */ + for (k =3D 0; k < nf; ++k) { + vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz, + (k * max_elems + max_elems) * esz); + } + if (nf * max_elems % total_elems !=3D 0) { + uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t registers_used =3D + ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; + vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, + registers_used * vlenb); + } } =20 #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \ @@ -292,7 +307,7 @@ void HELPER(NAME)(void *vd, void * v0, target_ulong bas= e, \ { \ uint32_t vm =3D vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ + ctzl(sizeof(ETYPE)), GETPC(), 1); \ } =20 GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b) @@ -307,7 +322,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base= , \ { \ uint32_t vm =3D vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ + ctzl(sizeof(ETYPE)), GETPC(), 0); \ } =20 GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b) @@ -323,11 +338,14 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t des= c, vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl, - uintptr_t ra) + uintptr_t ra, uint32_t is_load) { uint32_t i, k; uint32_t nf =3D vext_nf(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); + uint32_t esz =3D 1 << log2_esz; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc) & is_load; =20 /* load bytes from guest memory */ for (i =3D env->vstart; i < evl; i++, env->vstart++) { @@ -339,6 +357,18 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVStat= e *env, uint32_t desc, } } env->vstart =3D 0; + /* set tail elements to 1s */ + for (k =3D 0; k < nf; ++k) { + vext_set_elems_1s(vd, vta, (k * max_elems + evl) * esz, + (k * max_elems + max_elems) * esz); + } + if (nf * max_elems % total_elems !=3D 0) { + uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t registers_used =3D + ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; + vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, + registers_used * vlenb); + } } =20 /* @@ -352,14 +382,14 @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_u= long base, \ { \ uint32_t stride =3D vext_nf(desc) << ctzl(sizeof(ETYPE)); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ + ctzl(sizeof(ETYPE)), GETPC(), 1); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, LOAD_FN, \ - ctzl(sizeof(ETYPE)), env->vl, GETPC()); \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), 1); \ } =20 GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) @@ -373,14 +403,14 @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_u= long base, \ { \ uint32_t stride =3D vext_nf(desc) << ctzl(sizeof(ETYPE)); = \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - ctzl(sizeof(ETYPE)), GETPC()); \ + ctzl(sizeof(ETYPE)), GETPC(), 0); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, STORE_FN, \ - ctzl(sizeof(ETYPE)), env->vl, GETPC()); \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), 0); \ } =20 GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) @@ -397,7 +427,7 @@ void HELPER(vlm_v)(void *vd, void *v0, target_ulong bas= e, /* evl =3D ceil(vl/8) */ uint8_t evl =3D (env->vl + 7) >> 3; vext_ldst_us(vd, base, env, desc, lde_b, - 0, evl, GETPC()); + 0, evl, GETPC(), 1); } =20 void HELPER(vsm_v)(void *vd, void *v0, target_ulong base, @@ -406,7 +436,7 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong bas= e, /* evl =3D ceil(vl/8) */ uint8_t evl =3D (env->vl + 7) >> 3; vext_ldst_us(vd, base, env, desc, ste_b, - 0, evl, GETPC()); + 0, evl, GETPC(), 0); } =20 /* @@ -432,12 +462,15 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, void *vs2, CPURISCVState *env, uint32_t desc, vext_get_index_addr get_index_addr, vext_ldst_elem_fn *ldst_elem, - uint32_t log2_esz, uintptr_t ra) + uint32_t log2_esz, uintptr_t ra, uint32_t is_load) { uint32_t i, k; uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); + uint32_t esz =3D 1 << log2_esz; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc) & is_load; =20 /* load bytes from guest memory */ for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { @@ -453,6 +486,18 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, } } env->vstart =3D 0; + /* set tail elements to 1s */ + for (k =3D 0; k < nf; ++k) { + vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz, + (k * max_elems + max_elems) * esz); + } + if (nf * max_elems % total_elems !=3D 0) { + uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t registers_used =3D + ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; + vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, + registers_used * vlenb); + } } =20 #define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) = \ @@ -460,7 +505,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base= , \ void *vs2, CPURISCVState *env, uint32_t desc) = \ { = \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, = \ - LOAD_FN, ctzl(sizeof(ETYPE)), GETPC()); = \ + LOAD_FN, ctzl(sizeof(ETYPE)), GETPC(), 1); = \ } =20 GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b) @@ -486,7 +531,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base= , \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ STORE_FN, ctzl(sizeof(ETYPE)), \ - GETPC()); \ + GETPC(), 0); \ } =20 GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b) @@ -520,6 +565,9 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t nf =3D vext_nf(desc); uint32_t vm =3D vext_vm(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); + uint32_t esz =3D 1 << log2_esz; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); target_ulong addr, offset, remain; =20 /* probe every access*/ @@ -575,6 +623,18 @@ ProbeSuccess: } } env->vstart =3D 0; + /* set tail elements to 1s */ + for (k =3D 0; k < nf; ++k) { + vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz, + (k * max_elems + max_elems) * esz); + } + if (nf * max_elems % total_elems !=3D 0) { + uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t registers_used =3D + ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; + vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, + registers_used * vlenb); + } } =20 #define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \ --=20 2.34.2