From nobody Tue Feb 10 01:35:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651117633990993.2074304917139; Wed, 27 Apr 2022 20:47:13 -0700 (PDT) Received: from localhost ([::1]:55938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1njv7Y-000885-Tb for importer@patchew.org; Wed, 27 Apr 2022 23:47:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njuyC-00023E-0T; Wed, 27 Apr 2022 23:37:32 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:42346) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njuyA-0002nP-8Y; Wed, 27 Apr 2022 23:37:31 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 71A2A11F032; Thu, 28 Apr 2022 03:37:04 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Mon, 07 Mar 2022 01:53:23 -0800 Subject: [PATCH qemu v11 09/15] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions Message-ID: <165111702275.848.16529145411603891061-9@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165111702275.848.16529145411603891061-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1651117634729100001 From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 44 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 20 +++++++++++ 2 files changed, 64 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 430847b0f9..46ee673040 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2123,11 +2123,22 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_= v_v *a) /* vmv.v.v has rs2 =3D 0 and vm =3D 1 */ vext_check_sss(s, a->rd, a->rs1, 0, 1)) { if (s->vl_eq_vlmax) { + if (s->vta && s->lmul < 0) { + /* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ + uint32_t vlenb =3D s->cfg_ptr->vlen >> 3; + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rd), -1, + vlenb, vlenb); + } tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), MAXSZ(s), MAXSZ(s)); } else { uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_gvec_2_ptr * const fns[4] =3D { gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h, gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, @@ -2163,6 +2174,16 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v= _x *a) s1 =3D get_gpr(s, a->rs1, EXT_SIGN); =20 if (s->vl_eq_vlmax) { + if (s->vta && s->lmul < 0) { + /* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ + uint32_t vlenb =3D s->cfg_ptr->vlen >> 3; + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rd), -1, + vlenb, vlenb); + } tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), s1); } else { @@ -2170,6 +2191,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) TCGv_i64 s1_i64 =3D tcg_temp_new_i64(); TCGv_ptr dest =3D tcg_temp_new_ptr(); uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_vmv_vx * const fns[4] =3D { gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, @@ -2200,6 +2222,16 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v= _i *a) vext_check_ss(s, a->rd, 0, 1)) { int64_t simm =3D sextract64(a->rs1, 0, 5); if (s->vl_eq_vlmax) { + if (s->vta && s->lmul < 0) { + /* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ + uint32_t vlenb =3D s->cfg_ptr->vlen >> 3; + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rd), -1, + vlenb, vlenb); + } tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), simm); mark_vs_dirty(s); @@ -2208,6 +2240,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) TCGv_i64 s1; TCGv_ptr dest; uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_vmv_vx * const fns[4] =3D { gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, @@ -2780,6 +2813,16 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv= _v_f *a) TCGv_i64 t1; =20 if (s->vl_eq_vlmax) { + if (s->vta && s->lmul < 0) { + /* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ + uint32_t vlenb =3D s->cfg_ptr->vlen >> 3; + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rd), -1, + vlenb, vlenb); + } t1 =3D tcg_temp_new_i64(); /* NaN-box f[rs1] */ do_nanbox(s, t1, cpu_fpr[a->rs1]); @@ -2791,6 +2834,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) TCGv_ptr dest; TCGv_i32 desc; uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_vmv_vx * const fns[3] =3D { gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 6356b6b0ef..f7e36b0564 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1946,6 +1946,9 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState = *env, \ uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -1953,6 +1956,8 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState = *env, \ *((ETYPE *)vd + H(i)) =3D s1; \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1) @@ -1965,12 +1970,17 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVSt= ate *env, \ uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ *((ETYPE *)vd + H(i)) =3D (ETYPE)s1; \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1) @@ -1983,6 +1993,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -1990,6 +2003,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ *((ETYPE *)vd + H(i)) =3D *(vt + H(i)); \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1) @@ -2002,6 +2017,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -2011,6 +2029,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ *((ETYPE *)vd + H(i)) =3D d; \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1) --=20 2.34.2