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Mon, 25 Apr 2022 10:18:46 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 9942C11EF94; Mon, 25 Apr 2022 14:18:40 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 02:08:01 -0700 Subject: [PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floating-point instructions Message-ID: <165089631935.4839.7564289944057093570-7@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650897314652100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++++++++ target/riscv/vector_helper.c | 36 +++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index be08ec8a2e..e404d24bcf 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2415,6 +2415,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2498,6 +2499,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2537,6 +2539,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2577,6 +2580,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2614,6 +2618,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2654,6 +2659,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2738,6 +2744,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, @@ -2852,6 +2859,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) TCGv_i32 desc; uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_vmv_vx * const fns[3] =3D { gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, @@ -2953,6 +2961,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -3005,6 +3014,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -3073,6 +3083,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -3127,6 +3138,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e266a8673c..0af65e5423 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3051,10 +3051,16 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t total_elems =3D \ vext_get_total_elems(desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, i, \ + i * ESZ, \ + (i + 1) * \ + ESZ); \ continue; \ } \ do_##NAME(vd, vs1, vs2, i, env); \ @@ -3091,10 +3097,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ uint32_t total_elems =3D \ vext_get_total_elems(desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, i, \ + i * ESZ, \ + (i + 1) * \ + ESZ); \ continue; \ } \ do_##NAME(vd, s1, vs2, i, env); \ @@ -3667,6 +3679,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t total_elems =3D \ vext_get_total_elems(desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ if (vl =3D=3D 0) { \ @@ -3674,6 +3687,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ } \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, \ + i, \ + i * ESZ, \ + (i + 1) \ + * ESZ); \ continue; \ } \ do_##NAME(vd, vs2, i, env); \ @@ -4188,12 +4207,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ @@ -4221,11 +4245,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = void *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ @@ -4347,10 +4376,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t total_elems =3D \ vext_get_total_elems(desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, \ + i, \ + i * ESZ, \ + (i + 1) * \ + ESZ); \ continue; \ } \ do_##NAME(vd, vs2, i); \ --=20 2.34.2