From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650896519328902.4095320383616; Mon, 25 Apr 2022 07:21:59 -0700 (PDT) Received: from localhost ([::1]:46356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nizbC-0003Zb-Bb for importer@patchew.org; Mon, 25 Apr 2022 10:21:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY3-0007HK-Nc; Mon, 25 Apr 2022 10:18:45 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41748) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY1-0003PO-VO; Mon, 25 Apr 2022 10:18:43 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id C191011EEE2; Mon, 25 Apr 2022 14:18:39 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 00:26:23 -0700 Subject: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions Message-ID: <165089631935.4839.7564289944057093570-1@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650896521542100003 From: Yueh-Ting (eop) Chen This is the first commit regarding the mask agnostic behavior. Added option 'rvv_ma_all_1s' to enable the behavior, the option is default to false. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/internals.h | 5 +++-- target/riscv/translate.c | 2 ++ target/riscv/vector_helper.c | 8 ++++++++ 7 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd4cf4b41e..2bf862a5e4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -811,6 +811,7 @@ static Property riscv_cpu_properties[] =3D { =20 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), + DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c4a79b5a0..c76ded515b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -370,6 +370,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool rvv_ta_all_1s; + bool rvv_ma_all_1s; =20 /* Vendor-specific custom extensions */ bool ext_XVentanaCondOps; @@ -518,6 +519,7 @@ FIELD(TB_FLAGS, XL, 20, 2) FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) FIELD(TB_FLAGS, VTA, 24, 1) +FIELD(TB_FLAGS, VMA, 25, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2941c88c31..be94d82ff8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -67,6 +67,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 8d87501e03..4610107fb4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1251,6 +1251,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, @@ -1567,6 +1568,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), @@ -1649,6 +1651,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 512c6c30cf..00b72fd767 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -25,8 +25,9 @@ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) FIELD(VDATA, VTA, 4, 1) -FIELD(VDATA, NF, 5, 4) -FIELD(VDATA, WD, 5, 1) +FIELD(VDATA, VMA, 5, 1) +FIELD(VDATA, NF, 6, 4) +FIELD(VDATA, WD, 6, 1) =20 /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7775dade26..37893aa348 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -95,6 +95,7 @@ typedef struct DisasContext { int8_t lmul; uint8_t sew; uint8_t vta; + uint8_t vma; target_ulong vstart; bool vl_eq_vlmax; uint8_t ntemp; @@ -1085,6 +1086,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); ctx->vta =3D FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_al= l_1s; + ctx->vma =3D FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_al= l_1s; ctx->vstart =3D env->vstart; ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->misa_mxl_max =3D env->misa_mxl_max; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index fbde0c9248..141a06ddf0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -127,6 +127,11 @@ static inline uint32_t vext_vta(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, VTA); } =20 +static inline uint32_t vext_vma(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VMA); +} + /* * Get the maximum number of elements can be operated. * @@ -797,10 +802,13 @@ static void do_vext_vv(void *vd, void *v0, void *vs1,= void *vs2, uint32_t vl =3D env->vl; uint32_t total_elems =3D vext_get_total_elems(desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); uint32_t i; =20 for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, (i + 1) = * esz); continue; } fn(vd, vs1, vs2, i); --=20 2.34.2 From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650897137963503.52320696162906; Mon, 25 Apr 2022 07:32:17 -0700 (PDT) Received: from localhost ([::1]:43508 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nizlA-0003vA-FQ for importer@patchew.org; Mon, 25 Apr 2022 10:32:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY5-0007HO-5O; Mon, 25 Apr 2022 10:18:45 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41750) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY2-0003PP-Bo; Mon, 25 Apr 2022 10:18:44 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id DDB1B11EF19; Mon, 25 Apr 2022 14:18:39 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 00:47:13 -0700 Subject: [PATCH qemu 2/9] target/riscv: rvv: Add mask agnostic for vector load / store instructions Message-ID: <165089631935.4839.7564289944057093570-2@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650897139592100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 +++++++++ target/riscv/vector_helper.c | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 4610107fb4..4e141e5145 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -712,6 +712,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } =20 @@ -750,6 +751,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } =20 @@ -777,6 +779,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a= , uint8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, 0); data =3D FIELD_DP32(data, VDATA, NF, 1); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } =20 @@ -795,6 +798,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a= , uint8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, 0); data =3D FIELD_DP32(data, VDATA, NF, 1); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } =20 @@ -867,6 +871,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 @@ -897,6 +902,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); fn =3D fns[eew]; if (fn =3D=3D NULL) { return false; @@ -998,6 +1004,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a,= uint8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 @@ -1051,6 +1058,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a= , uint8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } =20 @@ -1117,6 +1125,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, u= int8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldff_trans(a->rd, a->rs1, data, fn, s); } =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 141a06ddf0..bd84b0409c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -296,9 +296,17 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); =20 for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { if (!vm && !vext_elem_mask(v0, i)) { + k =3D 0; + while (k < nf) { + /* set masked-off elements to 1s */ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i + k * max_elem= s, + (i + k * max_elems) * esz, (i + k * max_elems + 1) * e= sz); + k++; + } continue; } =20 @@ -479,10 +487,18 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); =20 /* load bytes from guest memory */ for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { if (!vm && !vext_elem_mask(v0, i)) { + k =3D 0; + while (k < nf) { + /* set masked-off elements to 1s */ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i + k * max_elem= s, + (i + k * max_elems) * esz, (i + k * max_elems + 1) * e= sz); + k++; + } continue; } =20 @@ -568,6 +584,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); target_ulong addr, offset, remain; =20 /* probe every access*/ @@ -614,6 +631,9 @@ ProbeSuccess: for (i =3D env->vstart; i < env->vl; i++) { k =3D 0; if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i + k * max_elems, + (i + k * max_elems) * esz, (i + k * max_elems + 1) * esz); continue; } while (k < nf) { --=20 2.34.2 From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165089690516635.030107187796034; Mon, 25 Apr 2022 07:28:25 -0700 (PDT) Received: from localhost ([::1]:35042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nizhP-0006a0-Hj for importer@patchew.org; Mon, 25 Apr 2022 10:28:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY4-0007HM-PB; Mon, 25 Apr 2022 10:18:45 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY1-0003PQ-VP; Mon, 25 Apr 2022 10:18:44 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 0621111EF24; Mon, 25 Apr 2022 14:18:40 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 01:38:39 -0700 Subject: [PATCH qemu 3/9] target/riscv: rvv: Add mask agnostic for vx instructions Message-ID: <165089631935.4839.7564289944057093570-3@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650896907255100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ target/riscv/vector_helper.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 4e141e5145..e2bdfc0fae 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1308,6 +1308,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 @@ -1484,6 +1485,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bd84b0409c..658ea0244d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -891,10 +891,13 @@ static void do_vext_vx(void *vd, void *v0, target_lon= g s1, void *vs2, uint32_t vl =3D env->vl; uint32_t total_elems =3D vext_get_total_elems(desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); uint32_t i; =20 for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, (i + 1) = * esz); continue; } fn(vd, s1, vs2, i); --=20 2.34.2 From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650896726510337.34607981440695; Mon, 25 Apr 2022 07:25:26 -0700 (PDT) Received: from localhost ([::1]:54776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nizeX-0000lt-Ct for importer@patchew.org; Mon, 25 Apr 2022 10:25:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY3-0007HJ-M7; Mon, 25 Apr 2022 10:18:45 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY1-0003PS-Ri; Mon, 25 Apr 2022 10:18:43 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 2EC0211EF53; Mon, 25 Apr 2022 14:18:40 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 01:43:10 -0700 Subject: [PATCH qemu 4/9] target/riscv: rvv: Add mask agnostic for vector integer shift instructions Message-ID: <165089631935.4839.7564289944057093570-4@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650896726983100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index e2bdfc0fae..a085ef2c29 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1935,6 +1935,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 658ea0244d..269e40c251 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1291,10 +1291,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t esz =3D sizeof(TS1); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \ + (i + 1) * esz); \ continue; \ } \ TS1 s1 =3D *((TS1 *)vs1 + HS1(i)); = \ @@ -1332,10 +1336,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, \ uint32_t esz =3D sizeof(TD); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, \ + i * esz, \ + (i + 1) * esz);\ continue; \ } \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ --=20 2.34.2 From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650896912765139.85766527269777; Mon, 25 Apr 2022 07:28:32 -0700 (PDT) Received: from localhost ([::1]:35662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nizhX-000711-4T for importer@patchew.org; Mon, 25 Apr 2022 10:28:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY6-0007JS-5K; Mon, 25 Apr 2022 10:18:47 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY4-0003Q5-9V; Mon, 25 Apr 2022 10:18:45 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 4D2E511EF81; Mon, 25 Apr 2022 14:18:40 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 01:46:28 -0700 Subject: [PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions Message-ID: <165089631935.4839.7564289944057093570-5@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650896913301100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index a085ef2c29..be08ec8a2e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1742,6 +1742,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 269e40c251..2b341d6679 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1401,12 +1401,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ @@ -1459,11 +1464,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ --=20 2.34.2 From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650897417022933.8403286642414; Mon, 25 Apr 2022 07:36:57 -0700 (PDT) Received: from localhost ([::1]:32780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nizpg-0007Aq-2T for importer@patchew.org; Mon, 25 Apr 2022 10:36:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY6-0007JR-1C; Mon, 25 Apr 2022 10:18:47 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41758) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY4-0003Q6-8U; Mon, 25 Apr 2022 10:18:45 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 69C9711EF86; Mon, 25 Apr 2022 14:18:40 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 01:52:54 -0700 Subject: [PATCH qemu 6/9] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions Message-ID: <165089631935.4839.7564289944057093570-6@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650897419159100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2b341d6679..e266a8673c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2129,10 +2129,12 @@ static inline void vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t vl, uint32_t vm, int vxrm, - opivv2_rm_fn *fn) + opivv2_rm_fn *fn, uint32_t vma, uint32_t esz) { for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, (i + 1) = * esz); continue; } fn(vd, vs1, vs2, i, env, vxrm); @@ -2150,23 +2152,24 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *v= s2, uint32_t vl =3D env->vl; uint32_t total_elems =3D vext_get_total_elems(desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); =20 switch (env->vxrm) { case 0: /* rnu */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, 0, fn); + env, vl, vm, 0, fn, vma, esz); break; case 1: /* rne */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, 1, fn); + env, vl, vm, 1, fn, vma, esz); break; case 2: /* rdn */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, 2, fn); + env, vl, vm, 2, fn, vma, esz); break; default: /* rod */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, 3, fn); + env, vl, vm, 3, fn, vma, esz); break; } /* set tail elements to 1s */ @@ -2250,10 +2253,12 @@ static inline void vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, uint32_t vl, uint32_t vm, int vxrm, - opivx2_rm_fn *fn) + opivx2_rm_fn *fn, uint32_t vma, uint32_t esz) { for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, (i + 1) = * esz); continue; } fn(vd, s1, vs2, i, env, vxrm); @@ -2271,23 +2276,24 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, vo= id *vs2, uint32_t vl =3D env->vl; uint32_t total_elems =3D vext_get_total_elems(desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); =20 switch (env->vxrm) { case 0: /* rnu */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, 0, fn); + env, vl, vm, 0, fn, vma, esz); break; case 1: /* rne */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, 1, fn); + env, vl, vm, 1, fn, vma, esz); break; case 2: /* rdn */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, 2, fn); + env, vl, vm, 2, fn, vma, esz); break; default: /* rod */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, 3, fn); + env, vl, vm, 3, fn, vma, esz); break; } /* set tail elements to 1s */ --=20 2.34.2 From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 25 Apr 2022 14:18:40 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 02:08:01 -0700 Subject: [PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floating-point instructions Message-ID: <165089631935.4839.7564289944057093570-7@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650897314652100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++++++++ target/riscv/vector_helper.c | 36 +++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index be08ec8a2e..e404d24bcf 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2415,6 +2415,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2498,6 +2499,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2537,6 +2539,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2577,6 +2580,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2614,6 +2618,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2654,6 +2659,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2738,6 +2744,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, @@ -2852,6 +2859,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) TCGv_i32 desc; uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_vmv_vx * const fns[3] =3D { gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, @@ -2953,6 +2961,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -3005,6 +3014,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -3073,6 +3083,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -3127,6 +3138,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e266a8673c..0af65e5423 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3051,10 +3051,16 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t total_elems =3D \ vext_get_total_elems(desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, i, \ + i * ESZ, \ + (i + 1) * \ + ESZ); \ continue; \ } \ do_##NAME(vd, vs1, vs2, i, env); \ @@ -3091,10 +3097,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ uint32_t total_elems =3D \ vext_get_total_elems(desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, i, \ + i * ESZ, \ + (i + 1) * \ + ESZ); \ continue; \ } \ do_##NAME(vd, s1, vs2, i, env); \ @@ -3667,6 +3679,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t total_elems =3D \ vext_get_total_elems(desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ if (vl =3D=3D 0) { \ @@ -3674,6 +3687,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ } \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, \ + i, \ + i * ESZ, \ + (i + 1) \ + * ESZ); \ continue; \ } \ do_##NAME(vd, vs2, i, env); \ @@ -4188,12 +4207,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ @@ -4221,11 +4245,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = void *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ @@ -4347,10 +4376,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t total_elems =3D \ vext_get_total_elems(desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, \ + i, \ + i * ESZ, \ + (i + 1) * \ + ESZ); \ continue; \ } \ do_##NAME(vd, vs2, i); \ --=20 2.34.2 From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 25 Apr 2022 14:18:40 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 02:14:47 -0700 Subject: [PATCH qemu 8/9] target/riscv: rvv: Add mask agnostic for vector mask instructions Message-ID: <165089631935.4839.7564289944057093570-8@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650897219748100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/vector_helper.c | 13 +++++++++++++ 2 files changed, 16 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index e404d24bcf..69d00c7116 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3333,6 +3333,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ cpu_env, s->cfg_ptr->vlen / 8, \ @@ -3371,6 +3372,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_gvec_3_ptr * const fns[4] =3D { gen_helper_viota_m_b, gen_helper_viota_m_h, gen_helper_viota_m_w, gen_helper_viota_m_d, @@ -3401,6 +3403,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_gvec_2_ptr * const fns[4] =3D { gen_helper_vid_v_b, gen_helper_vid_v_h, gen_helper_vid_v_w, gen_helper_vid_v_d, diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 0af65e5423..600ccad513 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4895,11 +4895,16 @@ static void vmsetm(void *vd, void *v0, void *vs2, C= PURISCVState *env, uint32_t vl =3D env->vl; uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); int i; bool first_mask_bit =3D false; =20 for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + if (vma) { + vext_set_elem_mask(vd, i, 1); + } continue; } /* write a zero to all following active elements */ @@ -4959,11 +4964,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CP= URISCVState *env, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint32_t sum =3D 0; = \ int i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \ + (i + 1) * esz); \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D sum; = \ @@ -4991,10 +5000,14 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState= *env, uint32_t desc) \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ int i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \ + (i + 1) * esz); \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D i; = \ --=20 2.34.2 From nobody Mon Feb 9 14:00:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650897854374627.326316661661; Mon, 25 Apr 2022 07:44:14 -0700 (PDT) Received: from localhost ([::1]:52538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nizwj-0003RS-Bt for importer@patchew.org; Mon, 25 Apr 2022 10:44:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY7-0007Jv-71; Mon, 25 Apr 2022 10:18:47 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41764) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY5-0003Qd-Bx; Mon, 25 Apr 2022 10:18:46 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id D82B811EFBD; Mon, 25 Apr 2022 14:18:40 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 02:32:47 -0700 Subject: [PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permutation instructions Message-ID: <165089631935.4839.7564289944057093570-9@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650897854779100001 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 34 +++++++++++++++++++++++-- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 69d00c7116..3858a0479a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3975,6 +3975,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 600ccad513..e87806ed64 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5037,11 +5037,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ target_ulong offset =3D s1, i_min, i; = \ \ i_min =3D MAX(env->vstart, offset); = \ for (i =3D i_min; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \ + (i + 1) * esz); \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); = \ @@ -5067,13 +5071,18 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ target_ulong i_max, i; \ \ i_max =3D MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); = \ for (i =3D env->vstart; i < i_max; ++i) { = \ - if (vm || vext_elem_mask(v0, i)) { \ - *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + s1)); = \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \ + (i + 1) * esz); \ + continue; \ } \ + *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + s1)); = \ } \ \ for (i =3D i_max; i < vl; ++i) { = \ @@ -5104,10 +5113,14 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0= , target_ulong s1, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint32_t i; = \ = \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { = \ + /* set masked-off elements to 1s */ = \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, = \ + (i + 1) * esz); = \ continue; = \ } = \ if (i =3D=3D 0) { = \ @@ -5150,10 +5163,14 @@ static void vslide1down_##BITWIDTH(void *vd, void *= v0, target_ulong s1, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint32_t i; = \ = \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { = \ + /* set masked-off elements to 1s */ = \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, = \ + (i + 1) * esz); = \ continue; = \ } = \ if (i =3D=3D vl - 1) { = \ @@ -5222,11 +5239,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ uint32_t esz =3D sizeof(TS2); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint64_t index; \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \ + (i + 1) * esz); \ continue; \ } \ index =3D *((TS1 *)vs1 + HS1(i)); = \ @@ -5263,11 +5284,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint64_t index =3D s1; = \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \ + (i + 1) * esz); \ continue; \ } \ if (index >=3D vlmax) { = \ @@ -5349,10 +5374,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, \ + i * esz, \ + (i + 1) * esz); \ continue; \ } \ *((ETYPE *)vd + HD(i)) =3D *((DTYPE *)vs2 + HS1(i)); \ --=20 2.34.2