From nobody Mon Feb 9 01:31:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=git.sr.ht Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16476372233231018.3084422207745; Fri, 18 Mar 2022 14:00:23 -0700 (PDT) Received: from localhost ([::1]:41596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nVJhv-0002vJ-Nm for importer@patchew.org; Fri, 18 Mar 2022 17:00:23 -0400 Received: from eggs.gnu.org ([209.51.188.92]:58078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nVH6R-0001My-Bo; Fri, 18 Mar 2022 14:13:31 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:35974) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nVH6O-0008NS-3X; Fri, 18 Mar 2022 14:13:31 -0400 Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 075C811EE5E; Fri, 18 Mar 2022 18:13:26 +0000 (UTC) Authentication-Results: mail-b.sr.ht; dkim=none From: ~eopxd Date: Thu, 17 Mar 2022 00:09:09 -0700 Subject: [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store MIME-Version: 1.0 Message-ID: <164762720573.18409.3931931227997483525-0@git.sr.ht> X-Mailer: git.sr.ht To: qemu-devel@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 15 X-Spam_score: 1.5 X-Spam_bar: + X-Spam_report: (1.5 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_24_48=1.34, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 18 Mar 2022 16:57:06 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1647637249415100001 From: Yueh-Ting (eop) Chen According to v-spec (section 7.9): The instructions operate with an effective vector length, evl=3DNFIELDS*VLE= N/EEW, regardless of current settings in vtype and vl. The usual property that no elements are written if vstart =E2=89=A5 vl does not apply to these instruc= tions. Instead, no elements are written if vstart =E2=89=A5 evl. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 275fded6e4..4ea7e41e1a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1121,6 +1121,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t r= s1, uint32_t nf, gen_helper_ldst_whole *fn, DisasContext *s, bool is_store) { + uint32_t evl =3D (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew); + TCGLabel *over =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over); + TCGv_ptr dest; TCGv base; TCGv_i32 desc; @@ -1140,6 +1144,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, if (!is_store) { mark_vs_dirty(s); } + gen_set_label(over); =20 return true; } --=20 2.34.1