From nobody Thu Nov 7 13:41:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1637304711810326.41917492144125; Thu, 18 Nov 2021 22:51:51 -0800 (PST) Received: from localhost ([::1]:60482 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mnxkS-00034p-L8 for importer@patchew.org; Fri, 19 Nov 2021 01:51:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mnxA3-0004Kn-Is for qemu-devel@nongnu.org; Fri, 19 Nov 2021 01:14:12 -0500 Received: from mail.loongson.cn ([114.242.206.163]:46960 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mnxA1-0004aU-4m for qemu-devel@nongnu.org; Fri, 19 Nov 2021 01:14:11 -0500 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxj8+KQJdhSG0AAA--.1952S24; Fri, 19 Nov 2021 14:13:56 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Subject: [PATCH v11 22/26] linux-user: Add LoongArch cpu_loop support Date: Fri, 19 Nov 2021 14:13:26 +0800 Message-Id: <1637302410-24632-23-git-send-email-gaosong@loongson.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1637302410-24632-1-git-send-email-gaosong@loongson.cn> References: <1637302410-24632-1-git-send-email-gaosong@loongson.cn> X-CM-TRANSID: AQAAf9Dxj8+KQJdhSG0AAA--.1952S24 X-Coremail-Antispam: 1UD129KBjvJXoWxXrWUGr17Kr4UXFyUtryrJFb_yoWruF1xpF 1fCr13Kr4kX3y2gws3J3s8uF15Zr4I9rZrGaySkFWrAay7Jry8ur1qgr9rtFy7C3yUWFyx ur9Iv3ZF9F45ZF7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiaojuan Yang , richard.henderson@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1637304713107100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- configure | 5 ++ linux-user/loongarch64/cpu_loop.c | 97 +++++++++++++++++++++++++++++++++= ++++ linux-user/loongarch64/target_cpu.h | 34 +++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 linux-user/loongarch64/cpu_loop.c create mode 100644 linux-user/loongarch64/target_cpu.h diff --git a/configure b/configure index 48c2177..9df99f6 100755 --- a/configure +++ b/configure @@ -581,6 +581,8 @@ elif check_define __arm__ ; then cpu=3D"arm" elif check_define __aarch64__ ; then cpu=3D"aarch64" +elif check_define __loongarch64__ ; then + cpu=3D"loongarch64" else cpu=3D$(uname -m) fi @@ -612,6 +614,9 @@ case "$cpu" in sparc|sun4[cdmuv]) cpu=3D"sparc" ;; + loongarch) + cpu=3D"loongarch" + ;; *) # This will result in either an error or falling back to TCI later ARCH=3Dunknown diff --git a/linux-user/loongarch64/cpu_loop.c b/linux-user/loongarch64/cpu= _loop.c new file mode 100644 index 0000000..f211304 --- /dev/null +++ b/linux-user/loongarch64/cpu_loop.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU LoongArch user cpu_loop. + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "qemu-common.h" +#include "user-internals.h" +#include "cpu_loop-common.h" +#include "signal-common.h" + +void cpu_loop(CPULoongArchState *env) +{ + CPUState *cs =3D env_cpu(env); + int trapnr, si_code; + abi_long ret; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_SYSCALL: + env->pc +=3D 4; + ret =3D do_syscall(env, env->gpr[11], + env->gpr[4], env->gpr[5], + env->gpr[6], env->gpr[7], + env->gpr[8], env->gpr[9], + -1, -1); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 4; + break; + } + if (ret =3D=3D -TARGET_QEMU_ESIGRETURN) { + /* + * Returning from a successful sigreturn syscall. + * Avoid clobbering register state. + */ + break; + } + env->gpr[4] =3D ret; + break; + case EXCP_ADE: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->badad= dr); + break; + case EXCP_INE: + force_sig_fault(TARGET_SIGILL, 0, env->pc); + break; + case EXCP_FPE: + si_code =3D TARGET_FPE_FLTUNK; + if (GET_FP_CAUSE(env->fcsr0) & FP_INVALID) { + si_code =3D TARGET_FPE_FLTINV; + } else if (GET_FP_CAUSE(env->fcsr0) & FP_DIV0) { + si_code =3D TARGET_FPE_FLTDIV; + } else if (GET_FP_CAUSE(env->fcsr0) & FP_OVERFLOW) { + si_code =3D TARGET_FPE_FLTOVF; + } else if (GET_FP_CAUSE(env->fcsr0) & FP_UNDERFLOW) { + si_code =3D TARGET_FPE_FLTUND; + } else if (GET_FP_CAUSE(env->fcsr0) & FP_INEXACT) { + si_code =3D TARGET_FPE_FLTRES; + } + force_sig_fault(TARGET_SIGFPE, si_code, env->pc); + break; + case EXCP_DEBUG: + case EXCP_BREAK: + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", + trapnr); + exit(EXIT_FAILURE); + } + process_pending_signals(env); + } +} + +void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) +{ + int i; + + for (i =3D 0; i < 32; i++) { + env->gpr[i] =3D regs->regs[i]; + } + env->pc =3D regs->csr_era; + +} diff --git a/linux-user/loongarch64/target_cpu.h b/linux-user/loongarch64/t= arget_cpu.h new file mode 100644 index 0000000..a29af66 --- /dev/null +++ b/linux-user/loongarch64/target_cpu.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch specific CPU ABI and functions for linux-user + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + */ + +#ifndef LOONGARCH_TARGET_CPU_H +#define LOONGARCH_TARGET_CPU_H + +static inline void cpu_clone_regs_child(CPULoongArchState *env, + target_ulong newsp, unsigned flags) +{ + if (newsp) { + env->gpr[3] =3D newsp; + } + env->gpr[4] =3D 0; +} + +static inline void cpu_clone_regs_parent(CPULoongArchState *env, + unsigned flags) +{ +} + +static inline void cpu_set_tls(CPULoongArchState *env, target_ulong newtls) +{ + env->gpr[2] =3D newtls; +} + +static inline abi_ulong get_sp_from_cpustate(CPULoongArchState *state) +{ + return state->gpr[3]; +} +#endif --=20 1.8.3.1