From nobody Tue Feb 10 13:17:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636595960466688.6061966181744; Wed, 10 Nov 2021 17:59:20 -0800 (PST) Received: from localhost ([::1]:57514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkzN1-0003sQ-GK for importer@patchew.org; Wed, 10 Nov 2021 20:59:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkz0g-00068Z-37 for qemu-devel@nongnu.org; Wed, 10 Nov 2021 20:36:14 -0500 Received: from mail.loongson.cn ([114.242.206.163]:54194 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkz0d-0001pG-Im for qemu-devel@nongnu.org; Wed, 10 Nov 2021 20:36:13 -0500 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxr9Ngc4xh9RMCAA--.4955S22; Thu, 11 Nov 2021 09:35:57 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 20/30] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Date: Thu, 11 Nov 2021 09:35:18 +0800 Message-Id: <1636594528-8175-21-git-send-email-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1636594528-8175-1-git-send-email-yangxiaojuan@loongson.cn> References: <1636594528-8175-1-git-send-email-yangxiaojuan@loongson.cn> X-CM-TRANSID: AQAAf9Dxr9Ngc4xh9RMCAA--.4955S22 X-Coremail-Antispam: 1UD129KBjvJXoWxGry5JF1kCryDAr15tF48tFb_yoWrtrW5pr sxuw15Kr4kJa17WrZ3J34fAFZ5JFs7Wry2vF4a9ryIkr47AFyrZ3Wktry7WFyUK3ykGryj 9FZ5C3W7Xa1UGaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Song Gao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636595961591100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch realize PCH-MSI interrupt controller. Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- hw/intc/Kconfig | 5 ++ hw/intc/loongarch_pch_msi.c | 73 +++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + hw/loongarch/Kconfig | 1 + include/hw/intc/loongarch_pch_msi.h | 16 +++++++ 5 files changed, 96 insertions(+) create mode 100644 hw/intc/loongarch_pch_msi.c create mode 100644 include/hw/intc/loongarch_pch_msi.h diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 3b7eca7b03..c0dc12dfa0 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -77,3 +77,8 @@ config M68K_IRQC config LOONGARCH_PCH_PIC bool select UNIMP + +config LOONGARCH_PCH_MSI + select MSI_NONBROKEN + bool + select UNIMP diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c new file mode 100644 index 0000000000..1d8a3c1b21 --- /dev/null +++ b/hw/intc/loongarch_pch_msi.c @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Loongson 7A1000 msi interrupt controller. + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/intc/loongarch_pch_msi.h" +#include "hw/pci/msi.h" +#include "hw/misc/unimp.h" +#include "migration/vmstate.h" + +#define DEBUG_LOONGARCH_PCH_MSI 0 + +#define DPRINTF(fmt, ...) \ +do { \ + if (DEBUG_LOONGARCH_PCH_MSI) { \ + fprintf(stderr, "LOONGARCH_PCH_MSI: " fmt , ## __VA_ARGS__); \ + } \ +} while (0) + +static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned= size) +{ + return 0; +} + +static void loongarch_msi_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + loongarch_pch_msi *s =3D opaque; + int irq_num =3D val & 0xff; + + qemu_set_irq(s->pch_msi_irq[irq_num - 32], 1); +} + +static const MemoryRegionOps loongarch_pch_msi_ops =3D { + .read =3D loongarch_msi_mem_read, + .write =3D loongarch_msi_mem_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void loongarch_pch_msi_init(Object *obj) +{ + loongarch_pch_msi *s =3D LOONGARCH_PCH_MSI(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + int tmp; + + memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops, + s, TYPE_LOONGARCH_PCH_MSI, 0x8); + sysbus_init_mmio(sbd, &s->msi_mmio); + msi_nonbroken =3D true; + + for (tmp =3D 0; tmp < 224; tmp++) { + sysbus_init_irq(sbd, &s->pch_msi_irq[tmp]); + } +} + +static const TypeInfo loongarch_pch_msi_info =3D { + .name =3D TYPE_LOONGARCH_PCH_MSI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(loongarch_pch_msi), + .instance_init =3D loongarch_pch_msi_init, +}; + +static void loongarch_pch_msi_register_types(void) +{ + type_register_static(&loongarch_pch_msi_info); +} + +type_init(loongarch_pch_msi_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 07b0627468..e04abe2d56 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -58,3 +58,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.= c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarc= h_pch_pic.c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarc= h_pch_msi.c')) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index c6d7ebcd5b..4500fd3a57 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -2,3 +2,4 @@ config LOONGSON_3A5000 bool select PCI_EXPRESS_7A select LOONGARCH_PCH_PIC + select LOONGARCH_PCH_MSI diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarc= h_pch_msi.h new file mode 100644 index 0000000000..40f0575bb5 --- /dev/null +++ b/include/hw/intc/loongarch_pch_msi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch 7A1000 I/O interrupt controller definitions + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" +DECLARE_INSTANCE_CHECKER(struct loongarch_pch_msi, LOONGARCH_PCH_MSI, + TYPE_LOONGARCH_PCH_MSI) + +typedef struct loongarch_pch_msi { + SysBusDevice parent_obj; + qemu_irq pch_msi_irq[224]; + MemoryRegion msi_mmio; +} loongarch_pch_msi; --=20 2.27.0