From nobody Wed Apr 24 22:35:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634562300757897.7088051886327; Mon, 18 Oct 2021 06:05:00 -0700 (PDT) Received: from localhost ([::1]:40260 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcSK2-0001At-GX for importer@patchew.org; Mon, 18 Oct 2021 09:04:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcS3Z-00056W-EW for qemu-devel@nongnu.org; Mon, 18 Oct 2021 08:47:57 -0400 Received: from mail.loongson.cn ([114.242.206.163]:50048 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcS3W-0003iA-1e for qemu-devel@nongnu.org; Mon, 18 Oct 2021 08:47:57 -0400 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxT2rfbG1hyhAcAA--.29044S13; Mon, 18 Oct 2021 20:47:39 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Subject: [PATCH v7 11/21] target/loongarch: Add floating point comparison instruction translation Date: Mon, 18 Oct 2021 20:47:17 +0800 Message-Id: <1634561247-25499-12-git-send-email-gaosong@loongson.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1634561247-25499-1-git-send-email-gaosong@loongson.cn> References: <1634561247-25499-1-git-send-email-gaosong@loongson.cn> X-CM-TRANSID: AQAAf9DxT2rfbG1hyhAcAA--.29044S13 X-Coremail-Antispam: 1UD129KBjvJXoW3Xr4DJF17KFyfurW8XryrJFb_yoW3JFW7pF W7Zry3GF48WFW3Jas2ga98GF15Jr48Ka17uFy3t34vyF45XFn7ZFy8ta429FWUG3s5ury8 X3WSyryUWFy7XaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@loongson.cn, philmd@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, peterx@redhat.com, f4bug@amsat.org, yangxiaojuan@loongson.cn, alistair.francis@wdc.com, maobibo@loongson.cn, pbonzini@redhat.com, bmeng.cn@gmail.com, alex.bennee@linaro.org, gaosong@loongson.cn Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1634562328125100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch implement floating point comparison instruction translation. This includes: - FCMP.cond.{S/D} Signed-off-by: Song Gao Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- target/loongarch/fpu_helper.c | 60 ++++++++++++++++++++++++++++= ++++ target/loongarch/helper.h | 9 +++++ target/loongarch/insn_trans/trans_fcmp.c | 59 ++++++++++++++++++++++++++++= +++ target/loongarch/insns.decode | 10 ++++++ target/loongarch/internals.h | 5 +++ target/loongarch/translate.c | 1 + 6 files changed, 144 insertions(+) create mode 100644 target/loongarch/insn_trans/trans_fcmp.c diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c index 0106881..49d3af8 100644 --- a/target/loongarch/fpu_helper.c +++ b/target/loongarch/fpu_helper.c @@ -404,3 +404,63 @@ uint64_t helper_fmuladd_d(CPULoongArchState *env, uint= 64_t fj, update_fcsr0(env, GETPC()); return fd; } + +static uint64_t fcmp_common(CPULoongArchState *env, FloatRelation cmp, + uint32_t flags) +{ + bool ret; + + switch (cmp) { + case float_relation_less: + ret =3D (flags & FCMP_LT); + break; + case float_relation_equal: + ret =3D (flags & FCMP_EQ); + break; + case float_relation_greater: + ret =3D (flags & FCMP_GT); + break; + case float_relation_unordered: + ret =3D (flags & FCMP_UN); + break; + default: + g_assert_not_reached(); + } + update_fcsr0(env, GETPC()); + + return ret; +} + +/* fcmp_cXXX_s */ +uint64_t helper_fcmp_c_s(CPULoongArchState *env, uint64_t fj, + uint64_t fk, uint32_t flags) +{ + FloatRelation cmp =3D float32_compare_quiet((uint32_t)fj, + (uint32_t)fk, &env->fp_statu= s); + return fcmp_common(env, cmp, flags); +} + +/* fcmp_sXXX_s */ +uint64_t helper_fcmp_s_s(CPULoongArchState *env, uint64_t fj, + uint64_t fk, uint32_t flags) +{ + FloatRelation cmp =3D float32_compare((uint32_t)fj, + (uint32_t)fk, &env->fp_status); + return fcmp_common(env, cmp, flags); +} + +/* fcmp_cXXX_d */ +uint64_t helper_fcmp_c_d(CPULoongArchState *env, uint64_t fj, + uint64_t fk, uint32_t flags) +{ + FloatRelation cmp =3D float64_compare_quiet(fj, fk, &env->fp_status); + return fcmp_common(env, cmp, flags); +} + +/* fcmp_sXXX_d */ +uint64_t helper_fcmp_s_d(CPULoongArchState *env, uint64_t fj, + uint64_t fk, uint32_t flags) +{ + FloatRelation cmp =3D float64_compare(fj, fk, &env->fp_status); + return fcmp_common(env, cmp, flags); +} diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 901ab27..e0ab735 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -55,3 +55,12 @@ DEF_HELPER_2(frecip_d, i64, env, i64) =20 DEF_HELPER_FLAGS_2(fclass_s, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(fclass_d, TCG_CALL_NO_RWG_SE, i64, env, i64) + +/* fcmp.cXXX.s */ +DEF_HELPER_4(fcmp_c_s, i64, env, i64, i64, i32) +/* fcmp.sXXX.s */ +DEF_HELPER_4(fcmp_s_s, i64, env, i64, i64, i32) +/* fcmp.cXXX.d */ +DEF_HELPER_4(fcmp_c_d, i64, env, i64, i64, i32) +/* fcmp.sXXX.d */ +DEF_HELPER_4(fcmp_s_d, i64, env, i64, i64, i32) diff --git a/target/loongarch/insn_trans/trans_fcmp.c b/target/loongarch/in= sn_trans/trans_fcmp.c new file mode 100644 index 0000000..1c5945b --- /dev/null +++ b/target/loongarch/insn_trans/trans_fcmp.c @@ -0,0 +1,59 @@ +/* + * LoongArch translate functions + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +/* bit0(signaling/quiet) bit1(lt) bit2(eq) bit3(un) bit4(neq) */ +static uint32_t get_fcmp_flags(int cond) +{ + uint32_t flags =3D 0; + + if (cond & 0x1) { + flags |=3D FCMP_LT; + } + if (cond & 0x2) { + flags |=3D FCMP_EQ; + } + if (cond & 0x4) { + flags |=3D FCMP_UN; + } + if (cond & 0x8) { + flags |=3D FCMP_GT | FCMP_LT; + } + return flags; +} + +static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a) +{ + TCGv var =3D tcg_temp_new(); + uint32_t flags; + void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); + + fn =3D (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s); + flags =3D get_fcmp_flags(a->fcond >> 1); + + fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flag= s)); + + tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x= 7])); + tcg_temp_free(var); + return true; +} + +static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a) +{ + TCGv var =3D tcg_temp_new(); + uint32_t flags; + void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); + fn =3D (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d); + flags =3D get_fcmp_flags(a->fcond >> 1); + + fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flag= s)); + + tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x= 7])); + + tcg_temp_free(var); + return true; +} diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 9e6a727..8aadcfd 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -32,6 +32,8 @@ %fj 5:5 %fk 10:5 %fa 15:5 +%cd 0:3 +%fcond 15:5 =20 # # Argument sets @@ -56,6 +58,7 @@ &fmt_fdfjfk fd fj fk &fmt_fdfjfkfa fd fj fk fa &fmt_fdfj fd fj +&fmt_cdfjfkfcond cd fj fk fcond =20 # # Formats @@ -80,6 +83,7 @@ @fmt_fdfjfk .... ........ ..... ..... ..... ..... &fmt_fdfjfk = %fd %fj %fk @fmt_fdfjfkfa .... ........ ..... ..... ..... ..... &fmt_fdfjfkf= a %fd %fj %fk %fa @fmt_fdfj .... ........ ..... ..... ..... ..... &fmt_fdfj = %fd %fj +@fmt_cdfjfkfcond .... ........ ..... ..... ..... .. ... &fmt_cdfjfkf= cond %cd %fj %fk %fcond =20 # # Fixed point arithmetic operation instruction @@ -341,3 +345,9 @@ fcopysign_s 0000 00010001 00101 ..... ..... ..... = @fmt_fdfjfk fcopysign_d 0000 00010001 00110 ..... ..... ..... @fmt_fdfjfk fclass_s 0000 00010001 01000 01101 ..... ..... @fmt_fdfj fclass_d 0000 00010001 01000 01110 ..... ..... @fmt_fdfj + +# +# Floating point compare instruction +# +fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @fmt_cdfjfkfcond +fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @fmt_cdfjfkfcond diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 096a4a7..b408aed 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -9,6 +9,11 @@ #ifndef LOONGARCH_INTERNALS_H #define LOONGARCH_INTERNALS_H =20 +#define FCMP_LT 0x0001 /* fp0 < fp1 */ +#define FCMP_EQ 0x0010 /* fp0 =3D fp1 */ +#define FCMP_UN 0x0100 /* unordered */ +#define FCMP_GT 0x1000 /* fp0 > fp1 */ + void loongarch_translate_init(void); =20 void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags); diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 9eeaf76..7301ac5 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -187,6 +187,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExten= d dst_ext) #include "insn_trans/trans_atomic.c" #include "insn_trans/trans_extra.c" #include "insn_trans/trans_farith.c" +#include "insn_trans/trans_fcmp.c" =20 static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState= *cs) { --=20 1.8.3.1