From nobody Mon Feb 9 17:24:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634034045263981.2987093000274; Tue, 12 Oct 2021 03:20:45 -0700 (PDT) Received: from localhost ([::1]:54056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maEto-0001bO-2Z for importer@patchew.org; Tue, 12 Oct 2021 06:20:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maEkv-0000X6-93 for qemu-devel@nongnu.org; Tue, 12 Oct 2021 06:11:33 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:12878) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1maEks-0006y1-CQ for qemu-devel@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634034046461100001 Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/translate.h | 61 ++++++++++++ target/hexagon/genptr.c | 15 +++ target/hexagon/translate.c | 243 +++++++++++++++++++++++++++++++++++++++++= +++- 3 files changed, 315 insertions(+), 4 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 703fd13..fccfb94 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -29,6 +29,7 @@ typedef struct DisasContext { uint32_t mem_idx; uint32_t num_packets; uint32_t num_insns; + uint32_t num_hvx_insns; int reg_log[REG_WRITES_MAX]; int reg_log_idx; DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); @@ -37,6 +38,20 @@ typedef struct DisasContext { DECLARE_BITMAP(pregs_written, NUM_PREGS); uint8_t store_width[STORES_MAX]; bool s1_store_processed; + int future_vregs_idx; + int future_vregs_num[VECTOR_TEMPS_MAX]; + int tmp_vregs_idx; + int tmp_vregs_num[VECTOR_TEMPS_MAX]; + int vreg_log[NUM_VREGS]; + bool vreg_is_predicated[NUM_VREGS]; + int vreg_log_idx; + DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS); + DECLARE_BITMAP(vregs_updated, NUM_VREGS); + DECLARE_BITMAP(vregs_select, NUM_VREGS); + int qreg_log[NUM_QREGS]; + bool qreg_is_predicated[NUM_QREGS]; + int qreg_log_idx; + bool pre_commit; } DisasContext; =20 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) @@ -67,6 +82,46 @@ static inline bool is_preloaded(DisasContext *ctx, int n= um) return test_bit(num, ctx->regs_written); } =20 +intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, + int num, bool alloc_ok); +intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, + int num, bool alloc_ok); + +static inline void ctx_log_vreg_write(DisasContext *ctx, + int rnum, VRegWriteType type, + bool is_predicated) +{ + if (type !=3D EXT_TMP) { + ctx->vreg_log[ctx->vreg_log_idx] =3D rnum; + ctx->vreg_is_predicated[ctx->vreg_log_idx] =3D is_predicated; + ctx->vreg_log_idx++; + + set_bit(rnum, ctx->vregs_updated); + } + if (type =3D=3D EXT_NEW) { + set_bit(rnum, ctx->vregs_select); + } + if (type =3D=3D EXT_TMP) { + set_bit(rnum, ctx->vregs_updated_tmp); + } +} + +static inline void ctx_log_vreg_write_pair(DisasContext *ctx, + int rnum, VRegWriteType type, + bool is_predicated) +{ + ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated); + ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated); +} + +static inline void ctx_log_qreg_write(DisasContext *ctx, + int rnum, bool is_predicated) +{ + ctx->qreg_log[ctx->qreg_log_idx] =3D rnum; + ctx->qreg_is_predicated[ctx->qreg_log_idx] =3D is_predicated; + ctx->qreg_log_idx++; +} + extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; extern TCGv hex_pred[NUM_PREGS]; extern TCGv hex_next_PC; @@ -85,6 +140,12 @@ extern TCGv hex_dczero_addr; extern TCGv hex_llsc_addr; extern TCGv hex_llsc_val; extern TCGv_i64 hex_llsc_val_i64; +extern TCGv hex_VRegs_updated; +extern TCGv hex_QRegs_updated; +extern TCGv hex_vstore_addr[VSTORES_MAX]; +extern TCGv hex_vstore_size[VSTORES_MAX]; +extern TCGv hex_vstore_pending[VSTORES_MAX]; =20 +bool is_gather_store_insn(Insn *insn, Packet *pkt); void process_store(DisasContext *ctx, Packet *pkt, int slot_num); #endif diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 4a21fa5..d16ff74 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -165,6 +165,9 @@ static inline void gen_read_ctrl_reg(DisasContext *ctx,= const int reg_num, } else if (reg_num =3D=3D HEX_REG_QEMU_INSN_CNT) { tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); + } else if (reg_num =3D=3D HEX_REG_QEMU_HVX_CNT) { + tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_HVX_CNT], + ctx->num_hvx_insns); } else { tcg_gen_mov_tl(dest, hex_gpr[reg_num]); } @@ -191,6 +194,12 @@ static inline void gen_read_ctrl_reg_pair(DisasContext= *ctx, const int reg_num, tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt); tcg_temp_free(pkt_cnt); tcg_temp_free(insn_cnt); + } else if (reg_num =3D=3D HEX_REG_QEMU_HVX_CNT) { + TCGv hvx_cnt =3D tcg_temp_new(); + tcg_gen_addi_tl(hvx_cnt, hex_gpr[HEX_REG_QEMU_HVX_CNT], + ctx->num_hvx_insns); + tcg_gen_concat_i32_i64(dest, hvx_cnt, hex_gpr[reg_num + 1]); + tcg_temp_free(hvx_cnt); } else { tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], @@ -226,6 +235,9 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx= , int reg_num, if (reg_num =3D=3D HEX_REG_QEMU_INSN_CNT) { ctx->num_insns =3D 0; } + if (reg_num =3D=3D HEX_REG_QEMU_HVX_CNT) { + ctx->num_hvx_insns =3D 0; + } } } =20 @@ -247,6 +259,9 @@ static inline void gen_write_ctrl_reg_pair(DisasContext= *ctx, int reg_num, ctx->num_packets =3D 0; ctx->num_insns =3D 0; } + if (reg_num =3D=3D HEX_REG_QEMU_HVX_CNT) { + ctx->num_hvx_insns =3D 0; + } } } =20 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 4f05ce3..e33e39c 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" @@ -47,11 +48,60 @@ TCGv hex_dczero_addr; TCGv hex_llsc_addr; TCGv hex_llsc_val; TCGv_i64 hex_llsc_val_i64; +TCGv hex_VRegs_updated; +TCGv hex_QRegs_updated; +TCGv hex_vstore_addr[VSTORES_MAX]; +TCGv hex_vstore_size[VSTORES_MAX]; +TCGv hex_vstore_pending[VSTORES_MAX]; =20 static const char * const hexagon_prednames[] =3D { "p0", "p1", "p2", "p3" }; =20 +intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, + int num, bool alloc_ok) +{ + intptr_t offset; + + /* See if it is already allocated */ + for (int i =3D 0; i < ctx->future_vregs_idx; i++) { + if (ctx->future_vregs_num[i] =3D=3D regnum) { + return offsetof(CPUHexagonState, future_VRegs[i]); + } + } + + g_assert(alloc_ok); + offset =3D offsetof(CPUHexagonState, future_VRegs[ctx->future_vregs_id= x]); + for (int i =3D 0; i < num; i++) { + ctx->future_vregs_num[ctx->future_vregs_idx + i] =3D regnum++; + } + ctx->future_vregs_idx +=3D num; + g_assert(ctx->future_vregs_idx <=3D VECTOR_TEMPS_MAX); + return offset; +} + +intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, + int num, bool alloc_ok) +{ + intptr_t offset; + + /* See if it is already allocated */ + for (int i =3D 0; i < ctx->tmp_vregs_idx; i++) { + if (ctx->tmp_vregs_num[i] =3D=3D regnum) { + return offsetof(CPUHexagonState, tmp_VRegs[i]); + } + } + + g_assert(alloc_ok); + offset =3D offsetof(CPUHexagonState, tmp_VRegs[ctx->tmp_vregs_idx]); + for (int i =3D 0; i < num; i++) { + ctx->tmp_vregs_num[ctx->tmp_vregs_idx + i] =3D regnum++; + } + ctx->tmp_vregs_idx +=3D num; + g_assert(ctx->tmp_vregs_idx <=3D VECTOR_TEMPS_MAX); + return offset; +} + static void gen_exception_raw(int excp) { gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); @@ -63,6 +113,8 @@ static void gen_exec_counters(DisasContext *ctx) hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT], + hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); } =20 static void gen_end_tb(DisasContext *ctx) @@ -171,11 +223,19 @@ static void gen_start_packet(DisasContext *ctx, Packe= t *pkt) bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); ctx->preg_log_idx =3D 0; bitmap_zero(ctx->pregs_written, NUM_PREGS); + ctx->future_vregs_idx =3D 0; + ctx->tmp_vregs_idx =3D 0; + ctx->vreg_log_idx =3D 0; + bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS); + bitmap_zero(ctx->vregs_updated, NUM_VREGS); + bitmap_zero(ctx->vregs_select, NUM_VREGS); + ctx->qreg_log_idx =3D 0; for (i =3D 0; i < STORES_MAX; i++) { ctx->store_width[i] =3D 0; } tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); ctx->s1_store_processed =3D false; + ctx->pre_commit =3D true; =20 if (HEX_DEBUG) { /* Handy place to set a breakpoint before the packet executes */ @@ -197,6 +257,26 @@ static void gen_start_packet(DisasContext *ctx, Packet= *pkt) if (need_pred_written(pkt)) { tcg_gen_movi_tl(hex_pred_written, 0); } + + if (pkt->pkt_has_hvx) { + tcg_gen_movi_tl(hex_VRegs_updated, 0); + tcg_gen_movi_tl(hex_QRegs_updated, 0); + } +} + +bool is_gather_store_insn(Insn *insn, Packet *pkt) +{ + if (GET_ATTRIB(insn->opcode, A_CVI_NEW) && + insn->new_value_producer_slot =3D=3D 1) { + /* Look for gather instruction */ + for (int i =3D 0; i < pkt->num_insns; i++) { + Insn *in =3D &pkt->insn[i]; + if (GET_ATTRIB(in->opcode, A_CVI_GATHER) && in->slot =3D=3D 1)= { + return true; + } + } + } + return false; } =20 /* @@ -445,10 +525,102 @@ static void process_dczeroa(DisasContext *ctx, Packe= t *pkt) } } =20 +static bool pkt_has_hvx_store(Packet *pkt) +{ + int i; + for (i =3D 0; i < pkt->num_insns; i++) { + int opcode =3D pkt->insn[i].opcode; + if (GET_ATTRIB(opcode, A_CVI) && GET_ATTRIB(opcode, A_STORE)) { + return true; + } + } + return false; +} + +static void gen_commit_hvx(DisasContext *ctx, Packet *pkt) +{ + int i; + + /* + * for (i =3D 0; i < ctx->vreg_log_idx; i++) { + * int rnum =3D ctx->vreg_log[i]; + * if (ctx->vreg_is_predicated[i]) { + * if (env->VRegs_updated & (1 << rnum)) { + * env->VRegs[rnum] =3D env->future_VRegs[rnum]; + * } + * } else { + * env->VRegs[rnum] =3D env->future_VRegs[rnum]; + * } + * } + */ + for (i =3D 0; i < ctx->vreg_log_idx; i++) { + int rnum =3D ctx->vreg_log[i]; + bool is_predicated =3D ctx->vreg_is_predicated[i]; + intptr_t dstoff =3D offsetof(CPUHexagonState, VRegs[rnum]); + intptr_t srcoff =3D ctx_future_vreg_off(ctx, rnum, 1, false); + size_t size =3D sizeof(MMVector); + + if (is_predicated) { + TCGv cmp =3D tcg_temp_local_new(); + TCGLabel *label_skip =3D gen_new_label(); + + tcg_gen_andi_tl(cmp, hex_VRegs_updated, 1 << rnum); + tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); + { + tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); + } + gen_set_label(label_skip); + tcg_temp_free(cmp); + } else { + tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); + } + } + + /* + * for (i =3D 0; i < ctx->qreg_log_idx; i++) { + * int rnum =3D ctx->qreg_log[i]; + * if (ctx->qreg_is_predicated[i]) { + * if (env->QRegs_updated) & (1 << rnum)) { + * env->QRegs[rnum] =3D env->future_QRegs[rnum]; + * } + * } else { + * env->QRegs[rnum] =3D env->future_QRegs[rnum]; + * } + * } + */ + for (i =3D 0; i < ctx->qreg_log_idx; i++) { + int rnum =3D ctx->qreg_log[i]; + bool is_predicated =3D ctx->qreg_is_predicated[i]; + intptr_t dstoff =3D offsetof(CPUHexagonState, QRegs[rnum]); + intptr_t srcoff =3D offsetof(CPUHexagonState, future_QRegs[rnum]); + size_t size =3D sizeof(MMQReg); + + if (is_predicated) { + TCGv cmp =3D tcg_temp_local_new(); + TCGLabel *label_skip =3D gen_new_label(); + + tcg_gen_andi_tl(cmp, hex_QRegs_updated, 1 << rnum); + tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); + { + tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); + } + gen_set_label(label_skip); + tcg_temp_free(cmp); + } else { + tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); + } + } + + if (pkt_has_hvx_store(pkt)) { + gen_helper_commit_hvx_stores(cpu_env); + } +} + static void update_exec_counters(DisasContext *ctx, Packet *pkt) { int num_insns =3D pkt->num_insns; int num_real_insns =3D 0; + int num_hvx_insns =3D 0; =20 for (int i =3D 0; i < num_insns; i++) { if (!pkt->insn[i].is_endloop && @@ -456,13 +628,18 @@ static void update_exec_counters(DisasContext *ctx, P= acket *pkt) !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { num_real_insns++; } + if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) { + num_hvx_insns++; + } } =20 ctx->num_packets++; ctx->num_insns +=3D num_real_insns; + ctx->num_hvx_insns +=3D num_hvx_insns; } =20 -static void gen_commit_packet(DisasContext *ctx, Packet *pkt) +static void gen_commit_packet(CPUHexagonState *env, DisasContext *ctx, + Packet *pkt) { /* * If there is more than one store in a packet, make sure they are all= OK @@ -471,6 +648,10 @@ static void gen_commit_packet(DisasContext *ctx, Packe= t *pkt) * dczeroa has to be the only store operation in the packet, so we go * ahead and process that first. * + * When there is an HVX store, there can also be a scalar store in eit= her + * slot 0 or slot1, so we create a mask for the helper to indicate what + * work to do. + * * When there are two scalar stores, we probe the one in slot 0. * * Note that we don't call the probe helper for packets with only one @@ -479,13 +660,35 @@ static void gen_commit_packet(DisasContext *ctx, Pack= et *pkt) */ bool has_store_s0 =3D pkt->pkt_has_store_s0; bool has_store_s1 =3D (pkt->pkt_has_store_s1 && !ctx->s1_store_process= ed); + bool has_hvx_store =3D pkt_has_hvx_store(pkt); if (pkt->pkt_has_dczeroa) { /* * The dczeroa will be the store in slot 0, check that we don't ha= ve - * a store in slot 1. + * a store in slot 1 or an HVX store. */ - g_assert(has_store_s0 && !has_store_s1); + g_assert(has_store_s0 && !has_store_s1 && !has_hvx_store); process_dczeroa(ctx, pkt); + } else if (has_hvx_store) { + TCGv mem_idx =3D tcg_constant_tl(ctx->mem_idx); + + if (!has_store_s0 && !has_store_s1) { + gen_helper_probe_hvx_stores(cpu_env, mem_idx); + } else { + int mask =3D 0; + TCGv mask_tcgv; + + if (has_store_s0) { + mask |=3D (1 << 0); + } + if (has_store_s1) { + mask |=3D (1 << 1); + } + if (has_hvx_store) { + mask |=3D (1 << 2); + } + mask_tcgv =3D tcg_constant_tl(mask); + gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, mask_tcgv, mem= _idx); + } } else if (has_store_s0 && has_store_s1) { /* * process_store_log will execute the slot 1 store first, @@ -500,6 +703,9 @@ static void gen_commit_packet(DisasContext *ctx, Packet= *pkt) =20 gen_reg_writes(ctx); gen_pred_writes(ctx, pkt); + if (pkt->pkt_has_hvx) { + gen_commit_hvx(ctx, pkt); + } update_exec_counters(ctx, pkt); if (HEX_DEBUG) { TCGv has_st0 =3D @@ -511,6 +717,11 @@ static void gen_commit_packet(DisasContext *ctx, Packe= t *pkt) gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); } =20 + if (pkt->vhist_insn !=3D NULL) { + ctx->pre_commit =3D false; + pkt->vhist_insn->generate(env, ctx, pkt->vhist_insn, pkt); + } + if (pkt->pkt_has_cof) { gen_end_tb(ctx); } @@ -535,7 +746,7 @@ static void decode_and_translate_packet(CPUHexagonState= *env, DisasContext *ctx) for (i =3D 0; i < pkt.num_insns; i++) { gen_insn(env, ctx, &pkt.insn[i], &pkt); } - gen_commit_packet(ctx, &pkt); + gen_commit_packet(env, ctx, &pkt); ctx->base.pc_next +=3D pkt.encod_pkt_size_in_bytes; } else { gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); @@ -550,6 +761,7 @@ static void hexagon_tr_init_disas_context(DisasContextB= ase *dcbase, ctx->mem_idx =3D MMU_USER_IDX; ctx->num_packets =3D 0; ctx->num_insns =3D 0; + ctx->num_hvx_insns =3D 0; } =20 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -658,6 +870,9 @@ static char store_addr_names[STORES_MAX][NAME_LEN]; static char store_width_names[STORES_MAX][NAME_LEN]; static char store_val32_names[STORES_MAX][NAME_LEN]; static char store_val64_names[STORES_MAX][NAME_LEN]; +static char vstore_addr_names[VSTORES_MAX][NAME_LEN]; +static char vstore_size_names[VSTORES_MAX][NAME_LEN]; +static char vstore_pending_names[VSTORES_MAX][NAME_LEN]; =20 void hexagon_translate_init(void) { @@ -720,6 +935,10 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, llsc_val), "llsc_val"); hex_llsc_val_i64 =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); + hex_VRegs_updated =3D tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, VRegs_updated), "VRegs_updated"); + hex_QRegs_updated =3D tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, QRegs_updated), "QRegs_updated"); for (i =3D 0; i < STORES_MAX; i++) { snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); hex_store_addr[i] =3D tcg_global_mem_new(cpu_env, @@ -741,4 +960,20 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, mem_log_stores[i].data64), store_val64_names[i]); } + for (int i =3D 0; i < VSTORES_MAX; i++) { + snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); + hex_vstore_addr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, vstore[i].va), + vstore_addr_names[i]); + + snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i); + hex_vstore_size[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, vstore[i].size), + vstore_size_names[i]); + + snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i= ); + hex_vstore_pending[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, vstore_pending[i]), + vstore_pending_names[i]); + } } --=20 2.7.4