From nobody Tue Feb 10 05:45:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634032037909155.63416944816413; Tue, 12 Oct 2021 02:47:17 -0700 (PDT) Received: from localhost ([::1]:44734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maENQ-0000Id-QV for importer@patchew.org; Tue, 12 Oct 2021 05:47:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41966) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maE8Q-0008F5-LZ for qemu-devel@nongnu.org; Tue, 12 Oct 2021 05:31:46 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:25400) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1maE8M-00073h-Dm for qemu-devel@nongnu.org; Tue, 12 Oct 2021 05:31:46 -0400 Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Oct 2021 02:31:38 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg03-sd.qualcomm.com with ESMTP; 12 Oct 2021 02:31:38 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D19C4672; Tue, 12 Oct 2021 04:31:37 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1634031102; x=1665567102; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/pjacqsTvFm3q+RGBcdDiN/VtLorvzsMud8fOPxg0OI=; b=Dq+JFLnHFtS2+gUvSSznObxJii474V8UpEalstMF3fLtL1Ok/fHyMx3S L2mAy8qwAw/uhMxfuO4CLijHpUhv5xRa9kdHmjXYmJiJZjv78DNe9deUA fifkNMqY5MqrRKi9UlJXaWMLZzhCkBIoG4178UPgKp0tP7oz/iMh6ShdO k=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 2/2] Hexagon (target/hexagon) put writes to USR into temp until commit Date: Tue, 12 Oct 2021 04:31:21 -0500 Message-Id: <1634031081-25450-4-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634031081-25450-1-git-send-email-tsimpson@quicinc.com> References: <1634031081-25450-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634032039956100001 Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead of hex_gpr[HEX_REG_USR]. Then, we need code to mark the instructions that can set implicitly set USR - Macros added to hex_common.py - A_FPOP added in translate.c Test case added in tests/tcg/hexagon/overflow.c Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/macros.h | 2 +- target/hexagon/attribs_def.h.inc | 1 + target/hexagon/translate.c | 9 +++- tests/tcg/hexagon/overflow.c | 107 ++++++++++++++++++++++++++++++++++= ++++ target/hexagon/hex_common.py | 2 + tests/tcg/hexagon/Makefile.target | 1 + 6 files changed, 120 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/hexagon/overflow.c diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 5c19cde..13e957b 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -62,7 +62,7 @@ reg_field_info[FIELD].offset) =20 #define SET_USR_FIELD(FIELD, VAL) \ - fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ + fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width,= \ reg_field_info[FIELD].offset, (VAL)) #endif =20 diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index 3815509..e44a7ea 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -64,6 +64,7 @@ DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", = "UREG.P1") DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2") DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3") DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "") +DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "") DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "") =20 DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "") diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index e065092..f1760ce 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -208,7 +208,12 @@ static void mark_implicit_reg_write(DisasContext *ctx,= Insn *insn, int attrib, int rnum) { if (GET_ATTRIB(insn->opcode, attrib)) { - bool is_predicated =3D GET_ATTRIB(insn->opcode, A_CONDEXEC); + /* + * USR is used to set overflow and FP exceptions, + * so treat it as conditional + */ + bool is_predicated =3D GET_ATTRIB(insn->opcode, A_CONDEXEC) || + rnum =3D=3D HEX_REG_USR; if (is_predicated && !is_preloaded(ctx, rnum)) { tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); } @@ -234,6 +239,8 @@ static void mark_implicit_reg_writes(DisasContext *ctx,= Insn *insn) mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_USR, HEX_REG_USR); + mark_implicit_reg_write(ctx, insn, A_FPOP, HEX_REG_USR); } =20 static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn) diff --git a/tests/tcg/hexagon/overflow.c b/tests/tcg/hexagon/overflow.c new file mode 100644 index 0000000..196fcf7 --- /dev/null +++ b/tests/tcg/hexagon/overflow.c @@ -0,0 +1,107 @@ +/* + * Copyright(c) 2021 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + + +int err; + +static void __check(const char *filename, int line, int x, int expect) +{ + if (x !=3D expect) { + printf("ERROR %s:%d - %d !=3D %d\n", + filename, line, x, expect); + err++; + } +} + +#define check(x, expect) __check(__FILE__, __LINE__, (x), (expect)) + +static int satub(int src, int *p, int *ovf_result) +{ + int result; + int usr; + + /* + * This instruction can set bit 0 (OVF/overflow) in usr + * Clear the bit first, then return that bit to the caller + * + * We also store the src into *p in the same packet, so we + * can ensure the overflow doesn't get set when an exception + * is generated. + */ + asm volatile("r2 =3D usr\n\t" + "r2 =3D clrbit(r2, #0)\n\t" /* clear overflow bit = */ + "usr =3D r2\n\t" + "{\n\t" + " %0 =3D satub(%2)\n\t" + " memw(%3) =3D %2\n\t" + "}\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) + : "r"(src), "r"(p) + : "r2", "usr", "memory"); + *ovf_result =3D (usr & 1); + return result; +} + +int read_usr_overflow(void) +{ + int result; + asm volatile("%0 =3D usr\n\t" : "=3Dr"(result)); + return result & 1; +} + + +jmp_buf jmp_env; +int usr_overflow; + +static void sig_segv(int sig, siginfo_t *info, void *puc) +{ + usr_overflow =3D read_usr_overflow(); + longjmp(jmp_env, 1); +} + +int main() +{ + struct sigaction act; + int ovf; + + /* SIGSEGV test */ + act.sa_sigaction =3D sig_segv; + sigemptyset(&act.sa_mask); + act.sa_flags =3D SA_SIGINFO; + sigaction(SIGSEGV, &act, NULL); + if (setjmp(jmp_env) =3D=3D 0) { + satub(300, 0, &ovf); + } + + act.sa_handler =3D SIG_DFL; + sigemptyset(&act.sa_mask); + act.sa_flags =3D 0; + + check(usr_overflow, 0); + + puts(err ? "FAIL" : "PASS"); + return err ? EXIT_FAILURE : EXIT_SUCCESS; +} diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index b3b5340..a84b003 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -73,6 +73,8 @@ def calculate_attribs(): add_qemu_macro_attrib('fWRITE_P1', 'A_WRITES_PRED_REG') add_qemu_macro_attrib('fWRITE_P2', 'A_WRITES_PRED_REG') add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG') + add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR') + add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR') =20 # Recurse down macros, find attributes from sub-macros macroValues =3D list(macros.values()) diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index c1e1650..8b07a28 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -40,5 +40,6 @@ HEX_TESTS +=3D load_unpack HEX_TESTS +=3D load_align HEX_TESTS +=3D atomics HEX_TESTS +=3D fpstuff +HEX_TESTS +=3D overflow =20 TESTS +=3D $(HEX_TESTS) --=20 2.7.4