From nobody Mon Feb 9 20:34:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1634032301856547.3752964527835; Tue, 12 Oct 2021 02:51:41 -0700 (PDT) Received: from localhost ([::1]:51380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maERg-00051w-Fn for importer@patchew.org; Tue, 12 Oct 2021 05:51:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maE8S-0008KX-VZ for qemu-devel@nongnu.org; Tue, 12 Oct 2021 05:31:51 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:25400) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1maE8Q-00073h-Uz for qemu-devel@nongnu.org; Tue, 12 Oct 2021 05:31:48 -0400 Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Oct 2021 02:31:38 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg03-sd.qualcomm.com with ESMTP; 12 Oct 2021 02:31:38 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D2E7A105B; Tue, 12 Oct 2021 04:31:37 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1634031106; x=1665567106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7dmbcaaEyYOQT2bBKJLadVqscIhGAfiDEvZu2WUH/Aw=; b=Bh0adogNo6YQZIu0WY0fBH8Pq4FHJeyho8vj1SBAdR132K9DaUYXmdIL ikOiWtqSESiQF9eS3hIUOK/ogrfiv6+D7ZMA3uDjxCQP2AMZVjc6GtNIz XBiIHKckfqMqlgVNu8wdax8j9ouYOn332VBFg/A08oQMV+F6V4rsPG/A9 g=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 1/2] Hexagon (target/hexagon) more tcg_constant_* Date: Tue, 12 Oct 2021 04:31:19 -0500 Message-Id: <1634031081-25450-2-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634031081-25450-1-git-send-email-tsimpson@quicinc.com> References: <1634031081-25450-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1634032304455100001 Change additional tcg_const_tl to tcg_constant_tl Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl. However, it is not constant throughout, so we initialize it with tcg_temp_new and replace the first use with the constant value. Inspired-by: Richard Henderson Inspired-by: Philippe Mathieu-Daud Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/hexagon/gen_tcg.h | 9 +++------ target/hexagon/macros.h | 7 +++---- target/hexagon/translate.c | 3 +-- target/hexagon/gen_tcg_funcs.py | 11 ++--------- 4 files changed, 9 insertions(+), 21 deletions(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 0361564..c6f0879 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -66,11 +66,10 @@ } while (0) #define GET_EA_pci \ do { \ - TCGv tcgv_siV =3D tcg_const_tl(siV); \ + TCGv tcgv_siV =3D tcg_constant_tl(siV); \ tcg_gen_mov_tl(EA, RxV); \ gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \ hex_gpr[HEX_REG_CS0 + MuN]); \ - tcg_temp_free(tcgv_siV); \ } while (0) #define GET_EA_pcr(SHIFT) \ do { \ @@ -557,7 +556,7 @@ #define fGEN_TCG_A4_addp_c(SHORTCODE) \ do { \ TCGv_i64 carry =3D tcg_temp_new_i64(); \ - TCGv_i64 zero =3D tcg_const_i64(0); \ + TCGv_i64 zero =3D tcg_constant_i64(0); \ tcg_gen_extu_i32_i64(carry, PxV); \ tcg_gen_andi_i64(carry, carry, 1); \ tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ @@ -565,14 +564,13 @@ tcg_gen_extrl_i64_i32(PxV, carry); \ gen_8bitsof(PxV, PxV); \ tcg_temp_free_i64(carry); \ - tcg_temp_free_i64(zero); \ } while (0) =20 /* r5:4 =3D sub(r1:0, r3:2, p1):carry */ #define fGEN_TCG_A4_subp_c(SHORTCODE) \ do { \ TCGv_i64 carry =3D tcg_temp_new_i64(); \ - TCGv_i64 zero =3D tcg_const_i64(0); \ + TCGv_i64 zero =3D tcg_constant_i64(0); \ TCGv_i64 not_RttV =3D tcg_temp_new_i64(); \ tcg_gen_extu_i32_i64(carry, PxV); \ tcg_gen_andi_i64(carry, carry, 1); \ @@ -582,7 +580,6 @@ tcg_gen_extrl_i64_i32(PxV, carry); \ gen_8bitsof(PxV, PxV); \ tcg_temp_free_i64(carry); \ - tcg_temp_free_i64(zero); \ tcg_temp_free_i64(not_RttV); \ } while (0) =20 diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 44e9b85..5c19cde 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -187,10 +187,10 @@ #ifdef QEMU_GENERATE static inline void gen_pred_cancel(TCGv pred, int slot_num) { - TCGv slot_mask =3D tcg_const_tl(1 << slot_num); + TCGv slot_mask =3D tcg_temp_new(); TCGv tmp =3D tcg_temp_new(); TCGv zero =3D tcg_constant_tl(0); - tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask); + tcg_gen_ori_tl(slot_mask, hex_slot_cancelled, 1 << slot_num); tcg_gen_andi_tl(tmp, pred, 1); tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero, slot_mask, hex_slot_cancelled); @@ -498,10 +498,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val= , int shift) #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) #define fPM_CIRI(REG, IMM, MVAL) \ do { \ - TCGv tcgv_siV =3D tcg_const_tl(siV); \ + TCGv tcgv_siV =3D tcg_constant_tl(siV); \ gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \ hex_gpr[HEX_REG_CS0 + MuN]); \ - tcg_temp_free(tcgv_siV); \ } while (0) #else #define fEA_IMM(IMM) do { EA =3D (IMM); } while (0) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 4f05ce3..e065092 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -491,9 +491,8 @@ static void gen_commit_packet(DisasContext *ctx, Packet= *pkt) * process_store_log will execute the slot 1 store first, * so we only have to probe the store in slot 0 */ - TCGv mem_idx =3D tcg_const_tl(ctx->mem_idx); + TCGv mem_idx =3D tcg_constant_tl(ctx->mem_idx); gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx); - tcg_temp_free(mem_idx); } =20 process_store_log(ctx, pkt); diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index ca8a801..e3d59dd 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -279,15 +279,12 @@ def gen_helper_call_opn(f, tag, regtype, regid, toss,= numregs, i): print("Bad register parse: ",regtype,regid,toss,numregs) =20 def gen_helper_decl_imm(f,immlett): - f.write(" TCGv tcgv_%s =3D tcg_const_tl(%s);\n" % \ + f.write(" TCGv tcgv_%s =3D tcg_constant_tl(%s);\n" % \ (hex_common.imm_name(immlett), hex_common.imm_name(immlett))) =20 def gen_helper_call_imm(f,immlett): f.write(", tcgv_%s" % hex_common.imm_name(immlett)) =20 -def gen_helper_free_imm(f,immlett): - f.write(" tcg_temp_free(tcgv_%s);\n" % hex_common.imm_name(immlett)) - def genptr_dst_write_pair(f, tag, regtype, regid): if ('A_CONDEXEC' in hex_common.attribdict[tag]): f.write(" gen_log_predicated_reg_write_pair(%s%sN, %s%sV, insn-= >slot);\n" % \ @@ -401,7 +398,7 @@ def gen_tcg_func(f, tag, regs, imms): for immlett,bits,immshift in imms: gen_helper_decl_imm(f,immlett) if hex_common.need_part1(tag): - f.write(" TCGv part1 =3D tcg_const_tl(insn->part1);\n") + f.write(" TCGv part1 =3D tcg_constant_tl(insn->part1);\n") if hex_common.need_slot(tag): f.write(" TCGv slot =3D tcg_constant_tl(insn->slot);\n") f.write(" gen_helper_%s(" % (tag)) @@ -424,10 +421,6 @@ def gen_tcg_func(f, tag, regs, imms): if hex_common.need_slot(tag): f.write(", slot") if hex_common.need_part1(tag): f.write(", part1" ) f.write(");\n") - if hex_common.need_part1(tag): - f.write(" tcg_temp_free(part1);\n") - for immlett,bits,immshift in imms: - gen_helper_free_imm(f,immlett) =20 ## Write all the outputs for regtype,regid,toss,numregs in regs: --=20 2.7.4