From nobody Mon Feb 9 14:50:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1633537380326787.3934132985664; Wed, 6 Oct 2021 09:23:00 -0700 (PDT) Received: from localhost ([::1]:54242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mY9h4-0007hN-NW for importer@patchew.org; Wed, 06 Oct 2021 12:22:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52910) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mY99F-0007zz-VB for qemu-devel@nongnu.org; Wed, 06 Oct 2021 11:48:05 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:26606) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1mY99A-0001oR-UT for qemu-devel@nongnu.org; Wed, 06 Oct 2021 11:48:01 -0400 Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 06 Oct 2021 08:47:54 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 06 Oct 2021 08:47:53 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 539BE1167; Wed, 6 Oct 2021 10:47:53 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1633535276; x=1665071276; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pfZORqaE6ltLrlwjVEnj2CTb5b8Hdjy6wdeDIZ4f/8E=; b=Lk+X99UU4GZtlFNOTivtSLnyefbRR4fxwckTffKdLc/PG/Qiog0MKI5w XKrsOOaiR1V0jC16HptOlZz+9WiLgBlwBKojTvB6usYgfwBwOZY+xEXUC clq+Lr4VoKj4quOa+/Vt1L9IwAMcMH/bt4INlbbk9ToTT0HPIpwyCtsuR E=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PULL 3/3] target/hexagon: Use tcg_constant_* Date: Wed, 6 Oct 2021 10:47:51 -0500 Message-Id: <1633535271-17986-4-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1633535271-17986-1-git-send-email-tsimpson@quicinc.com> References: <1633535271-17986-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1633537382237100001 Content-Type: text/plain; charset="utf-8" From: Philippe Mathieu-Daud=C3=A9 Replace uses of tcg_const_* with the allocate and free close together. Inspired-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Taylor Simpson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20211003004750.3608983-3-f4bug@amsat.org> --- target/hexagon/gen_tcg.h | 6 ++---- target/hexagon/macros.h | 3 +-- target/hexagon/genptr.c | 39 +++++++++++++------------------------= -- target/hexagon/translate.c | 26 ++++++++------------------ target/hexagon/gen_tcg_funcs.py | 4 +--- 5 files changed, 25 insertions(+), 53 deletions(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index ee94c90..0361564 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -684,9 +684,8 @@ gen_helper_sfmin(RdV, cpu_env, RsV, RtV) #define fGEN_TCG_F2_sfclass(SHORTCODE) \ do { \ - TCGv imm =3D tcg_const_tl(uiV); \ + TCGv imm =3D tcg_constant_tl(uiV); \ gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ - tcg_temp_free(imm); \ } while (0) #define fGEN_TCG_F2_sffixupn(SHORTCODE) \ gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) @@ -712,9 +711,8 @@ gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) #define fGEN_TCG_F2_dfclass(SHORTCODE) \ do { \ - TCGv imm =3D tcg_const_tl(uiV); \ + TCGv imm =3D tcg_constant_tl(uiV); \ gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ - tcg_temp_free(imm); \ } while (0) #define fGEN_TCG_F2_sfmpy(SHORTCODE) \ gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index ae6663c..44e9b85 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -189,14 +189,13 @@ static inline void gen_pred_cancel(TCGv pred, int slo= t_num) { TCGv slot_mask =3D tcg_const_tl(1 << slot_num); TCGv tmp =3D tcg_temp_new(); - TCGv zero =3D tcg_const_tl(0); + TCGv zero =3D tcg_constant_tl(0); tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask); tcg_gen_andi_tl(tmp, pred, 1); tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero, slot_mask, hex_slot_cancelled); tcg_temp_free(slot_mask); tcg_temp_free(tmp); - tcg_temp_free(zero); } #define PRED_LOAD_CANCEL(PRED, EA) \ gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 7333299..4a21fa5 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -29,7 +29,7 @@ =20 static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int sl= ot) { - TCGv zero =3D tcg_const_tl(0); + TCGv zero =3D tcg_constant_tl(0); TCGv slot_mask =3D tcg_temp_new(); =20 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); @@ -47,7 +47,6 @@ static inline void gen_log_predicated_reg_write(int rnum,= TCGv val, int slot) tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_m= ask); } =20 - tcg_temp_free(zero); tcg_temp_free(slot_mask); } =20 @@ -63,7 +62,7 @@ static inline void gen_log_reg_write(int rnum, TCGv val) static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int = slot) { TCGv val32 =3D tcg_temp_new(); - TCGv zero =3D tcg_const_tl(0); + TCGv zero =3D tcg_constant_tl(0); TCGv slot_mask =3D tcg_temp_new(); =20 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); @@ -92,7 +91,6 @@ static void gen_log_predicated_reg_write_pair(int rnum, T= CGv_i64 val, int slot) } =20 tcg_temp_free(val32); - tcg_temp_free(zero); tcg_temp_free(slot_mask); } =20 @@ -181,9 +179,8 @@ static inline void gen_read_ctrl_reg_pair(DisasContext = *ctx, const int reg_num, tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]); tcg_temp_free(p3_0); } else if (reg_num =3D=3D HEX_REG_PC - 1) { - TCGv pc =3D tcg_const_tl(ctx->base.pc_next); + TCGv pc =3D tcg_constant_tl(ctx->base.pc_next); tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc); - tcg_temp_free(pc); } else if (reg_num =3D=3D HEX_REG_QEMU_PKT_CNT) { TCGv pkt_cnt =3D tcg_temp_new(); TCGv insn_cnt =3D tcg_temp_new(); @@ -331,15 +328,13 @@ static inline void gen_store_conditional4(DisasContex= t *ctx, =20 tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); =20 - one =3D tcg_const_tl(0xff); - zero =3D tcg_const_tl(0); + one =3D tcg_constant_tl(0xff); + zero =3D tcg_constant_tl(0); tmp =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src, ctx->mem_idx, MO_32); tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val, one, zero); - tcg_temp_free(one); - tcg_temp_free(zero); tcg_temp_free(tmp); tcg_gen_br(done); =20 @@ -359,16 +354,14 @@ static inline void gen_store_conditional8(DisasContex= t *ctx, =20 tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); =20 - one =3D tcg_const_i64(0xff); - zero =3D tcg_const_i64(0); + one =3D tcg_constant_i64(0xff); + zero =3D tcg_constant_i64(0); tmp =3D tcg_temp_new_i64(); tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src, ctx->mem_idx, MO_64); tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64, one, zero); tcg_gen_extrl_i64_i32(pred, tmp); - tcg_temp_free_i64(one); - tcg_temp_free_i64(zero); tcg_temp_free_i64(tmp); tcg_gen_br(done); =20 @@ -396,9 +389,8 @@ static inline void gen_store1(TCGv_env cpu_env, TCGv va= ddr, TCGv src, static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx, int slot) { - TCGv tmp =3D tcg_const_tl(src); + TCGv tmp =3D tcg_constant_tl(src); gen_store1(cpu_env, vaddr, tmp, ctx, slot); - tcg_temp_free(tmp); } =20 static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, @@ -411,9 +403,8 @@ static inline void gen_store2(TCGv_env cpu_env, TCGv va= ddr, TCGv src, static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx, int slot) { - TCGv tmp =3D tcg_const_tl(src); + TCGv tmp =3D tcg_constant_tl(src); gen_store2(cpu_env, vaddr, tmp, ctx, slot); - tcg_temp_free(tmp); } =20 static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, @@ -426,9 +417,8 @@ static inline void gen_store4(TCGv_env cpu_env, TCGv va= ddr, TCGv src, static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx, int slot) { - TCGv tmp =3D tcg_const_tl(src); + TCGv tmp =3D tcg_constant_tl(src); gen_store4(cpu_env, vaddr, tmp, ctx, slot); - tcg_temp_free(tmp); } =20 static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, @@ -443,18 +433,15 @@ static inline void gen_store8(TCGv_env cpu_env, TCGv = vaddr, TCGv_i64 src, static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, DisasContext *ctx, int slot) { - TCGv_i64 tmp =3D tcg_const_i64(src); + TCGv_i64 tmp =3D tcg_constant_i64(src); gen_store8(cpu_env, vaddr, tmp, ctx, slot); - tcg_temp_free_i64(tmp); } =20 static TCGv gen_8bitsof(TCGv result, TCGv value) { - TCGv zero =3D tcg_const_tl(0); - TCGv ones =3D tcg_const_tl(0xff); + TCGv zero =3D tcg_constant_tl(0); + TCGv ones =3D tcg_constant_tl(0xff); tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero); - tcg_temp_free(zero); - tcg_temp_free(ones); =20 return result; } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 51930e8..4f05ce3 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -54,9 +54,7 @@ static const char * const hexagon_prednames[] =3D { =20 static void gen_exception_raw(int excp) { - TCGv_i32 helper_tmp =3D tcg_const_i32(excp); - gen_helper_raise_exception(cpu_env, helper_tmp); - tcg_temp_free_i32(helper_tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); } =20 static void gen_exec_counters(DisasContext *ctx) @@ -288,7 +286,7 @@ static void gen_pred_writes(DisasContext *ctx, Packet *= pkt) * write of the predicates. */ if (pkt->pkt_has_endloop) { - TCGv zero =3D tcg_const_tl(0); + TCGv zero =3D tcg_constant_tl(0); TCGv pred_written =3D tcg_temp_new(); for (i =3D 0; i < ctx->preg_log_idx; i++) { int pred_num =3D ctx->preg_log[i]; @@ -299,7 +297,6 @@ static void gen_pred_writes(DisasContext *ctx, Packet *= pkt) hex_new_pred_value[pred_num], hex_pred[pred_num]); } - tcg_temp_free(zero); tcg_temp_free(pred_written); } else { for (i =3D 0; i < ctx->preg_log_idx; i++) { @@ -317,11 +314,9 @@ static void gen_pred_writes(DisasContext *ctx, Packet = *pkt) static void gen_check_store_width(DisasContext *ctx, int slot_num) { if (HEX_DEBUG) { - TCGv slot =3D tcg_const_tl(slot_num); - TCGv check =3D tcg_const_tl(ctx->store_width[slot_num]); + TCGv slot =3D tcg_constant_tl(slot_num); + TCGv check =3D tcg_constant_tl(ctx->store_width[slot_num]); gen_helper_debug_check_store_width(cpu_env, slot, check); - tcg_temp_free(slot); - tcg_temp_free(check); } } =20 @@ -403,9 +398,8 @@ void process_store(DisasContext *ctx, Packet *pkt, int = slot_num) * TCG generation time, we'll use a helper to * avoid branching based on the width at runtime. */ - TCGv slot =3D tcg_const_tl(slot_num); + TCGv slot =3D tcg_constant_tl(slot_num); gen_helper_commit_store(cpu_env, slot); - tcg_temp_free(slot); } } tcg_temp_free(address); @@ -436,7 +430,7 @@ static void process_dczeroa(DisasContext *ctx, Packet *= pkt) if (pkt->pkt_has_dczeroa) { /* Store 32 bytes of zero starting at (addr & ~0x1f) */ TCGv addr =3D tcg_temp_new(); - TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); =20 tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); @@ -448,7 +442,6 @@ static void process_dczeroa(DisasContext *ctx, Packet *= pkt) tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); =20 tcg_temp_free(addr); - tcg_temp_free_i64(zero); } } =20 @@ -510,15 +503,12 @@ static void gen_commit_packet(DisasContext *ctx, Pack= et *pkt) update_exec_counters(ctx, pkt); if (HEX_DEBUG) { TCGv has_st0 =3D - tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); + tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa= ); TCGv has_st1 =3D - tcg_const_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); + tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa= ); =20 /* Handy place to set a breakpoint at the end of execution */ gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); - - tcg_temp_free(has_st0); - tcg_temp_free(has_st1); } =20 if (pkt->pkt_has_cof) { diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 7ceb25b..ca8a801 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -403,7 +403,7 @@ def gen_tcg_func(f, tag, regs, imms): if hex_common.need_part1(tag): f.write(" TCGv part1 =3D tcg_const_tl(insn->part1);\n") if hex_common.need_slot(tag): - f.write(" TCGv slot =3D tcg_const_tl(insn->slot);\n") + f.write(" TCGv slot =3D tcg_constant_tl(insn->slot);\n") f.write(" gen_helper_%s(" % (tag)) i=3D0 ## If there is a scalar result, it is the return type @@ -424,8 +424,6 @@ def gen_tcg_func(f, tag, regs, imms): if hex_common.need_slot(tag): f.write(", slot") if hex_common.need_part1(tag): f.write(", part1" ) f.write(");\n") - if hex_common.need_slot(tag): - f.write(" tcg_temp_free(slot);\n") if hex_common.need_part1(tag): f.write(" tcg_temp_free(part1);\n") for immlett,bits,immshift in imms: --=20 2.7.4