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charset="utf-8" Signed-off-by: Pierre Morel --- linux-headers/linux/kvm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index bcaf66cc4d..38e96ea6f7 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1112,6 +1112,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_BINARY_STATS_FD 203 #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204 #define KVM_CAP_ARM_MTE 205 +#define KVM_CAP_S390_CPU_TOPOLOGY 206 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 --=20 2.25.1 From nobody Tue May 7 14:17:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631800407037944.6423558575458; Thu, 16 Sep 2021 06:53:27 -0700 (PDT) Received: from localhost ([::1]:42370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQrpO-0006Qq-1Q for importer@patchew.org; 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Thu, 16 Sep 2021 13:50:56 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=pp1; bh=SvnJ+x5KP6BN+9WZkQJ4hf0UCAkqjOEEP9ClR/W/P5o=; b=MmzY8GrbbDF605xK1C7rGs4bD82gUdLQO2/X6lxbGNb197thM2vI3J0X+CaAhqB3ohYB 6hlN8K4roZH7xacOGLvO2eybmSoFCRKY2cRF4sEsPHZyoPZA3Cia4wV5iXTO1tIDt170 DA1YozwHzwyAyXNSJedYvc64fWtRhOnvZOXJNETIfz/o5/As7ViLVbYWK/x8Wn8J7gYG ch+Vdt577Z7uQq4/oEmgfnjUXolMUryaVNukwcdZ9gE4gLdx5CGpys6gX4llgsSlFupK 77/Dco4laqhTMtB/GcxWBTU7oolimWxkmW+76kcBmYvB3v+PzqAStbAnYWKs1248avQj mA== From: Pierre Morel To: qemu-s390x@nongnu.org Subject: [PATCH v3 2/4] s390x: kvm: topology: interception of PTF instruction Date: Thu, 16 Sep 2021 15:50:52 +0200 Message-Id: <1631800254-25762-3-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631800254-25762-1-git-send-email-pmorel@linux.ibm.com> References: <1631800254-25762-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: UdFO8AzXPXIA6iOyshlM8v8CFJVxQ0bR X-Proofpoint-ORIG-GUID: fFN2YAfWgTFyrVWvRIuzR6LCyMfaRUTP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109030001 definitions=main-2109160073 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" When the host supports the CPU topology facility, the PTF instruction with function code 2 is interpreted by the SIE, provided that the userland hypervizor activates the interpretation by using the KVM_CAP_S390_CPU_TOPOLOGY KVM extension. The PTF instructions with function code 0 and 1 are intercepted and must be emulated by the userland hypervizor. Signed-off-by: Pierre Morel --- hw/s390x/s390-virtio-ccw.c | 36 ++++++++++++++++++++++++++++++ include/hw/s390x/s390-virtio-ccw.h | 6 +++++ target/s390x/kvm/kvm.c | 15 +++++++++++++ 3 files changed, 57 insertions(+) diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 61aeccb163..894f013139 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -404,6 +404,42 @@ static void s390_pv_prepare_reset(S390CcwMachineState = *ms) s390_pv_prep_reset(); } =20 +int s390_handle_ptf(S390CPU *cpu, uint8_t r1, uintptr_t ra) +{ + CPUS390XState *env =3D &cpu->env; + uint64_t reg =3D env->regs[r1]; + uint8_t fc =3D reg & S390_TOPO_FC_MASK; + + if (!s390_has_feat(S390_FEAT_CONFIGURATION_TOPOLOGY)) { + s390_program_interrupt(env, PGM_OPERATION, ra); + return 0; + } + + if (env->psw.mask & PSW_MASK_PSTATE) { + s390_program_interrupt(env, PGM_PRIVILEGED, ra); + return 0; + } + + if (reg & ~S390_TOPO_FC_MASK) { + s390_program_interrupt(env, PGM_SPECIFICATION, ra); + return 0; + } + + switch (fc) { + case 0: /* Horizontal polarization is already set */ + env->regs[r1] |=3D S390_PTF_REASON_DONE; + return 2; + case 1: /* Vertical polarization is not supported */ + env->regs[r1] |=3D S390_PTF_REASON_NONE; + return 2; + default: + /* Note that fc =3D=3D 2 is interpreted by the SIE */ + s390_program_interrupt(env, PGM_SPECIFICATION, ra); + } + + return 0; +} + static void s390_machine_reset(MachineState *machine) { S390CcwMachineState *ms =3D S390_CCW_MACHINE(machine); diff --git a/include/hw/s390x/s390-virtio-ccw.h b/include/hw/s390x/s390-vir= tio-ccw.h index 3331990e02..ac4b4a92e7 100644 --- a/include/hw/s390x/s390-virtio-ccw.h +++ b/include/hw/s390x/s390-virtio-ccw.h @@ -30,6 +30,12 @@ struct S390CcwMachineState { uint8_t loadparm[8]; }; =20 +#define S390_PTF_REASON_NONE (0x00 << 8) +#define S390_PTF_REASON_DONE (0x01 << 8) +#define S390_PTF_REASON_BUSY (0x02 << 8) +#define S390_TOPO_FC_MASK 0xffUL +int s390_handle_ptf(S390CPU *cpu, uint8_t r1, uintptr_t ra); + struct S390CcwMachineClass { /*< private >*/ MachineClass parent_class; diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 5b1fdb55c4..dd036961fe 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -97,6 +97,7 @@ =20 #define PRIV_B9_EQBS 0x9c #define PRIV_B9_CLP 0xa0 +#define PRIV_B9_PTF 0xa2 #define PRIV_B9_PCISTG 0xd0 #define PRIV_B9_PCILG 0xd2 #define PRIV_B9_RPCIT 0xd3 @@ -362,6 +363,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) kvm_vm_enable_cap(s, KVM_CAP_S390_USER_SIGP, 0); kvm_vm_enable_cap(s, KVM_CAP_S390_VECTOR_REGISTERS, 0); kvm_vm_enable_cap(s, KVM_CAP_S390_USER_STSI, 0); + kvm_vm_enable_cap(s, KVM_CAP_S390_CPU_TOPOLOGY, 0); if (ri_allowed()) { if (kvm_vm_enable_cap(s, KVM_CAP_S390_RI, 0) =3D=3D 0) { cap_ri =3D 1; @@ -1452,6 +1454,16 @@ static int kvm_mpcifc_service_call(S390CPU *cpu, str= uct kvm_run *run) } } =20 +static int kvm_handle_ptf(S390CPU *cpu, struct kvm_run *run) +{ + uint8_t r1 =3D (run->s390_sieic.ipb >> 20) & 0x0f; + int ret; + + ret =3D s390_handle_ptf(cpu, r1, RA_IGNORED); + setcc(cpu, ret); + return 0; +} + static int handle_b9(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1) { int r =3D 0; @@ -1469,6 +1481,9 @@ static int handle_b9(S390CPU *cpu, struct kvm_run *ru= n, uint8_t ipa1) case PRIV_B9_RPCIT: r =3D kvm_rpcit_service_call(cpu, run); break; + case PRIV_B9_PTF: + r =3D kvm_handle_ptf(cpu, run); + break; case PRIV_B9_EQBS: /* just inject exception */ r =3D -1; --=20 2.25.1 From nobody Tue May 7 14:17:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1631800717607347.2414972205328; Thu, 16 Sep 2021 06:58:37 -0700 (PDT) Received: from localhost ([::1]:55938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQruO-0007Vp-Em for importer@patchew.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=pmorel@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: 0 X-Spam_score: -0.1 X-Spam_bar: / X-Spam_report: (-0.1 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, david@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, pasic@linux.ibm.com, borntraeger@de.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1631800718069100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We use new objects to have a dynamic administration of the CPU topology. The highest level object in this implementation is the s390 book and in this first implementation of CPU topology for S390 we have a single book. The book is built as a SYSBUS bridge during the CPU initialization. Every object under this single book will be build dynamically immediately after a CPU has be realized if it is needed. The CPU will fill the sockets once after the other, according to the number of core per socket defined during the smp parsing. Each CPU inside a socket will be represented by a bit in a 64bit unsigned long. Set on plug and clear on unplug of a CPU. Signed-off-by: Pierre Morel --- hw/s390x/cpu-topology.c | 353 ++++++++++++++++++++++++++++++++ hw/s390x/meson.build | 1 + hw/s390x/s390-virtio-ccw.c | 4 + include/hw/s390x/cpu-topology.h | 67 ++++++ target/s390x/cpu.h | 47 +++++ 5 files changed, 472 insertions(+) create mode 100644 hw/s390x/cpu-topology.c create mode 100644 include/hw/s390x/cpu-topology.h diff --git a/hw/s390x/cpu-topology.c b/hw/s390x/cpu-topology.c new file mode 100644 index 0000000000..f0ffd86a4f --- /dev/null +++ b/hw/s390x/cpu-topology.c @@ -0,0 +1,353 @@ +/* + * CPU Topology + * + * Copyright 2021 IBM Corp. + * Author(s): Pierre Morel + + * This work is licensed under the terms of the GNU GPL, version 2 or (at + * your option) any later version. See the COPYING file in the top-level + * directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "hw/sysbus.h" +#include "hw/s390x/cpu-topology.h" +#include "hw/qdev-properties.h" +#include "hw/boards.h" +#include "qemu/typedefs.h" +#include "target/s390x/cpu.h" +#include "hw/s390x/s390-virtio-ccw.h" + +static S390TopologyCores *s390_create_cores(S390TopologySocket *socket, + int origin) +{ + DeviceState *dev; + S390TopologyCores *cores; + const MachineState *ms =3D MACHINE(qdev_get_machine()); + + if (socket->bus->num_children >=3D ms->smp.cores) { + return NULL; + } + + dev =3D qdev_new(TYPE_S390_TOPOLOGY_CORES); + qdev_realize_and_unref(dev, socket->bus, &error_fatal); + + cores =3D S390_TOPOLOGY_CORES(dev); + cores->origin =3D origin; + socket->cnt +=3D 1; + + return cores; +} + +static S390TopologySocket *s390_create_socket(S390TopologyBook *book, int = id) +{ + DeviceState *dev; + S390TopologySocket *socket; + const MachineState *ms =3D MACHINE(qdev_get_machine()); + + if (book->bus->num_children >=3D ms->smp.sockets) { + return NULL; + } + + dev =3D qdev_new(TYPE_S390_TOPOLOGY_SOCKET); + qdev_realize_and_unref(dev, book->bus, &error_fatal); + + socket =3D S390_TOPOLOGY_SOCKET(dev); + socket->socket_id =3D id; + book->cnt++; + + return socket; +} + +/* + * s390_get_cores: + * @socket: the socket to search into + * @origin: the origin specified for the S390TopologyCores + * + * returns a pointer to a S390TopologyCores structure within a socket havi= ng + * the specified origin. + * First search if the socket is already containing the S390TopologyCores + * structure and if not create one with this origin. + */ +static S390TopologyCores *s390_get_cores(S390TopologySocket *socket, int o= rigin) +{ + S390TopologyCores *cores; + BusChild *kid; + + QTAILQ_FOREACH(kid, &socket->bus->children, sibling) { + cores =3D S390_TOPOLOGY_CORES(kid->child); + if (cores->origin =3D=3D origin) { + return cores; + } + } + return s390_create_cores(socket, origin); +} + +/* + * s390_get_socket: + * @book: The book to search into + * @socket_id: the identifier of the socket to search for + * + * returns a pointer to a S390TopologySocket structure within a book having + * the specified socket_id. + * First search if the book is already containing the S390TopologySocket + * structure and if not create one with this socket_id. + */ +static S390TopologySocket *s390_get_socket(S390TopologyBook *book, + int socket_id) +{ + S390TopologySocket *socket; + BusChild *kid; + + QTAILQ_FOREACH(kid, &book->bus->children, sibling) { + socket =3D S390_TOPOLOGY_SOCKET(kid->child); + if (socket->socket_id =3D=3D socket_id) { + return socket; + } + } + return s390_create_socket(book, socket_id); +} + +/* + * s390_topology_new_cpu: + * @core_id: the core ID is machine wide + * + * We have a single book returned by s390_get_topology(), + * then we build the hierarchy on demand. + * Note that we do not destroy the hierarchy on error creating + * an entry in the topology, we just keep it empty. + * We do not need to worry about not finding a topology level + * entry this would have been caught during smp parsing. + */ +void s390_topology_new_cpu(int core_id) +{ + const MachineState *ms =3D MACHINE(qdev_get_machine()); + S390TopologyBook *book; + S390TopologySocket *socket; + S390TopologyCores *cores; + int cores_per_socket, sock_idx; + int origin, bit; + + book =3D s390_get_topology(); + + cores_per_socket =3D ms->smp.max_cpus / ms->smp.sockets; + + sock_idx =3D (core_id / cores_per_socket); + socket =3D s390_get_socket(book, sock_idx); + + /* + * We assume that all CPU are identical IFL, shared and + * horizontal topology, the only reason to have several + * S390TopologyCores is to have more than 64 CPUs. + */ + origin =3D 64 * (core_id / 64); + + cores =3D s390_get_cores(socket, origin); + + bit =3D 63 - (core_id - origin); + set_bit(bit, &cores->mask); + cores->origin =3D origin; +} + +/* + * Setting the first topology: 1 book, 1 socket + * This is enough for 64 cores if the topology is flat (single socket) + */ +void s390_topology_setup(MachineState *ms) +{ + DeviceState *dev; + + /* Create BOOK bridge device */ + dev =3D qdev_new(TYPE_S390_TOPOLOGY_BOOK); + object_property_add_child(qdev_get_machine(), + TYPE_S390_TOPOLOGY_BOOK, OBJECT(dev)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); +} + +S390TopologyBook *s390_get_topology(void) +{ + static S390TopologyBook *book; + + if (!book) { + book =3D S390_TOPOLOGY_BOOK( + object_resolve_path(TYPE_S390_TOPOLOGY_BOOK, NULL)); + assert(book !=3D NULL); + } + + return book; +} + +/* --- CORES Definitions --- */ + +static Property s390_topology_cores_properties[] =3D { + DEFINE_PROP_BOOL("dedicated", S390TopologyCores, dedicated, false), + DEFINE_PROP_UINT8("polarity", S390TopologyCores, polarity, + S390_TOPOLOGY_POLARITY_H), + DEFINE_PROP_UINT8("cputype", S390TopologyCores, cputype, + S390_TOPOLOGY_CPU_TYPE), + DEFINE_PROP_UINT16("origin", S390TopologyCores, origin, 0), + DEFINE_PROP_UINT64("mask", S390TopologyCores, mask, 0), + DEFINE_PROP_UINT8("id", S390TopologyCores, id, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void cpu_cores_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); + + device_class_set_props(dc, s390_topology_cores_properties); + hc->unplug =3D qdev_simple_device_unplug_cb; + dc->bus_type =3D TYPE_S390_TOPOLOGY_SOCKET_BUS; + dc->desc =3D "topology cpu entry"; +} + +static const TypeInfo cpu_cores_info =3D { + .name =3D TYPE_S390_TOPOLOGY_CORES, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(S390TopologyCores), + .class_init =3D cpu_cores_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + } +}; + +/* --- SOCKETS Definitions --- */ +static Property s390_topology_socket_properties[] =3D { + DEFINE_PROP_UINT8("socket_id", S390TopologySocket, socket_id, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static char *socket_bus_get_dev_path(DeviceState *dev) +{ + S390TopologySocket *socket =3D S390_TOPOLOGY_SOCKET(dev); + DeviceState *book =3D dev->parent_bus->parent; + char *id =3D qdev_get_dev_path(book); + char *ret; + + if (id) { + ret =3D g_strdup_printf("%s:%02d", id, socket->socket_id); + g_free(id); + } else { + ret =3D g_strdup_printf("_:%02d", socket->socket_id); + } + + return ret; +} + +static void socket_bus_class_init(ObjectClass *oc, void *data) +{ + BusClass *k =3D BUS_CLASS(oc); + + k->get_dev_path =3D socket_bus_get_dev_path; + k->max_dev =3D S390_MAX_SOCKETS; +} + +static const TypeInfo socket_bus_info =3D { + .name =3D TYPE_S390_TOPOLOGY_SOCKET_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D 0, + .class_init =3D socket_bus_class_init, +}; + +static void s390_socket_device_realize(DeviceState *dev, Error **errp) +{ + S390TopologySocket *socket =3D S390_TOPOLOGY_SOCKET(dev); + BusState *bus; + + bus =3D qbus_create(TYPE_S390_TOPOLOGY_SOCKET_BUS, dev, + TYPE_S390_TOPOLOGY_SOCKET_BUS); + qbus_set_hotplug_handler(bus, OBJECT(dev)); + socket->bus =3D bus; +} + +static void socket_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); + + hc->unplug =3D qdev_simple_device_unplug_cb; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->bus_type =3D TYPE_S390_TOPOLOGY_BOOK_BUS; + dc->realize =3D s390_socket_device_realize; + device_class_set_props(dc, s390_topology_socket_properties); + dc->desc =3D "topology socket"; +} + +static const TypeInfo socket_info =3D { + .name =3D TYPE_S390_TOPOLOGY_SOCKET, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(S390TopologySocket), + .class_init =3D socket_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + } +}; + +static char *book_bus_get_dev_path(DeviceState *dev) +{ + return g_strdup_printf("00"); +} + +static void book_bus_class_init(ObjectClass *oc, void *data) +{ + BusClass *k =3D BUS_CLASS(oc); + + k->get_dev_path =3D book_bus_get_dev_path; + k->max_dev =3D S390_MAX_BOOKS; +} + +static const TypeInfo book_bus_info =3D { + .name =3D TYPE_S390_TOPOLOGY_BOOK_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D 0, + .class_init =3D book_bus_class_init, +}; + +static void s390_book_device_realize(DeviceState *dev, Error **errp) +{ + S390TopologyBook *book =3D S390_TOPOLOGY_BOOK(dev); + BusState *bus; + + bus =3D qbus_create(TYPE_S390_TOPOLOGY_BOOK_BUS, dev, + TYPE_S390_TOPOLOGY_BOOK_BUS); + qbus_set_hotplug_handler(bus, OBJECT(dev)); + book->bus =3D bus; +} + +static void book_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); + + hc->unplug =3D qdev_simple_device_unplug_cb; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->realize =3D s390_book_device_realize; + dc->desc =3D "topology book"; +} + +static const TypeInfo book_info =3D { + .name =3D TYPE_S390_TOPOLOGY_BOOK, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(S390TopologyBook), + .class_init =3D book_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + } +}; + +static void topology_register(void) +{ + type_register_static(&cpu_cores_info); + type_register_static(&socket_bus_info); + type_register_static(&socket_info); + type_register_static(&book_bus_info); + type_register_static(&book_info); +} + +type_init(topology_register); diff --git a/hw/s390x/meson.build b/hw/s390x/meson.build index 59485ddfaa..0f3424220b 100644 --- a/hw/s390x/meson.build +++ b/hw/s390x/meson.build @@ -2,6 +2,7 @@ s390x_ss =3D ss.source_set() s390x_ss.add(files( 'ap-bridge.c', 'ap-device.c', + 'cpu-topology.c', 'ccw-device.c', 'css-bridge.c', 'css.c', diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 894f013139..ec46a72a98 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -42,6 +42,7 @@ #include "sysemu/sysemu.h" #include "hw/s390x/pv.h" #include "migration/blocker.h" +#include "hw/s390x/cpu-topology.h" =20 static Error *pv_mig_blocker; =20 @@ -88,6 +89,7 @@ static void s390_init_cpus(MachineState *machine) /* initialize possible_cpus */ mc->possible_cpu_arch_ids(machine); =20 + s390_topology_setup(machine); for (i =3D 0; i < machine->smp.cpus; i++) { s390x_new_cpu(machine->cpu_type, i, &error_fatal); } @@ -305,6 +307,8 @@ static void s390_cpu_plug(HotplugHandler *hotplug_dev, g_assert(!ms->possible_cpus->cpus[cpu->env.core_id].cpu); ms->possible_cpus->cpus[cpu->env.core_id].cpu =3D OBJECT(dev); =20 + s390_topology_new_cpu(cpu->env.core_id); + if (dev->hotplugged) { raise_irq_cpu_hotplug(); } diff --git a/include/hw/s390x/cpu-topology.h b/include/hw/s390x/cpu-topolog= y.h new file mode 100644 index 0000000000..f7ccba3725 --- /dev/null +++ b/include/hw/s390x/cpu-topology.h @@ -0,0 +1,67 @@ +/* + * CPU Topology + * + * Copyright 2021 IBM Corp. + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at + * your option) any later version. See the COPYING file in the top-level + * directory. + */ +#ifndef HW_S390X_CPU_TOPOLOGY_H +#define HW_S390X_CPU_TOPOLOGY_H + +#include "hw/qdev-core.h" +#include "qom/object.h" + +#define S390_TOPOLOGY_CPU_TYPE 0x03 + +#define S390_TOPOLOGY_POLARITY_H 0x00 +#define S390_TOPOLOGY_POLARITY_VL 0x01 +#define S390_TOPOLOGY_POLARITY_VM 0x02 +#define S390_TOPOLOGY_POLARITY_VH 0x03 + +#define TYPE_S390_TOPOLOGY_CORES "topology cores" +struct S390TopologyCores { + DeviceState parent_obj; + uint8_t id; + bool dedicated; + uint8_t polarity; + uint8_t cputype; + uint16_t origin; + uint64_t mask; + int cnt; +}; +typedef struct S390TopologyCores S390TopologyCores; +OBJECT_DECLARE_SIMPLE_TYPE(S390TopologyCores, S390_TOPOLOGY_CORES) + +#define TYPE_S390_TOPOLOGY_SOCKET "topology socket" +#define TYPE_S390_TOPOLOGY_SOCKET_BUS "socket-bus" +struct S390TopologySocket { + DeviceState parent_obj; + BusState *bus; + uint8_t socket_id; + int cnt; +}; +typedef struct S390TopologySocket S390TopologySocket; +OBJECT_DECLARE_SIMPLE_TYPE(S390TopologySocket, S390_TOPOLOGY_SOCKET) +#define S390_MAX_SOCKETS 4 + +#define TYPE_S390_TOPOLOGY_BOOK "topology book" +#define TYPE_S390_TOPOLOGY_BOOK_BUS "book-bus" +struct S390TopologyBook { + SysBusDevice parent_obj; + BusState *bus; + uint8_t book_id; + int cnt; +}; +typedef struct S390TopologyBook S390TopologyBook; +OBJECT_DECLARE_SIMPLE_TYPE(S390TopologyBook, S390_TOPOLOGY_BOOK) +#define S390_MAX_BOOKS 1 + +S390TopologyBook *s390_init_topology(void); + +S390TopologyBook *s390_get_topology(void); +void s390_topology_setup(MachineState *ms); +void s390_topology_new_cpu(int core_id); + +#endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index b26ae8fff2..d10792f3bb 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -564,6 +564,53 @@ typedef union SysIB { } SysIB; QEMU_BUILD_BUG_ON(sizeof(SysIB) !=3D 4096); =20 +/* CPU type Topology List Entry */ +typedef struct SysIBTl_cpu { + uint8_t nl; + uint8_t reserved0[3]; + uint8_t reserved1:5; + uint8_t dedicated:1; + uint8_t polarity:2; + uint8_t type; + uint16_t origin; + uint64_t mask; +} SysIBTl_cpu; +QEMU_BUILD_BUG_ON(sizeof(SysIBTl_cpu) !=3D 16); + +/* Container type Topology List Entry */ +typedef struct SysIBTl_container { + uint8_t nl; + uint8_t reserved[6]; + uint8_t id; +} QEMU_PACKED SysIBTl_container; +QEMU_BUILD_BUG_ON(sizeof(SysIBTl_container) !=3D 8); + +/* Generic Topology List Entry */ +typedef union SysIBTl_entry { + uint8_t nl; + SysIBTl_container container; + SysIBTl_cpu cpu; +} SysIBTl_entry; + +#define TOPOLOGY_NR_MAG 6 +#define TOPOLOGY_NR_MAG6 0 +#define TOPOLOGY_NR_MAG5 1 +#define TOPOLOGY_NR_MAG4 2 +#define TOPOLOGY_NR_MAG3 3 +#define TOPOLOGY_NR_MAG2 4 +#define TOPOLOGY_NR_MAG1 5 +/* Configuration topology */ +typedef struct SysIB_151x { + uint8_t res0[2]; + uint16_t length; + uint8_t mag[TOPOLOGY_NR_MAG]; + uint8_t res1; + uint8_t mnest; + uint32_t res2; + SysIBTl_entry tle[0]; +} SysIB_151x; +QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) !=3D 16); + /* MMU defines */ #define ASCE_ORIGIN (~0xfffULL) /* segment table origin = */ #define ASCE_SUBSPACE 0x200 /* subspace group control = */ --=20 2.25.1 From nobody Tue May 7 14:17:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" The handling of STSI is enhanced with the interception of the function code 15 for storing CPU topology. Using the objects built during the pluging of CPU, we build the SYSIB 15_1_x structures. With this patch the maximum MNEST level is 2, this is also the only level allowed and only SYSIB 15_1_2 will be built. Signed-off-by: Pierre Morel --- target/s390x/kvm/kvm.c | 101 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index dd036961fe..0a5f2aced2 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -52,6 +52,7 @@ #include "hw/s390x/s390-virtio-ccw.h" #include "hw/s390x/s390-virtio-hcall.h" #include "hw/s390x/pv.h" +#include "hw/s390x/cpu-topology.h" =20 #ifndef DEBUG_KVM #define DEBUG_KVM 0 @@ -1908,6 +1909,102 @@ static void insert_stsi_3_2_2(S390CPU *cpu, __u64 a= ddr, uint8_t ar) } } =20 +static int stsi_15_container(void *p, int nl, int id) +{ + SysIBTl_container *tle =3D (SysIBTl_container *)p; + + tle->nl =3D nl; + tle->id =3D id; + + return sizeof(*tle); +} + +static int stsi_15_cpus(void *p, S390TopologyCores *cd) +{ + SysIBTl_cpu *tle =3D (SysIBTl_cpu *)p; + + tle->nl =3D 0; + tle->dedicated =3D cd->dedicated; + tle->polarity =3D cd->polarity; + tle->type =3D cd->cputype; + tle->origin =3D cd->origin; + tle->mask =3D cd->mask; + + return sizeof(*tle); +} + +static int set_socket(const MachineState *ms, void *p, + S390TopologySocket *socket) +{ + BusChild *kid; + int l, len =3D 0; + + len +=3D stsi_15_container(p, 1, socket->socket_id); + p +=3D len; + + QTAILQ_FOREACH_REVERSE(kid, &socket->bus->children, sibling) { + l =3D stsi_15_cpus(p, S390_TOPOLOGY_CORES(kid->child)); + p +=3D l; + len +=3D l; + } + return len; +} + +static void insert_stsi_15_1_2(const MachineState *ms, void *p) +{ + S390TopologyBook *book; + SysIB_151x *sysib; + BusChild *kid; + int level =3D 2; + int len, l; + + sysib =3D (SysIB_151x *)p; + sysib->mnest =3D level; + sysib->mag[TOPOLOGY_NR_MAG2] =3D ms->smp.sockets; + sysib->mag[TOPOLOGY_NR_MAG1] =3D ms->smp.cores; + + book =3D s390_get_topology(); + len =3D sizeof(SysIB_151x); + p +=3D len; + + QTAILQ_FOREACH_REVERSE(kid, &book->bus->children, sibling) { + l =3D set_socket(ms, p, S390_TOPOLOGY_SOCKET(kid->child)); + p +=3D l; + len +=3D l; + } + + sysib->length =3D len; +} + +static void insert_stsi_15_1_x(S390CPU *cpu, int sel2, __u64 addr, uint8_t= ar) +{ + const MachineState *machine =3D MACHINE(qdev_get_machine()); + void *p; + int ret, cc; + + /* + * Until the SCLP STSI Facility reporting the MNEST value is used, + * a sel2 value of 2 is the only value allowed in STSI 15.1.x. + */ + if (sel2 !=3D 2) { + setcc(cpu, 3); + return; + } + + p =3D g_malloc0(TARGET_PAGE_SIZE); + + insert_stsi_15_1_2(machine, p); + + if (s390_is_pv()) { + ret =3D s390_cpu_pv_mem_write(cpu, 0, p, TARGET_PAGE_SIZE); + } else { + ret =3D s390_cpu_virt_mem_write(cpu, addr, ar, p, TARGET_PAGE_SIZE= ); + } + cc =3D ret ? 3 : 0; + setcc(cpu, cc); + g_free(p); +} + static int handle_stsi(S390CPU *cpu) { CPUState *cs =3D CPU(cpu); @@ -1921,6 +2018,10 @@ static int handle_stsi(S390CPU *cpu) /* Only sysib 3.2.2 needs post-handling for now. */ insert_stsi_3_2_2(cpu, run->s390_stsi.addr, run->s390_stsi.ar); return 0; + case 15: + insert_stsi_15_1_x(cpu, run->s390_stsi.sel2, run->s390_stsi.addr, + run->s390_stsi.ar); + return 0; default: return 0; } --=20 2.25.1