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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630000779597100001 Commit vector stores (masked and scatter/gather) Log vector register writes Add the execution counters to the debug log Histogram instructions Signed-off-by: Taylor Simpson --- target/hexagon/helper.h | 13 +++ target/hexagon/op_helper.c | 235 +++++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 246 insertions(+), 2 deletions(-) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index ca201fb..c99c1c1 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -23,6 +23,7 @@ DEF_HELPER_1(debug_start_packet, void, env) DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int= , int) DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int) DEF_HELPER_2(commit_store, void, env, int) +DEF_HELPER_1(commit_hvx_stores, void, env) DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32) DEF_HELPER_FLAGS_1(fbrev, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_3(sfrecipa, i64, env, f32, f32) @@ -89,3 +90,15 @@ DEF_HELPER_4(sffms_lib, f32, env, f32, f32, f32) =20 DEF_HELPER_3(dfmpyfix, f64, env, f64, f64) DEF_HELPER_4(dfmpyhh, f64, env, f64, f64, f64) + +/* Histogram instructions */ +DEF_HELPER_1(vhist, void, env) +DEF_HELPER_1(vhistq, void, env) +DEF_HELPER_1(vwhist256, void, env) +DEF_HELPER_1(vwhist256q, void, env) +DEF_HELPER_1(vwhist256_sat, void, env) +DEF_HELPER_1(vwhist256q_sat, void, env) +DEF_HELPER_1(vwhist128, void, env) +DEF_HELPER_1(vwhist128q, void, env) +DEF_HELPER_2(vwhist128m, void, env, s32) +DEF_HELPER_2(vwhist128qm, void, env, s32) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 61d5cde..3219765 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -27,6 +27,8 @@ #include "arch.h" #include "hex_arch_types.h" #include "fma_emu.h" +#include "mmvec/mmvec.h" +#include "mmvec/macros.h" =20 #define SF_BIAS 127 #define SF_MANTBITS 23 @@ -164,6 +166,52 @@ void HELPER(commit_store)(CPUHexagonState *env, int sl= ot_num) } } =20 +void HELPER(commit_hvx_stores)(CPUHexagonState *env) +{ + uintptr_t ra =3D GETPC(); + int i; + + /* Normal (possibly masked) vector store */ + for (i =3D 0; i < VSTORES_MAX; i++) { + if (env->vstore_pending[i]) { + env->vstore_pending[i] =3D 0; + target_ulong va =3D env->vstore[i].va; + int size =3D env->vstore[i].size; + for (int j =3D 0; j < size; j++) { + if (test_bit(j, env->vstore[i].mask)) { + cpu_stb_data_ra(env, va + j, env->vstore[i].data.ub[j]= , ra); + } + } + } + } + + /* Scatter store */ + if (env->vtcm_pending) { + env->vtcm_pending =3D false; + if (env->vtcm_log.op) { + /* Need to perform the scatter read/modify/write at commit tim= e */ + if (env->vtcm_log.op_size =3D=3D 2) { + SCATTER_OP_WRITE_TO_MEM(uint16_t); + } else if (env->vtcm_log.op_size =3D=3D 4) { + /* Word Scatter +=3D */ + SCATTER_OP_WRITE_TO_MEM(uint32_t); + } else { + g_assert_not_reached(); + } + } else { + for (i =3D 0; i < env->vtcm_log.size; i++) { + if (test_bit(i, env->vtcm_log.mask)) { + cpu_stb_data_ra(env, env->vtcm_log.va[i], + env->vtcm_log.data.ub[i], ra); + clear_bit(i, env->vtcm_log.mask); + env->vtcm_log.data.ub[i] =3D 0; + } + + } + } + } +} + static void print_store(CPUHexagonState *env, int slot) { if (!(env->slot_cancelled & (1 << slot))) { @@ -242,9 +290,10 @@ void HELPER(debug_commit_end)(CPUHexagonState *env, in= t has_st0, int has_st1) HEX_DEBUG_LOG("Next PC =3D " TARGET_FMT_lx "\n", env->next_PC); HEX_DEBUG_LOG("Exec counters: pkt =3D " TARGET_FMT_lx ", insn =3D " TARGET_FMT_lx - "\n", + ", hvx =3D " TARGET_FMT_lx "\n", env->gpr[HEX_REG_QEMU_PKT_CNT], - env->gpr[HEX_REG_QEMU_INSN_CNT]); + env->gpr[HEX_REG_QEMU_INSN_CNT], + env->gpr[HEX_REG_QEMU_HVX_CNT]); =20 } =20 @@ -1165,6 +1214,188 @@ float64 HELPER(dfmpyhh)(CPUHexagonState *env, float= 64 RxxV, return RxxV; } =20 +/* Histogram instructions */ + +static inline MMVector vhist_input(CPUHexagonState *env) +{ + /* + * There isn't a 1-1 mapping of register numbers for tmp_VRegs + * They are allocated on an as-needed basis during translation. + * + * The rules for histogram instructions are that there can only + * be one tmp register assigned in the packet. + * So, we check that there is only one bit in the mask, and + * this means the tmp we need will be at index 0. + */ + VRegMask vsel =3D env->VRegs_updated_tmp; + g_assert(ctpop32(vsel) =3D=3D 1); + env->VRegs_updated_tmp =3D 0; + return env->tmp_VRegs[0]; +} + +void HELPER(vhist)(CPUHexagonState *env) +{ + MMVector input =3D vhist_input(env); + + for (int lane =3D 0; lane < 8; lane++) { + for (int i =3D 0; i < sizeof(MMVector) / 8; ++i) { + unsigned char value =3D input.ub[(sizeof(MMVector) / 8) * lane= + i]; + unsigned char regno =3D value >> 3; + unsigned char element =3D value & 7; + + env->VRegs[regno].uh[(sizeof(MMVector) / 16) * lane + element]= ++; + } + } +} + +void HELPER(vhistq)(CPUHexagonState *env) +{ + MMVector input =3D vhist_input(env); + + for (int lane =3D 0; lane < 8; lane++) { + for (int i =3D 0; i < sizeof(MMVector) / 8; ++i) { + unsigned char value =3D input.ub[(sizeof(MMVector) / 8) * lane= + i]; + unsigned char regno =3D value >> 3; + unsigned char element =3D value & 7; + + if (fGETQBIT(env->qtmp, sizeof(MMVector) / 8 * lane + i)) { + env->VRegs[regno].uh[ + (sizeof(MMVector) / 16) * lane + element]++; + } + } + } +} + +void HELPER(vwhist256)(CPUHexagonState *env) +{ + MMVector input =3D vhist_input(env); + + for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + unsigned int bucket =3D fGETUBYTE(0, input.h[i]); + unsigned int weight =3D fGETUBYTE(1, input.h[i]); + unsigned int vindex =3D (bucket >> 3) & 0x1F; + unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); + + env->VRegs[vindex].uh[elindex] =3D + env->VRegs[vindex].uh[elindex] + weight; + } +} + +void HELPER(vwhist256q)(CPUHexagonState *env) +{ + MMVector input =3D vhist_input(env); + + for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + unsigned int bucket =3D fGETUBYTE(0, input.h[i]); + unsigned int weight =3D fGETUBYTE(1, input.h[i]); + unsigned int vindex =3D (bucket >> 3) & 0x1F; + unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); + + if (fGETQBIT(env->qtmp, 2 * i)) { + env->VRegs[vindex].uh[elindex] =3D + env->VRegs[vindex].uh[elindex] + weight; + } + } +} + +void HELPER(vwhist256_sat)(CPUHexagonState *env) +{ + MMVector input =3D vhist_input(env); + + for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + unsigned int bucket =3D fGETUBYTE(0, input.h[i]); + unsigned int weight =3D fGETUBYTE(1, input.h[i]); + unsigned int vindex =3D (bucket >> 3) & 0x1F; + unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); + + env->VRegs[vindex].uh[elindex] =3D + fVSATUH(env->VRegs[vindex].uh[elindex] + weight); + } +} + +void HELPER(vwhist256q_sat)(CPUHexagonState *env) +{ + MMVector input =3D vhist_input(env); + + for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + unsigned int bucket =3D fGETUBYTE(0, input.h[i]); + unsigned int weight =3D fGETUBYTE(1, input.h[i]); + unsigned int vindex =3D (bucket >> 3) & 0x1F; + unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); + + if (fGETQBIT(env->qtmp, 2 * i)) { + env->VRegs[vindex].uh[elindex] =3D + fVSATUH(env->VRegs[vindex].uh[elindex] + weight); + } + } +} + +void HELPER(vwhist128)(CPUHexagonState *env) +{ + MMVector input =3D vhist_input(env); + + for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + unsigned int bucket =3D fGETUBYTE(0, input.h[i]); + unsigned int weight =3D fGETUBYTE(1, input.h[i]); + unsigned int vindex =3D (bucket >> 3) & 0x1F; + unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); + + env->VRegs[vindex].uw[elindex] =3D + env->VRegs[vindex].uw[elindex] + weight; + } +} + +void HELPER(vwhist128q)(CPUHexagonState *env) +{ + MMVector input =3D vhist_input(env); + + for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + unsigned int bucket =3D fGETUBYTE(0, input.h[i]); + unsigned int weight =3D fGETUBYTE(1, input.h[i]); + unsigned int vindex =3D (bucket >> 3) & 0x1F; + unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); + + if (fGETQBIT(env->qtmp, 2 * i)) { + env->VRegs[vindex].uw[elindex] =3D + env->VRegs[vindex].uw[elindex] + weight; + } + } +} + +void HELPER(vwhist128m)(CPUHexagonState *env, int32_t uiV) +{ + MMVector input =3D vhist_input(env); + + for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + unsigned int bucket =3D fGETUBYTE(0, input.h[i]); + unsigned int weight =3D fGETUBYTE(1, input.h[i]); + unsigned int vindex =3D (bucket >> 3) & 0x1F; + unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); + + if ((bucket & 1) =3D=3D uiV) { + env->VRegs[vindex].uw[elindex] =3D + env->VRegs[vindex].uw[elindex] + weight; + } + } +} + +void HELPER(vwhist128qm)(CPUHexagonState *env, int32_t uiV) +{ + MMVector input =3D vhist_input(env); + + for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + unsigned int bucket =3D fGETUBYTE(0, input.h[i]); + unsigned int weight =3D fGETUBYTE(1, input.h[i]); + unsigned int vindex =3D (bucket >> 3) & 0x1F; + unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); + + if (((bucket & 1) =3D=3D uiV) && fGETQBIT(env->qtmp, 2 * i)) { + env->VRegs[vindex].uw[elindex] =3D + env->VRegs[vindex].uw[elindex] + weight; + } + } +} + static void cancel_slot(CPUHexagonState *env, uint32_t slot) { HEX_DEBUG_LOG("Slot %d cancelled\n", slot); --=20 2.7.4