From nobody Sun Dec 14 02:00:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625528168765188.13555781718526; Mon, 5 Jul 2021 16:36:08 -0700 (PDT) Received: from localhost ([::1]:56630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m0Y8E-0005qk-Jw for importer@patchew.org; Mon, 05 Jul 2021 19:36:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m0Y6u-0003CF-Jr for qemu-devel@nongnu.org; Mon, 05 Jul 2021 19:34:44 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:53655) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1m0Y6s-0004a7-8e for qemu-devel@nongnu.org; Mon, 05 Jul 2021 19:34:44 -0400 Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 05 Jul 2021 16:34:38 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg01-sd.qualcomm.com with ESMTP; 05 Jul 2021 16:34:38 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id CFD32AF1; Mon, 5 Jul 2021 18:34:37 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1625528082; x=1657064082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=olsr8usaTTmzx7MME4JrirfUnlDzgRjlSLHjenPeJcA=; b=BJBb3s8Ocy9kPqG+9cjlCUwf0AqZspK2EFehItJ/0OQuyulnT/7lTRsq t+83j5ORmtDmSDpGk14tp7cFr+ByTnfa2DTfjrGlbKHlY0A9vqOQKSzH9 YP/yT74cFaS+wJ/EWts49j8tNDkVOJUgN8aRHchduyzxR5wDyKhWmqKMn U=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 01/20] Hexagon HVX (target/hexagon) README Date: Mon, 5 Jul 2021 18:34:15 -0500 Message-Id: <1625528074-19440-2-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1625528074-19440-1-git-send-email-tsimpson@quicinc.com> References: <1625528074-19440-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, peter.maydell@linaro.org, bcain@quicinc.com, richard.henderson@linaro.org, tsimpson@quicinc.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1625528170828100001 Signed-off-by: Taylor Simpson --- target/hexagon/README | 83 +++++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/target/hexagon/README b/target/hexagon/README index b0b2435..9a57802 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -1,9 +1,13 @@ Hexagon is Qualcomm's very long instruction word (VLIW) digital signal -processor(DSP). +processor(DSP). We also support Hexagon Vector eXtensions (HVX). HVX +is a wide vector coprocessor designed for high performance computer vision, +image processing, machine learning, and other workloads. =20 The following versions of the Hexagon core are supported Scalar core: v67 https://developer.qualcomm.com/downloads/qualcomm-hexagon-v67-programm= er-s-reference-manual + HVX extension: v66 + https://developer.qualcomm.com/downloads/qualcomm-hexagon-v66-hvx-prog= rammer-s-reference-manual =20 We presented an overview of the project at the 2019 KVM Forum. https://kvmforum2019.sched.com/event/Tmwc/qemu-hexagon-automatic-trans= lation-of-the-isa-manual-pseudcode-to-tiny-code-instructions-of-a-vliw-arch= itecture-niccolo-izzo-revng-taylor-simpson-qualcomm-innovation-center @@ -124,6 +128,73 @@ There are also cases where we brute force the TCG code= generation. Instructions with multiple definitions are examples. These require special handling because qemu helpers can only return a single value. =20 +For HVX vectors, the generator behaves slightly differently. The wide vec= tors +won't fit in a TCGv or TCGv_i64, so we pass TCGv_ptr variables to pass the +address to helper functions. Here's an example for an HVX vector-add-word +istruction. + static void generate_V6_vaddw( + CPUHexagonState *env, + DisasContext *ctx, + Insn *insn, + Packet *pkt) + { + const int VdN =3D insn->regno[0]; + const intptr_t VdV_off =3D + offsetof(CPUHexagonState, + future_VRegs[VdN]); + TCGv_ptr VdV =3D tcg_temp_local_new_ptr(); + tcg_gen_addi_ptr(VdV, cpu_env, VdV_off); + const int VuN =3D insn->regno[1]; + const intptr_t VuV_off =3D + vreg_src_off(ctx, VuN); + TCGv_ptr VuV =3D tcg_temp_local_new_ptr(); + const int VvN =3D insn->regno[2]; + const intptr_t VvV_off =3D + vreg_src_off(ctx, VvN); + TCGv_ptr VvV =3D tcg_temp_local_new_ptr(); + tcg_gen_addi_ptr(VuV, cpu_env, VuV_off); + tcg_gen_addi_ptr(VvV, cpu_env, VvV_off); + TCGv slot =3D tcg_const_tl(insn->slot); + gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV, slot); + tcg_temp_free(slot); + gen_log_vreg_write(VdV_off, VdN, EXT_DFL, insn->slot, false, pkt->= pkt_has_vhist); + ctx_log_vreg_write(ctx, VdN, EXT_DFL, false); + tcg_temp_free_ptr(VdV); + tcg_temp_free_ptr(VuV); + tcg_temp_free_ptr(VvV); + } + +Notice that we also generate a variable named _off for each opera= nd of +the instruction. This makes it easy to override the instruction semantics= with +functions from tcg-op-gved.h. Here's the override for this instruction. + #define fGEN_TCG_V6_vaddw(SHORTCODE) \ + tcg_gen_gvec_add(MO_32, VdV_off, VuV_off, VvV_off, \ + sizeof(MMVector), sizeof(MMVector)) + +Finally, we notice that the override doesn't use the TCGv_ptr variables, so +we don't generate them when an override is present. Here is what we gener= ate +when the override is present. + static void generate_V6_vaddw( + CPUHexagonState *env, + DisasContext *ctx, + Insn *insn, + Packet *pkt) + { + const int VdN =3D insn->regno[0]; + const intptr_t VdV_off =3D + offsetof(CPUHexagonState, + future_VRegs[VdN]); + const int VuN =3D insn->regno[1]; + const intptr_t VuV_off =3D + vreg_src_off(ctx, VuN); + const int VvN =3D insn->regno[2]; + const intptr_t VvV_off =3D + vreg_src_off(ctx, VvN); + fGEN_TCG_V6_vaddw({ fHIDE(int i;) fVFOREACH(32, i) { VdV.w[i] =3D = VuV.w[i] + VvV.w[i] ; } }); + gen_log_vreg_write(VdV_off, VdN, EXT_DFL, insn->slot, false, pkt->= pkt_has_vhist); + ctx_log_vreg_write(ctx, VdN, EXT_DFL, false); + } + In addition to instruction semantics, we use a generator to create the dec= ode tree. This generation is also a two step process. The first step is to r= un target/hexagon/gen_dectree_import.c to produce @@ -140,6 +211,7 @@ runtime information for each thread and contains stuff = like the GPR and predicate registers. =20 macros.h +mmvec/macros.h =20 The Hexagon arch lib relies heavily on macros for the instruction semantic= s. This is a great advantage for qemu because we can override them for differ= ent @@ -203,6 +275,15 @@ During runtime, the following fields in CPUHexagonStat= e (see cpu.h) are used pred_written boolean indicating if predicate was written mem_log_stores record of the stores (indexed by slot) =20 +For Hexagon Vector eXtensions (HVX), the following fields are used + future_VRegs + tmp_VRegs + future_ZRegs + ZRegs_updated + VRegs_updated_tmp + VRegs_updated + VRegs_select + *** Debugging *** =20 You can turn on a lot of debugging by changing the HEX_DEBUG macro to 1 in --=20 2.7.4