From nobody Sun Dec 14 06:17:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625528780335889.5700805543858; Mon, 5 Jul 2021 16:46:20 -0700 (PDT) Received: from localhost ([::1]:34202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m0YI6-0003Bl-T9 for importer@patchew.org; Mon, 05 Jul 2021 19:46:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m0Y76-0003fa-LB for qemu-devel@nongnu.org; Mon, 05 Jul 2021 19:34:56 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:37367) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1m0Y74-0004gT-DW for qemu-devel@nongnu.org; Mon, 05 Jul 2021 19:34:56 -0400 Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 05 Jul 2021 16:34:39 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 05 Jul 2021 16:34:38 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id EE65811BC; Mon, 5 Jul 2021 18:34:37 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1625528094; x=1657064094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6ZXpHousDRgYCAM62TGKmSVyU/og7FVfu8y9tlDD8bw=; b=VNHLJVTnlz2aQJEJMI5xCNmQfJk818WYbi6W7mzlNcDmLkLBdynyKrWh l6Phm7+dhBx4vkFQD5jc960iCbdhIwp74HfOGUpXX1/Czt1QhRt6QpkNO ZIqNXHdsoGx/0ddHaDlsQlgo+12VhgupE4s28dn3l7ymsS3vbuQ7nvlh2 8=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 11/20] Hexagon HVX (target/hexagon) instruction utility functions Date: Mon, 5 Jul 2021 18:34:25 -0500 Message-Id: <1625528074-19440-12-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1625528074-19440-1-git-send-email-tsimpson@quicinc.com> References: <1625528074-19440-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, peter.maydell@linaro.org, bcain@quicinc.com, richard.henderson@linaro.org, tsimpson@quicinc.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1625528782188100001 Functions to support scatter/gather Add new file to target/hexagon/meson.build Signed-off-by: Taylor Simpson --- target/hexagon/arch.h | 1 + target/hexagon/mmvec/system_ext_mmvec.h | 35 ++++++++++ target/hexagon/arch.c | 9 +++ target/hexagon/mmvec/system_ext_mmvec.c | 119 ++++++++++++++++++++++++++++= ++++ target/hexagon/meson.build | 1 + 5 files changed, 165 insertions(+) create mode 100644 target/hexagon/mmvec/system_ext_mmvec.h create mode 100644 target/hexagon/mmvec/system_ext_mmvec.c diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h index 7091806..133cb6d 100644 --- a/target/hexagon/arch.h +++ b/target/hexagon/arch.h @@ -24,6 +24,7 @@ extern const uint8_t rLPS_table_64x4[64][4]; extern const uint8_t AC_next_state_MPS_64[64]; extern const uint8_t AC_next_state_LPS_64[64]; =20 +uint32_t count_leading_ones_2(uint16_t src); uint64_t interleave(uint32_t odd, uint32_t even); uint64_t deinterleave(uint64_t src); int32_t conv_round(int32_t a, int n); diff --git a/target/hexagon/mmvec/system_ext_mmvec.h b/target/hexagon/mmvec= /system_ext_mmvec.h new file mode 100644 index 0000000..d103191 --- /dev/null +++ b/target/hexagon/mmvec/system_ext_mmvec.h @@ -0,0 +1,35 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_SYSTEM_EXT_MMVEC_H +#define HEXAGON_SYSTEM_EXT_MMVEC_H + +void mem_load_vector(CPUHexagonState *env, target_ulong vaddr, + int size, uint8_t *data); +void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, + int slot, uint8_t *data); +void mem_store_vector(CPUHexagonState *env, target_ulong vaddr, + int slot, int size, + uint8_t *data, uint8_t *mask, bool invert); +void mem_vector_scatter_init(CPUHexagonState *env, int slot, + target_ulong base_vaddr, int length, + int element_size); +void mem_vector_gather_init(CPUHexagonState *env, int slot, + target_ulong base_vaddr, int length, + int element_size); + +#endif diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index 68a55b3..b2ff905 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -118,6 +118,15 @@ const uint8_t AC_next_state_LPS_64[64] =3D { 37, 38, 38, 63 }; =20 +uint32_t count_leading_ones_2(uint16_t src) +{ + int ret; + for (ret =3D 0; src & 0x8000; src <<=3D 1) { + ret++; + } + return ret; +} + #define BITS_MASK_8 0x5555555555555555ULL #define PAIR_MASK_8 0x3333333333333333ULL #define NYBL_MASK_8 0x0f0f0f0f0f0f0f0fULL diff --git a/target/hexagon/mmvec/system_ext_mmvec.c b/target/hexagon/mmvec= /system_ext_mmvec.c new file mode 100644 index 0000000..fbd7505 --- /dev/null +++ b/target/hexagon/mmvec/system_ext_mmvec.c @@ -0,0 +1,119 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "cpu.h" +#include "mmvec/system_ext_mmvec.h" + +void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, + int slot, uint8_t *data) +{ + size_t size =3D sizeof(MMVector); + + /* + * If it's a gather store update store data from temporary register + * and clear flag + */ + memcpy(data, &env->tmp_VRegs[0].ub[0], size); + env->VRegs_updated_tmp =3D 0; + env->gather_issued =3D false; + + env->vstore_pending[slot] =3D 1; + env->vstore[slot].va =3D vaddr; + env->vstore[slot].size =3D size; + memcpy(&env->vstore[slot].data.ub[0], data, size); + + /* On a gather store, overwrite the store mask to emulate dropped gath= ers */ + memcpy(&env->vstore[slot].mask.ub[0], &env->vtcm_log.mask.ub[0], size); +} + +void mem_store_vector(CPUHexagonState *env, target_ulong vaddr, int slot, + int size, uint8_t *data, uint8_t *mask, bool invert) +{ + if (!size) { + return; + } + + if (env->is_gather_store_insn) { + mem_gather_store(env, vaddr, slot, data); + return; + } + + env->vstore_pending[slot] =3D 1; + env->vstore[slot].va =3D vaddr; + env->vstore[slot].size =3D size; + memcpy(&env->vstore[slot].data.ub[0], data, size); + if (!mask) { + memset(&env->vstore[slot].mask.ub[0], invert ? 0 : -1, size); + } else if (invert) { + for (int i =3D 0; i < size; i++) { + env->vstore[slot].mask.ub[i] =3D !mask[i]; + } + } else { + memcpy(&env->vstore[slot].mask.ub[0], mask, size); + } +} + +void mem_load_vector(CPUHexagonState *env, target_ulong vaddr, + int size, uint8_t *data) +{ + for (int i =3D 0; i < size; i++) { + get_user_u8(data[i], vaddr); + vaddr++; + } +} + +void mem_vector_scatter_init(CPUHexagonState *env, int slot, + target_ulong base_vaddr, + int length, int element_size) +{ + int i; + + for (i =3D 0; i < sizeof(MMVector); i++) { + env->vtcm_log.data.ub[i] =3D 0; + env->vtcm_log.mask.ub[i] =3D 0; + } + + env->vtcm_pending =3D true; + env->vtcm_log.op =3D false; + env->vtcm_log.op_size =3D 0; + env->vtcm_log.size =3D sizeof(MMVector); +} + +void mem_vector_gather_init(CPUHexagonState *env, int slot, + target_ulong base_vaddr, + int length, int element_size) +{ + int i; + + for (i =3D 0; i < sizeof(MMVector); i++) { + env->vtcm_log.data.ub[i] =3D 0; + env->vtcm_log.mask.ub[i] =3D 0; + env->vtcm_log.va[i] =3D 0; + env->tmp_VRegs[0].ub[i] =3D 0; + } + env->vtcm_log.op =3D false; + env->vtcm_log.op_size =3D 0; + + /* + * Temp reg gets updated + * This allows store .new to grab the correct result + */ + env->VRegs_updated_tmp =3D 1; + env->gather_issued =3D true; +} diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 6fd9360..ed292b4 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -173,6 +173,7 @@ hexagon_ss.add(files( 'printinsn.c', 'arch.c', 'fma_emu.c', + 'mmvec/system_ext_mmvec.c', )) =20 target_arch +=3D {'hexagon': hexagon_ss} --=20 2.7.4