From nobody Mon Feb 9 01:19:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1621489551; cv=none; d=zohomail.com; s=zohoarc; b=MFvCkc0jZEBMB0sJhMQqWoChU0IDmA4Cyw7rdSCLbYq7pknWZeZH3RTXIE9J4zsy8k2ANXSWuuxDZnMTDP2oA8EQO+zA5mOAbSavasCjNJ+LMsljQFzKFuIFHmx9wDxdK8g2rtzYg8/oMJDIsSdTu6fr7P4Xo8IC7cWK1ZJ1D5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621489551; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=FcgXh/5ZLkg6gqoR/K978alvP4C44NXYKohs5cuR3C4=; b=P7yqt24uGSvq2WEO8kyTBVUI3qma8+hdQtDLIhUUMu3ATNFYBFVCVEvLfonfDNmYjh4NeGXjlyqIjSRA/9mK6JPA1pOCq/9IkOaxSDGOGxmFBA7RTEV22UbMeTTG4/JaZOz/MvnEnG2zJMjw2BFuCzjoVN1Gc426HzRLqi00r0c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621489551593507.9132014867773; Wed, 19 May 2021 22:45:51 -0700 (PDT) Received: from localhost ([::1]:53470 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljbVG-0007on-Gt for importer@patchew.org; Thu, 20 May 2021 01:45:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTF-00055s-S0 for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:45 -0400 Received: from mga06.intel.com ([134.134.136.31]:7412) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTD-000736-St for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:45 -0400 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 22:43:41 -0700 Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.172]) by fmsmga008.fm.intel.com with ESMTP; 19 May 2021 22:43:38 -0700 IronPort-SDR: 0YcZntxZmMWRXg8pRQQm0s7XZMDFAX7yp5qF5sOeoLj9p8PNgeq6Fjx8BLVVMLvNEcSh3U2Z7r 0NhFSf9HeipQ== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="262370940" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="262370940" IronPort-SDR: ar0N9UY+xr+HJvOfO2f4rKmGcGWNRQKYWaLSpahhINj89QNu6AMCJASfI73y9NJnpau60EGe0A iKFoBQEL3N9A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="440160306" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v8 3/6] target/i386: Enable XSAVES support for CET states Date: Thu, 20 May 2021 13:57:08 +0800 Message-Id: <1621490231-4765-4-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> References: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=weijiang.yang@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET Shadow Stack(SHSTK) and Indirect Branch Tracking(IBT) are enumerated via CPUID.(EAX=3D07H,ECX=3D0H):ECX[bit 7] and EDX[bit 20] respectively. Two CET bits (bit 11 and 12) are defined in MSR_IA32_XSS for XSAVES. They correspond to CET states in user and supervisor mode respectively. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 42 +++++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 21 +++++++++++++++++++++ 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d74d68e319..bae827c8d5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1064,6 +1064,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, [FEAT_XSAVE_XSS_LO] =3D { .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "cet-u", + "cet-s", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, .cpuid =3D { .eax =3D 0xD, .needs_ecx =3D true, @@ -1472,7 +1482,7 @@ typedef struct ExtSaveArea { } ExtSaveArea; =20 /* CPUID feature bits available in XSS */ -#define CPUID_XSTATE_XSS_MASK 0 +#define CPUID_XSTATE_XSS_MASK (XSTATE_CET_U_MASK) =20 static const ExtSaveArea x86_ext_save_areas[] =3D { [XSTATE_FP_BIT] =3D { @@ -1517,6 +1527,19 @@ static const ExtSaveArea x86_ext_save_areas[] =3D { { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .offset =3D offsetof(X86XSaveArea, pkru_state), .size =3D sizeof(XSavePKRU) }, + [XSTATE_CET_U_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + /* + * The features enabled in XSS MSR always use compacted format + * to store the data, in this case .offset =3D=3D 0. And CET bits + * fall into this category. + */ + .offset =3D 0, + .size =3D sizeof(XSavesCETU) }, + [XSTATE_CET_S_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + .offset =3D 0, + .size =3D sizeof(XSavesCETS) }, }; =20 static uint32_t xsave_area_size(uint64_t mask, bool compacted) @@ -6486,6 +6509,23 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) if (env->features[esa->feature] & esa->bits) { mask |=3D (1ULL << i); } + + /* + * Both CET SHSTK and IBT feature requires XSAVES support, but two + * features can be controlled independently by kernel, and we only + * have one correlated bit set in x86_ext_save_areas, so if either + * of two features is enabled, we set the XSAVES support bit to ma= ke + * the enabled feature work. + */ + if (i =3D=3D XSTATE_CET_U_BIT || i =3D=3D XSTATE_CET_S_BIT) { + uint64_t ecx =3D env->features[FEAT_7_0_ECX]; + uint64_t edx =3D env->features[FEAT_7_0_EDX]; + + if ((ecx & CPUID_7_0_ECX_CET_SHSTK) || + (edx & CPUID_7_0_EDX_CET_IBT)) { + mask |=3D (1ULL << i); + } + } } =20 env->features[FEAT_XSAVE_XCR0_LO] =3D mask & CPUID_XSTATE_XCR0_MASK; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 42f835d455..593a2d6823 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -492,6 +492,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_CET_U_BIT 11 +#define XSTATE_CET_S_BIT 12 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -502,6 +504,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) +#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) =20 /* CPUID feature bits available in XCR0 */ #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ @@ -761,6 +765,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_WAITPKG (1U << 5) /* Additional AVX-512 Vector Byte Manipulation Instruction */ #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) +/* CET SHSTK feature */ +#define CPUID_7_0_ECX_CET_SHSTK (1U << 7) /* Galois Field New Instructions */ #define CPUID_7_0_ECX_GFNI (1U << 8) /* Vector AES Instructions */ @@ -800,6 +806,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_SERIALIZE (1U << 14) /* TSX Suspend Load Address Tracking instruction */ #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) +/* CET IBT feature */ +#define CPUID_7_0_EDX_CET_IBT (1U << 20) /* AVX512_FP16 instruction */ #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) /* Speculation Control */ @@ -1301,6 +1309,19 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 11: User mode CET state */ +typedef struct XSavesCETU { + uint64_t u_cet; + uint64_t user_ssp; +} XSavesCETU; + +/* Ext. save area 12: Supervisor mode CET state */ +typedef struct XSavesCETS { + uint64_t kernel_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; +} XSavesCETS; + typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; X86XSaveHeader header; --=20 2.26.2